Patent
US 10,454,472BOOTSTRAP CAPACITOR OVER-VOLTAGE MANAGEMENT CIRCUIT
David C. Reusch, John Glaser, Michael A. de Rooij, Stephen A. Soffen
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 10,454,472Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1B-1 D show the current paths thr ou gh the circuit during various time periods, and FIG. lE is timing diagram for the circuit. [00026]
FIG. 2 shows the gate-to-source waveforms of a GaN based design with the conventional bootstrapping circuit of
FIG. 3E is a timing diagram for the circuit. [00028]
FIG. 4A shows a second embodiment of the circuit of the invention with a turn- on diode,
FIG. 5 shows a third embodiment of the circuit of the invention with a second shunt diode. [00030]
FIG. 6 shows a fourth embodiment of the invention, in which the invention is extended to converters with a higher number of levels. [00031]
FIG. 7A shows a fifth embodiment of the circuit of the invention with a shunt transistor substituted for the shunt diode, and
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An electrical c ircuit arranged in a half bridge topology, comprising: a high side transistor and a low side transistor, each having a source, a drain and a gate, the source of the high side transistor being electrically connected to the drain of the low side transistor at a first node; a gate driver electrically coupled to the gate of the high side transistor; a bootstrap capacitor electrically coupled in parallel with the gate driver; a shunt diode having a cathode and an anode, the cathode of the shunt diode being connected to the capacitor at a second node, and the anode of the shunt diode being connected to ground, the shunt diode providing a low voltage drop path to charge the bootstrap capacitor; and a shunt resistor electrically connected between the first node and the second node, to decouple the shunt diode from the first node, and to control and limit current through the shunt diode. Currently amended
The electrical circuit of claim 1, wherein the high side and low side transistors are enhancement mode GaN transistors. Original
The electrical circuit of claim 1, further comprising a tu rn on diode electrically connected in anti-parallel with the shunt resistor. Original
The electrical circuit of claim 1, further comprising additional shunt diodes and shunt resistors connected to respective sources of additional high side transistors. Original
The electrical circuit of claim 1, wherein the shunt diode is substituted with a shunt transistor, the shunt transistor being driven with a gate drive signal that is complementary to the signal applied to the gate of the low side transistor. Original
The electrical circuit of claim 1, wherein the gate driver, the bootstrap capacitor, the shunt diode and the shunt resistor ar e all fully integrated monolithically into a single integrated circuit. Original
The electrical circuit of claim 1, wherein the integrated circuit includes the high side and low side transistors and passive components of the circuit. Original
A method of avoiding gate drive overvoltage in an electrical circuit arranged in a half bridge configuration, wherein the half bridge of the electrical circuit comprises a high side transistor and a low side transistor, each having a source, a drain and a gate, the source of the high side transistor being electrically connected to the drain of the low side transistor at a first node, and the electrical circuit further comprises a gate driver electrically coupled to the gate of the high side transistor, and a bootstrap capacitor electrically coupled in parallel with the gate driver, wherein the method comprises charging the bootstrap capacitor, when both the high side and low side transistors are of f, th r ough a shunt network electrically connected in parallel to the low side transistor, the shunt network providing a low voltage drop charging path as compared to the reverse voltage drop of the low side transistor, wherein the shunt network comprises: a shunt diode having a cathode and an anode, the cathode of the shunt diode being connected to the capacitor at a second node, and the anode of the shunt diode being connected to ground, and a shunt resistor electrically connected between the first node and the second node to decouple the shunt diode from the first node, and to control and limit current through the shunt diode. Currently amended
The method of claim 10, wherein the high side and low side transistors are enhancement mode GaN transistors. Original
The method o f claim 10, wherein the shunt network further comprises a turn on diode electrically connected in anti-parallel with respect to the shunt resistor. Original
The method of claim 10, wherein the shunt network further comprises a turn on resistor in series with the turn on diode. Original
The method of claim 10, wherein the shunt diode is substituted with a shunt transistor, and the shunt transistor is driven with a gate drive signal that is complementary to the signal applied to the gate of the low side transistor. Original
Layer stacks claimed or described, ordered top of device to substrate.
half bridge circuit with bootstrap capacitor over-voltage management
Materials described outside the worked examples.
enhancement mode GaN transistor
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 7A shows a fifth embodiment of the circuit of the invention with a shunt transistor substituted for the shunt diode, and
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
GaN transistor reverse conduction voltage during dead-time | 2–2.5 V | enhancement mode GaN transistor |
bootstrap diode forward voltage drop | 0.3–0.7 V |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,454,472Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1B-1 D show the current paths thr ou gh the circuit during various time periods, and FIG. lE is timing diagram for the circuit. [00026]
FIG. 2 shows the gate-to-source waveforms of a GaN based design with the conventional bootstrapping circuit of
FIG. 3E is a timing diagram for the circuit. [00028]
FIG. 4A shows a second embodiment of the circuit of the invention with a turn- on diode,
FIG. 5 shows a third embodiment of the circuit of the invention with a second shunt diode. [00030]
FIG. 6 shows a fourth embodiment of the invention, in which the invention is extended to converters with a higher number of levels. [00031]
FIG. 7A shows a fifth embodiment of the circuit of the invention with a shunt transistor substituted for the shunt diode, and
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An electrical c ircuit arranged in a half bridge topology, comprising: a high side transistor and a low side transistor, each having a source, a drain and a gate, the source of the high side transistor being electrically connected to the drain of the low side transistor at a first node; a gate driver electrically coupled to the gate of the high side transistor; a bootstrap capacitor electrically coupled in parallel with the gate driver; a shunt diode having a cathode and an anode, the cathode of the shunt diode being connected to the capacitor at a second node, and the anode of the shunt diode being connected to ground, the shunt diode providing a low voltage drop path to charge the bootstrap capacitor; and a shunt resistor electrically connected between the first node and the second node, to decouple the shunt diode from the first node, and to control and limit current through the shunt diode. Currently amended
The electrical circuit of claim 1, wherein the high side and low side transistors are enhancement mode GaN transistors. Original
The electrical circuit of claim 1, further comprising a tu rn on diode electrically connected in anti-parallel with the shunt resistor. Original
The electrical circuit of claim 1, further comprising additional shunt diodes and shunt resistors connected to respective sources of additional high side transistors. Original
The electrical circuit of claim 1, wherein the shunt diode is substituted with a shunt transistor, the shunt transistor being driven with a gate drive signal that is complementary to the signal applied to the gate of the low side transistor. Original
The electrical circuit of claim 1, wherein the gate driver, the bootstrap capacitor, the shunt diode and the shunt resistor ar e all fully integrated monolithically into a single integrated circuit. Original
The electrical circuit of claim 1, wherein the integrated circuit includes the high side and low side transistors and passive components of the circuit. Original
A method of avoiding gate drive overvoltage in an electrical circuit arranged in a half bridge configuration, wherein the half bridge of the electrical circuit comprises a high side transistor and a low side transistor, each having a source, a drain and a gate, the source of the high side transistor being electrically connected to the drain of the low side transistor at a first node, and the electrical circuit further comprises a gate driver electrically coupled to the gate of the high side transistor, and a bootstrap capacitor electrically coupled in parallel with the gate driver, wherein the method comprises charging the bootstrap capacitor, when both the high side and low side transistors are of f, th r ough a shunt network electrically connected in parallel to the low side transistor, the shunt network providing a low voltage drop charging path as compared to the reverse voltage drop of the low side transistor, wherein the shunt network comprises: a shunt diode having a cathode and an anode, the cathode of the shunt diode being connected to the capacitor at a second node, and the anode of the shunt diode being connected to ground, and a shunt resistor electrically connected between the first node and the second node to decouple the shunt diode from the first node, and to control and limit current through the shunt diode. Currently amended
The method of claim 10, wherein the high side and low side transistors are enhancement mode GaN transistors. Original
The method o f claim 10, wherein the shunt network further comprises a turn on diode electrically connected in anti-parallel with respect to the shunt resistor. Original
The method of claim 10, wherein the shunt network further comprises a turn on resistor in series with the turn on diode. Original
The method of claim 10, wherein the shunt diode is substituted with a shunt transistor, and the shunt transistor is driven with a gate drive signal that is complementary to the signal applied to the gate of the low side transistor. Original
Layer stacks claimed or described, ordered top of device to substrate.
half bridge circuit with bootstrap capacitor over-voltage management
Materials described outside the worked examples.
enhancement mode GaN transistor
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 7A shows a fifth embodiment of the circuit of the invention with a shunt transistor substituted for the shunt diode, and
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
GaN transistor reverse conduction voltage during dead-time | 2–2.5 V | enhancement mode GaN transistor |
bootstrap diode forward voltage drop | 0.3–0.7 V |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,454,472Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1B-1 D show the current paths thr ou gh the circuit during various time periods, and FIG. lE is timing diagram for the circuit. [00026]
FIG. 2 shows the gate-to-source waveforms of a GaN based design with the conventional bootstrapping circuit of
FIG. 3E is a timing diagram for the circuit. [00028]
FIG. 4A shows a second embodiment of the circuit of the invention with a turn- on diode,
FIG. 5 shows a third embodiment of the circuit of the invention with a second shunt diode. [00030]
FIG. 6 shows a fourth embodiment of the invention, in which the invention is extended to converters with a higher number of levels. [00031]
FIG. 7A shows a fifth embodiment of the circuit of the invention with a shunt transistor substituted for the shunt diode, and
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An electrical c ircuit arranged in a half bridge topology, comprising: a high side transistor and a low side transistor, each having a source, a drain and a gate, the source of the high side transistor being electrically connected to the drain of the low side transistor at a first node; a gate driver electrically coupled to the gate of the high side transistor; a bootstrap capacitor electrically coupled in parallel with the gate driver; a shunt diode having a cathode and an anode, the cathode of the shunt diode being connected to the capacitor at a second node, and the anode of the shunt diode being connected to ground, the shunt diode providing a low voltage drop path to charge the bootstrap capacitor; and a shunt resistor electrically connected between the first node and the second node, to decouple the shunt diode from the first node, and to control and limit current through the shunt diode. Currently amended
The electrical circuit of claim 1, wherein the high side and low side transistors are enhancement mode GaN transistors. Original
The electrical circuit of claim 1, further comprising a tu rn on diode electrically connected in anti-parallel with the shunt resistor. Original
The electrical circuit of claim 1, further comprising additional shunt diodes and shunt resistors connected to respective sources of additional high side transistors. Original
The electrical circuit of claim 1, wherein the shunt diode is substituted with a shunt transistor, the shunt transistor being driven with a gate drive signal that is complementary to the signal applied to the gate of the low side transistor. Original
The electrical circuit of claim 1, wherein the gate driver, the bootstrap capacitor, the shunt diode and the shunt resistor ar e all fully integrated monolithically into a single integrated circuit. Original
The electrical circuit of claim 1, wherein the integrated circuit includes the high side and low side transistors and passive components of the circuit. Original
A method of avoiding gate drive overvoltage in an electrical circuit arranged in a half bridge configuration, wherein the half bridge of the electrical circuit comprises a high side transistor and a low side transistor, each having a source, a drain and a gate, the source of the high side transistor being electrically connected to the drain of the low side transistor at a first node, and the electrical circuit further comprises a gate driver electrically coupled to the gate of the high side transistor, and a bootstrap capacitor electrically coupled in parallel with the gate driver, wherein the method comprises charging the bootstrap capacitor, when both the high side and low side transistors are of f, th r ough a shunt network electrically connected in parallel to the low side transistor, the shunt network providing a low voltage drop charging path as compared to the reverse voltage drop of the low side transistor, wherein the shunt network comprises: a shunt diode having a cathode and an anode, the cathode of the shunt diode being connected to the capacitor at a second node, and the anode of the shunt diode being connected to ground, and a shunt resistor electrically connected between the first node and the second node to decouple the shunt diode from the first node, and to control and limit current through the shunt diode. Currently amended
The method of claim 10, wherein the high side and low side transistors are enhancement mode GaN transistors. Original
The method o f claim 10, wherein the shunt network further comprises a turn on diode electrically connected in anti-parallel with respect to the shunt resistor. Original
The method of claim 10, wherein the shunt network further comprises a turn on resistor in series with the turn on diode. Original
The method of claim 10, wherein the shunt diode is substituted with a shunt transistor, and the shunt transistor is driven with a gate drive signal that is complementary to the signal applied to the gate of the low side transistor. Original
Layer stacks claimed or described, ordered top of device to substrate.
half bridge circuit with bootstrap capacitor over-voltage management
Materials described outside the worked examples.
enhancement mode GaN transistor
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 7A shows a fifth embodiment of the circuit of the invention with a shunt transistor substituted for the shunt diode, and
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
GaN transistor reverse conduction voltage during dead-time | 2–2.5 V | enhancement mode GaN transistor |
bootstrap diode forward voltage drop | 0.3–0.7 V |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,454,472Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1B-1 D show the current paths thr ou gh the circuit during various time periods, and FIG. lE is timing diagram for the circuit. [00026]
FIG. 2 shows the gate-to-source waveforms of a GaN based design with the conventional bootstrapping circuit of
FIG. 3E is a timing diagram for the circuit. [00028]
FIG. 4A shows a second embodiment of the circuit of the invention with a turn- on diode,
FIG. 5 shows a third embodiment of the circuit of the invention with a second shunt diode. [00030]
FIG. 6 shows a fourth embodiment of the invention, in which the invention is extended to converters with a higher number of levels. [00031]
FIG. 7A shows a fifth embodiment of the circuit of the invention with a shunt transistor substituted for the shunt diode, and
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An electrical c ircuit arranged in a half bridge topology, comprising: a high side transistor and a low side transistor, each having a source, a drain and a gate, the source of the high side transistor being electrically connected to the drain of the low side transistor at a first node; a gate driver electrically coupled to the gate of the high side transistor; a bootstrap capacitor electrically coupled in parallel with the gate driver; a shunt diode having a cathode and an anode, the cathode of the shunt diode being connected to the capacitor at a second node, and the anode of the shunt diode being connected to ground, the shunt diode providing a low voltage drop path to charge the bootstrap capacitor; and a shunt resistor electrically connected between the first node and the second node, to decouple the shunt diode from the first node, and to control and limit current through the shunt diode. Currently amended
The electrical circuit of claim 1, wherein the high side and low side transistors are enhancement mode GaN transistors. Original
The electrical circuit of claim 1, further comprising a tu rn on diode electrically connected in anti-parallel with the shunt resistor. Original
The electrical circuit of claim 1, further comprising additional shunt diodes and shunt resistors connected to respective sources of additional high side transistors. Original
The electrical circuit of claim 1, wherein the shunt diode is substituted with a shunt transistor, the shunt transistor being driven with a gate drive signal that is complementary to the signal applied to the gate of the low side transistor. Original
The electrical circuit of claim 1, wherein the gate driver, the bootstrap capacitor, the shunt diode and the shunt resistor ar e all fully integrated monolithically into a single integrated circuit. Original
The electrical circuit of claim 1, wherein the integrated circuit includes the high side and low side transistors and passive components of the circuit. Original
A method of avoiding gate drive overvoltage in an electrical circuit arranged in a half bridge configuration, wherein the half bridge of the electrical circuit comprises a high side transistor and a low side transistor, each having a source, a drain and a gate, the source of the high side transistor being electrically connected to the drain of the low side transistor at a first node, and the electrical circuit further comprises a gate driver electrically coupled to the gate of the high side transistor, and a bootstrap capacitor electrically coupled in parallel with the gate driver, wherein the method comprises charging the bootstrap capacitor, when both the high side and low side transistors are of f, th r ough a shunt network electrically connected in parallel to the low side transistor, the shunt network providing a low voltage drop charging path as compared to the reverse voltage drop of the low side transistor, wherein the shunt network comprises: a shunt diode having a cathode and an anode, the cathode of the shunt diode being connected to the capacitor at a second node, and the anode of the shunt diode being connected to ground, and a shunt resistor electrically connected between the first node and the second node to decouple the shunt diode from the first node, and to control and limit current through the shunt diode. Currently amended
The method of claim 10, wherein the high side and low side transistors are enhancement mode GaN transistors. Original
The method o f claim 10, wherein the shunt network further comprises a turn on diode electrically connected in anti-parallel with respect to the shunt resistor. Original
The method of claim 10, wherein the shunt network further comprises a turn on resistor in series with the turn on diode. Original
The method of claim 10, wherein the shunt diode is substituted with a shunt transistor, and the shunt transistor is driven with a gate drive signal that is complementary to the signal applied to the gate of the low side transistor. Original
Layer stacks claimed or described, ordered top of device to substrate.
half bridge circuit with bootstrap capacitor over-voltage management
Materials described outside the worked examples.
enhancement mode GaN transistor
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 7A shows a fifth embodiment of the circuit of the invention with a shunt transistor substituted for the shunt diode, and
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
GaN transistor reverse conduction voltage during dead-time | 2–2.5 V | enhancement mode GaN transistor |
bootstrap diode forward voltage drop | 0.3–0.7 V |
Related documents with shared materials, methods, properties, or citations.
bootstrap capacitor voltage (no dead-time, t2=0 ns) | 4.4 VDC | — |
bootstrap capacitor voltage/upper gate VGS(Q1) at maximum dead-time | 6 VDC | — |
peak gate voltage spike at maximum dead-time | 7 V | enhancement mode GaN transistor |
maximum peak gate voltage of GaN transistors | 6 V | enhancement mode GaN transistor |
HIGH SPEED PROGRAMMABLE THRESHOLD GALLIUM NITRIDE POWER LIMITER
bootstrap capacitor voltage (no dead-time, t2=0 ns) | 4.4 VDC | — |
bootstrap capacitor voltage/upper gate VGS(Q1) at maximum dead-time | 6 VDC | — |
peak gate voltage spike at maximum dead-time | 7 V | enhancement mode GaN transistor |
maximum peak gate voltage of GaN transistors | 6 V | enhancement mode GaN transistor |
HIGH SPEED PROGRAMMABLE THRESHOLD GALLIUM NITRIDE POWER LIMITER
bootstrap capacitor voltage (no dead-time, t2=0 ns) | 4.4 VDC | — |
bootstrap capacitor voltage/upper gate VGS(Q1) at maximum dead-time | 6 VDC | — |
peak gate voltage spike at maximum dead-time | 7 V | enhancement mode GaN transistor |
maximum peak gate voltage of GaN transistors | 6 V | enhancement mode GaN transistor |
HIGH SPEED PROGRAMMABLE THRESHOLD GALLIUM NITRIDE POWER LIMITER
bootstrap capacitor voltage (no dead-time, t2=0 ns) | 4.4 VDC | — |
bootstrap capacitor voltage/upper gate VGS(Q1) at maximum dead-time | 6 VDC | — |
peak gate voltage spike at maximum dead-time | 7 V | enhancement mode GaN transistor |
maximum peak gate voltage of GaN transistors | 6 V | enhancement mode GaN transistor |
HIGH SPEED PROGRAMMABLE THRESHOLD GALLIUM NITRIDE POWER LIMITER