Patent
US 10,847,624METHODS AND APPARATUS TO FORM GaN-BASED TRANSISTORS DURING BACK-END-OF-LINE PROCESSING
Marko Radosavljevic, Sansaptak Dasgupta, Han Wui Then
INTEL CORPORATION·05 April 2018·US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 10,847,624Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a graph representing the electron Hall mobility versus temperature of three different doping densities of InN. [0004]
FIG. 2. [0007] The figures are not to scale. Instead, to clarify multiple layers and regions, the thickness of the layers may be enlarged in the drawings. …
FIG. 3 is a flowchart of an example method to manufacture the example circuit of
FIG. 4 is a block diagram of an example processor system associated with a semiconductor fabrication machine to execute example machine readable instructions …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit comprising: a first transistor on a first semiconductor material comprising a fin; an amorphous dielectric material on the first semiconductor material and extending over the first transistor; a second semiconductor material on the amorphous dielectric material, the second semiconductor material comprising a polycrystalline or amorphous alloy of indium, gallium, and nitrogen; and a second transistor on the second semiconductor material, wherein the second transistor comprises a planar transistor. Currently amended
The integrated circuit of claim 1, further comprising metal wiring to electrically interconnect the first and second transistors. Previously presented
The integrated circuit of claim 1, wherein the first semiconductor material comprises silicon. Previously presented
The integrated circuit of claim 1, wherein the second semiconductor material has a thickness of not more than 100 nanometers. Previously presented
The integrated circuit of claim 1, wherein the second semiconductor material has a thickness of not more than 30 nanometers. Previously presented
The integrated circuit of claim 1, wherein the first transistor is a PMOS transistor and the second transistor is an NMOS transistor. Previously presented
Canceled
An apparatus comprising: a battery; and a circuit coupled to the battery, the circuit comprising: a first transistor on a first semiconductor material comprising a fin; an amorphous dielectric material on the first semiconductor material and extending over the first transistor; a second semiconductor material on the amorphous dielectric material, the second semiconductor material comprising a polycrystalline or amorphous alloy of indium, gallium, and nitrogen; and a second transistor on the second semiconductor material, wherein the second transistor comprises a planar transistor. Currently amended
The apparatus of claim 11, further comprising metal wiring to electrically interconnect the first and second transistors, wherein the metal wiring and the amorphous dielectric material comprises a series of layers of the amorphous dielectric material and layers of the metal wiring, and wherein the second transistor is within the layers of the metal wiring. Previously presented
The apparatus of claim 11, wherein the second semiconductor material has a thickness of not more than 30 nanometers. Previously presented
The apparatus of claim 11, wherein the first transistor is a PMOS transistor and the second transistor is an NMOS transistor.. Currently amended
A method to manufacture an integrated circuit, comprising: forming a first transistor on a first semiconductor material comprising a fin; adding an amorphous dielectric material on the first semiconductor material and extending over the first transistor forming a second semiconductor material on the amorphous dielectric material, the second semiconductor material comprising a polycrystalline or amorphous alloy of indium, gallium, and nitrogen; and forming a second transistor on the second semiconductor material, wherein the second transistor comprises a planar transistor. Currently amended
The method of claim 16, wherein the second semiconductor material has a thickness of not more than 30 nanometers and a height difference between a top surface of the first semiconductor material and a top surface of the second semiconductor material is not more than 0.5 microns. Previously presented
The method of claim 16, further comprising the first transistor to the second transistor. Previously
The method of claim 16. where the first transistor is an NMOS transistor. Previously presented forming metal wiring to electrically interconnect presented of the metal wiring is formed prior to fo t transistor is a PMOS transistor and the second
Layer stacks claimed or described, ordered top of device to substrate.
monolithically integrated PMOS/NMOS circuit with BEOL GaN-based transistor
Materials described outside the worked examples.
silicon
Si
amorphous dielectric material
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a graph representing the electron Hall mobility versus temperature of three different doping densities of InN. [0004]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Optical Band Gap | 3.4 eV | GaN |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,847,624Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a graph representing the electron Hall mobility versus temperature of three different doping densities of InN. [0004]
FIG. 2. [0007] The figures are not to scale. Instead, to clarify multiple layers and regions, the thickness of the layers may be enlarged in the drawings. …
FIG. 3 is a flowchart of an example method to manufacture the example circuit of
FIG. 4 is a block diagram of an example processor system associated with a semiconductor fabrication machine to execute example machine readable instructions …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit comprising: a first transistor on a first semiconductor material comprising a fin; an amorphous dielectric material on the first semiconductor material and extending over the first transistor; a second semiconductor material on the amorphous dielectric material, the second semiconductor material comprising a polycrystalline or amorphous alloy of indium, gallium, and nitrogen; and a second transistor on the second semiconductor material, wherein the second transistor comprises a planar transistor. Currently amended
The integrated circuit of claim 1, further comprising metal wiring to electrically interconnect the first and second transistors. Previously presented
The integrated circuit of claim 1, wherein the first semiconductor material comprises silicon. Previously presented
The integrated circuit of claim 1, wherein the second semiconductor material has a thickness of not more than 100 nanometers. Previously presented
The integrated circuit of claim 1, wherein the second semiconductor material has a thickness of not more than 30 nanometers. Previously presented
The integrated circuit of claim 1, wherein the first transistor is a PMOS transistor and the second transistor is an NMOS transistor. Previously presented
Canceled
An apparatus comprising: a battery; and a circuit coupled to the battery, the circuit comprising: a first transistor on a first semiconductor material comprising a fin; an amorphous dielectric material on the first semiconductor material and extending over the first transistor; a second semiconductor material on the amorphous dielectric material, the second semiconductor material comprising a polycrystalline or amorphous alloy of indium, gallium, and nitrogen; and a second transistor on the second semiconductor material, wherein the second transistor comprises a planar transistor. Currently amended
The apparatus of claim 11, further comprising metal wiring to electrically interconnect the first and second transistors, wherein the metal wiring and the amorphous dielectric material comprises a series of layers of the amorphous dielectric material and layers of the metal wiring, and wherein the second transistor is within the layers of the metal wiring. Previously presented
The apparatus of claim 11, wherein the second semiconductor material has a thickness of not more than 30 nanometers. Previously presented
The apparatus of claim 11, wherein the first transistor is a PMOS transistor and the second transistor is an NMOS transistor.. Currently amended
A method to manufacture an integrated circuit, comprising: forming a first transistor on a first semiconductor material comprising a fin; adding an amorphous dielectric material on the first semiconductor material and extending over the first transistor forming a second semiconductor material on the amorphous dielectric material, the second semiconductor material comprising a polycrystalline or amorphous alloy of indium, gallium, and nitrogen; and forming a second transistor on the second semiconductor material, wherein the second transistor comprises a planar transistor. Currently amended
The method of claim 16, wherein the second semiconductor material has a thickness of not more than 30 nanometers and a height difference between a top surface of the first semiconductor material and a top surface of the second semiconductor material is not more than 0.5 microns. Previously presented
The method of claim 16, further comprising the first transistor to the second transistor. Previously
The method of claim 16. where the first transistor is an NMOS transistor. Previously presented forming metal wiring to electrically interconnect presented of the metal wiring is formed prior to fo t transistor is a PMOS transistor and the second
Layer stacks claimed or described, ordered top of device to substrate.
monolithically integrated PMOS/NMOS circuit with BEOL GaN-based transistor
Materials described outside the worked examples.
silicon
Si
amorphous dielectric material
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a graph representing the electron Hall mobility versus temperature of three different doping densities of InN. [0004]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Optical Band Gap | 3.4 eV | GaN |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,847,624Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a graph representing the electron Hall mobility versus temperature of three different doping densities of InN. [0004]
FIG. 2. [0007] The figures are not to scale. Instead, to clarify multiple layers and regions, the thickness of the layers may be enlarged in the drawings. …
FIG. 3 is a flowchart of an example method to manufacture the example circuit of
FIG. 4 is a block diagram of an example processor system associated with a semiconductor fabrication machine to execute example machine readable instructions …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit comprising: a first transistor on a first semiconductor material comprising a fin; an amorphous dielectric material on the first semiconductor material and extending over the first transistor; a second semiconductor material on the amorphous dielectric material, the second semiconductor material comprising a polycrystalline or amorphous alloy of indium, gallium, and nitrogen; and a second transistor on the second semiconductor material, wherein the second transistor comprises a planar transistor. Currently amended
The integrated circuit of claim 1, further comprising metal wiring to electrically interconnect the first and second transistors. Previously presented
The integrated circuit of claim 1, wherein the first semiconductor material comprises silicon. Previously presented
The integrated circuit of claim 1, wherein the second semiconductor material has a thickness of not more than 100 nanometers. Previously presented
The integrated circuit of claim 1, wherein the second semiconductor material has a thickness of not more than 30 nanometers. Previously presented
The integrated circuit of claim 1, wherein the first transistor is a PMOS transistor and the second transistor is an NMOS transistor. Previously presented
Canceled
An apparatus comprising: a battery; and a circuit coupled to the battery, the circuit comprising: a first transistor on a first semiconductor material comprising a fin; an amorphous dielectric material on the first semiconductor material and extending over the first transistor; a second semiconductor material on the amorphous dielectric material, the second semiconductor material comprising a polycrystalline or amorphous alloy of indium, gallium, and nitrogen; and a second transistor on the second semiconductor material, wherein the second transistor comprises a planar transistor. Currently amended
The apparatus of claim 11, further comprising metal wiring to electrically interconnect the first and second transistors, wherein the metal wiring and the amorphous dielectric material comprises a series of layers of the amorphous dielectric material and layers of the metal wiring, and wherein the second transistor is within the layers of the metal wiring. Previously presented
The apparatus of claim 11, wherein the second semiconductor material has a thickness of not more than 30 nanometers. Previously presented
The apparatus of claim 11, wherein the first transistor is a PMOS transistor and the second transistor is an NMOS transistor.. Currently amended
A method to manufacture an integrated circuit, comprising: forming a first transistor on a first semiconductor material comprising a fin; adding an amorphous dielectric material on the first semiconductor material and extending over the first transistor forming a second semiconductor material on the amorphous dielectric material, the second semiconductor material comprising a polycrystalline or amorphous alloy of indium, gallium, and nitrogen; and forming a second transistor on the second semiconductor material, wherein the second transistor comprises a planar transistor. Currently amended
The method of claim 16, wherein the second semiconductor material has a thickness of not more than 30 nanometers and a height difference between a top surface of the first semiconductor material and a top surface of the second semiconductor material is not more than 0.5 microns. Previously presented
The method of claim 16, further comprising the first transistor to the second transistor. Previously
The method of claim 16. where the first transistor is an NMOS transistor. Previously presented forming metal wiring to electrically interconnect presented of the metal wiring is formed prior to fo t transistor is a PMOS transistor and the second
Layer stacks claimed or described, ordered top of device to substrate.
monolithically integrated PMOS/NMOS circuit with BEOL GaN-based transistor
Materials described outside the worked examples.
silicon
Si
amorphous dielectric material
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a graph representing the electron Hall mobility versus temperature of three different doping densities of InN. [0004]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Optical Band Gap | 3.4 eV | GaN |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,847,624Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a graph representing the electron Hall mobility versus temperature of three different doping densities of InN. [0004]
FIG. 2. [0007] The figures are not to scale. Instead, to clarify multiple layers and regions, the thickness of the layers may be enlarged in the drawings. …
FIG. 3 is a flowchart of an example method to manufacture the example circuit of
FIG. 4 is a block diagram of an example processor system associated with a semiconductor fabrication machine to execute example machine readable instructions …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit comprising: a first transistor on a first semiconductor material comprising a fin; an amorphous dielectric material on the first semiconductor material and extending over the first transistor; a second semiconductor material on the amorphous dielectric material, the second semiconductor material comprising a polycrystalline or amorphous alloy of indium, gallium, and nitrogen; and a second transistor on the second semiconductor material, wherein the second transistor comprises a planar transistor. Currently amended
The integrated circuit of claim 1, further comprising metal wiring to electrically interconnect the first and second transistors. Previously presented
The integrated circuit of claim 1, wherein the first semiconductor material comprises silicon. Previously presented
The integrated circuit of claim 1, wherein the second semiconductor material has a thickness of not more than 100 nanometers. Previously presented
The integrated circuit of claim 1, wherein the second semiconductor material has a thickness of not more than 30 nanometers. Previously presented
The integrated circuit of claim 1, wherein the first transistor is a PMOS transistor and the second transistor is an NMOS transistor. Previously presented
Canceled
An apparatus comprising: a battery; and a circuit coupled to the battery, the circuit comprising: a first transistor on a first semiconductor material comprising a fin; an amorphous dielectric material on the first semiconductor material and extending over the first transistor; a second semiconductor material on the amorphous dielectric material, the second semiconductor material comprising a polycrystalline or amorphous alloy of indium, gallium, and nitrogen; and a second transistor on the second semiconductor material, wherein the second transistor comprises a planar transistor. Currently amended
The apparatus of claim 11, further comprising metal wiring to electrically interconnect the first and second transistors, wherein the metal wiring and the amorphous dielectric material comprises a series of layers of the amorphous dielectric material and layers of the metal wiring, and wherein the second transistor is within the layers of the metal wiring. Previously presented
The apparatus of claim 11, wherein the second semiconductor material has a thickness of not more than 30 nanometers. Previously presented
The apparatus of claim 11, wherein the first transistor is a PMOS transistor and the second transistor is an NMOS transistor.. Currently amended
A method to manufacture an integrated circuit, comprising: forming a first transistor on a first semiconductor material comprising a fin; adding an amorphous dielectric material on the first semiconductor material and extending over the first transistor forming a second semiconductor material on the amorphous dielectric material, the second semiconductor material comprising a polycrystalline or amorphous alloy of indium, gallium, and nitrogen; and forming a second transistor on the second semiconductor material, wherein the second transistor comprises a planar transistor. Currently amended
The method of claim 16, wherein the second semiconductor material has a thickness of not more than 30 nanometers and a height difference between a top surface of the first semiconductor material and a top surface of the second semiconductor material is not more than 0.5 microns. Previously presented
The method of claim 16, further comprising the first transistor to the second transistor. Previously
The method of claim 16. where the first transistor is an NMOS transistor. Previously presented forming metal wiring to electrically interconnect presented of the metal wiring is formed prior to fo t transistor is a PMOS transistor and the second
Layer stacks claimed or described, ordered top of device to substrate.
monolithically integrated PMOS/NMOS circuit with BEOL GaN-based transistor
Materials described outside the worked examples.
silicon
Si
amorphous dielectric material
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a graph representing the electron Hall mobility versus temperature of three different doping densities of InN. [0004]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Optical Band Gap | 3.4 eV | GaN |
Thickness |
Related documents with shared materials, methods, properties, or citations.
polycrystalline or amorphous indium gallium nitride alloy
InGaN
gallium nitride
GaN
gallium arsenide
GaAs
FIG. 1 is a graph representing the electron Hall mobility versus temperature of three different doping densities of InN. [0004]
FIG. 2. [0007] The figures are not to scale. Instead, to clarify multiple layers and regions, the thickness of the layers may be enlarged in the drawings. …
| — |
Thickness | 0.1–0.5 µm | — |
Thickness | ≤ 1 µm | — |
Thickness | ≥ 1 nm | — |
Thickness | ≥ 30 nm | — |
Thickness | ≥ 0.5 µm | — |
polycrystalline or amorphous indium gallium nitride alloy
InGaN
gallium nitride
GaN
gallium arsenide
GaAs
FIG. 1 is a graph representing the electron Hall mobility versus temperature of three different doping densities of InN. [0004]
FIG. 2. [0007] The figures are not to scale. Instead, to clarify multiple layers and regions, the thickness of the layers may be enlarged in the drawings. …
| — |
Thickness | 0.1–0.5 µm | — |
Thickness | ≤ 1 µm | — |
Thickness | ≥ 1 nm | — |
Thickness | ≥ 30 nm | — |
Thickness | ≥ 0.5 µm | — |
polycrystalline or amorphous indium gallium nitride alloy
InGaN
gallium nitride
GaN
gallium arsenide
GaAs
FIG. 1 is a graph representing the electron Hall mobility versus temperature of three different doping densities of InN. [0004]
FIG. 2. [0007] The figures are not to scale. Instead, to clarify multiple layers and regions, the thickness of the layers may be enlarged in the drawings. …
| — |
Thickness | 0.1–0.5 µm | — |
Thickness | ≤ 1 µm | — |
Thickness | ≥ 1 nm | — |
Thickness | ≥ 30 nm | — |
Thickness | ≥ 0.5 µm | — |
polycrystalline or amorphous indium gallium nitride alloy
InGaN
gallium nitride
GaN
gallium arsenide
GaAs
FIG. 1 is a graph representing the electron Hall mobility versus temperature of three different doping densities of InN. [0004]
FIG. 2. [0007] The figures are not to scale. Instead, to clarify multiple layers and regions, the thickness of the layers may be enlarged in the drawings. …
| — |
Thickness | 0.1–0.5 µm | — |
Thickness | ≤ 1 µm | — |
Thickness | ≥ 1 nm | — |
Thickness | ≥ 30 nm | — |
Thickness | ≥ 0.5 µm | — |