Patent
US 12,648,207 B2FIELD PLATE STRUCTURES FOR GaN HIGH VOLTAGE TRANSISTORS
Pil Sung Park, Daniel M. Kinzer
Navitas Semiconductor Limited, Dublin (IE)·Jun. 2, 2026·US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 12,648,207 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1A illustrates a cross-sectional view of a GaN transistor with field plate structures having a pedestal according to an embodiment of the disclosure;
FIG. 2 illustrates a cross-sectional view of a GaN tran- sistor with field plate structures according to an embodiment of the disclosure;
FIG. 3A illustrates a cross-sectional view of a GaN transistor with field plate structures using dielectric layers according to an embodiment of the disclosure;
FIG. 4 illustrates a plan view of a GaN transistor accord- ing to an embodiment of the disclosure; 5
FIG. 5A illustrates a plan view of a GaN transistor with a field plate structure according to an embodiment of the disclosure;
FIG. 6A illustrates a cross-sectional view of a GaN transistor with multiple pedestals and with an additional layer for adjusting the thickness of the …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A transistor comprising: a gallium nitride (GaN) substrate; a source region formed on the GaN substrate; a drain region formed on the GaN substrate and separate from the source region; a gate region formed between the source region and the drain region; a pedestal formed on the GaN substrate and positioned between the gate region and the drain region, wherein the pedestal is not positioned between the gate region and the source region; and a field plate electrically coupled to the source region, the field plate extending from a proximal region positioned between the source region and the pedestal, towards the drain region, wherein a starting position of the field plate is disposed between the gate region and the pedestal, and the starting position of the field plate is separated from the GaN substrate by a thickness of a dielectric layer that extends across at least a portion of the GaN substrate and across at least a portion of the pedestal, wherein the dielectric layer is positioned between the pedestal and the field plate, wherein at least a portion of the field plate overlaps at least a portion of the pedestal wherein a portion of the field plate is formed at an angle with respect to the GaN substrate; and wherein a value of the angle is determined by a ratio of a distance between a distal region of the field plate and the GaN substrate to a distance between the proximal region of the field plate and the GaN substrate.
The transistor of claim 1, wherein the proximal region of the field plate is separated from the GaN substrate by the thickness of the dielectric layer and wherein a distal region of the field plate is separated from the GaN substrate by the thickness of the dielectric layer and the thickness of the pedestal.
The transistor of claim 1, wherein the pedestal is a first pedestal of a plurality of pedestals.
The transistor of claim 1, wherein the pedestal is formed from a P-type GaN layer.
The transistor of claim 1, wherein a value of the angle is between 5 to 175 degrees.
A transistor comprising: a gallium nitride (GaN) substrate; a source region formed on the GaN substrate; a drain region formed on the GaN substrate and separate from the source region; 5 a gate region formed between the source region and the drain region; a pedestal formed on the GaN substrate and positioned between the gate region and the drain region, wherein the pedestal is not positioned between the gate region and the source region and the pedestal is formed from a material that is not doped; a field plate electrically coupled to the source region, the field plate extending towards the drain region, across a portion of the GaN substrate and across at least a portion of the pedestal; and a dielectric layer extending across at least a portion of the GaN substrate and extending across at least a portion of the pedestal, the dielectric layer being positioned between the pedestal and the field plate, wherein a starting position of the field plate is disposed between the gate region and the pedestal, and the starting position of the field plate is separated from the GaN substrate by a thickness of the dielectric layer; wherein a portion of the field plate is formed in shape of an angle; and wherein a value of the angle is determined by a ratio of a distance between a distal region of the field plate and the GaN substrate to a distance between a proximal region of the field plate and the GaN substrate.
The transistor of claim 8, wherein a proximal region of the field plate is separated from the GaN substrate by the thickness of the dielectric layer and wherein a distal region of the field plate is separated from the GaN substrate by the thickness of the dielectric layer and the thickness of the pedestal.
The transistor of claim 8, further comprising two or more pedestals.
A method of forming a transistor, the method com-prising: providing a gallium nitride (GaN) substrate; forming a source region formed on the GaN substrate; forming a drain region formed on the GaN substrate and separate from the source region; forming a gate region formed between the source region and the drain region; forming a pedestal formed on the GaN substrate and positioned between the gate region and the drain region, wherein the pedestal is not positioned between the gate region and the source region; and forming a field plate electrically coupled to the source region, the field plate extending from a proximal region positioned between the source region and the pedestal, towards the drain region, wherein a starting position of the field plate is disposed between the gate region and the pedestal and the starting position of the field plate is separated from the GaN substrate by a thickness of a dielectric layer that extends across at least a portion of the GaN substrate and across at least a portion of the pedestal, wherein the dielectric layer is positioned between the pedestal and the field plate, wherein at least a portion of the field plate overlaps at least a portion of the pedestal; wherein a portion of the field plate is formed at an angle with respect to the GaN substrate; and wherein a value of the angle is determined by a ratio of a distance between a distal region of the field plate and the GaN substrate to a distance between the proximal region of the field plate and the GaN substrate. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN high voltage lateral transistor with field plate and pedestal (P-type GaN or dielectric pedestal)
GaN high voltage lateral transistor with field plate and undoped pedestal
Materials described outside the worked examples.
gallium nitride
GaN
dielectric layer
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1A illustrates a cross-sectional view of a GaN transistor with field plate structures having a pedestal according to an embodiment of the disclosure;
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.6–0.8 um | — |
Thickness |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 5
Related documents with shared materials, methods, properties, or citations.
VERTICAL GALLIUM NITRIDE CONTAINING FIELD EFFECT TRANSISTOR WITH SILICON NITRIDE PASSIVATION AND GATE DIELECTRIC REGIONS
MONOLITHIC INTEGRATION OF HIGH AND LOW-SIDE GAN FETS WITH SCREENING BACK GATING EFFECT
Patent
Atlas literature
Patent
US 12,648,207 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1A illustrates a cross-sectional view of a GaN transistor with field plate structures having a pedestal according to an embodiment of the disclosure;
FIG. 2 illustrates a cross-sectional view of a GaN tran- sistor with field plate structures according to an embodiment of the disclosure;
FIG. 3A illustrates a cross-sectional view of a GaN transistor with field plate structures using dielectric layers according to an embodiment of the disclosure;
FIG. 4 illustrates a plan view of a GaN transistor accord- ing to an embodiment of the disclosure; 5
FIG. 5A illustrates a plan view of a GaN transistor with a field plate structure according to an embodiment of the disclosure;
FIG. 6A illustrates a cross-sectional view of a GaN transistor with multiple pedestals and with an additional layer for adjusting the thickness of the …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A transistor comprising: a gallium nitride (GaN) substrate; a source region formed on the GaN substrate; a drain region formed on the GaN substrate and separate from the source region; a gate region formed between the source region and the drain region; a pedestal formed on the GaN substrate and positioned between the gate region and the drain region, wherein the pedestal is not positioned between the gate region and the source region; and a field plate electrically coupled to the source region, the field plate extending from a proximal region positioned between the source region and the pedestal, towards the drain region, wherein a starting position of the field plate is disposed between the gate region and the pedestal, and the starting position of the field plate is separated from the GaN substrate by a thickness of a dielectric layer that extends across at least a portion of the GaN substrate and across at least a portion of the pedestal, wherein the dielectric layer is positioned between the pedestal and the field plate, wherein at least a portion of the field plate overlaps at least a portion of the pedestal wherein a portion of the field plate is formed at an angle with respect to the GaN substrate; and wherein a value of the angle is determined by a ratio of a distance between a distal region of the field plate and the GaN substrate to a distance between the proximal region of the field plate and the GaN substrate.
The transistor of claim 1, wherein the proximal region of the field plate is separated from the GaN substrate by the thickness of the dielectric layer and wherein a distal region of the field plate is separated from the GaN substrate by the thickness of the dielectric layer and the thickness of the pedestal.
The transistor of claim 1, wherein the pedestal is a first pedestal of a plurality of pedestals.
The transistor of claim 1, wherein the pedestal is formed from a P-type GaN layer.
The transistor of claim 1, wherein a value of the angle is between 5 to 175 degrees.
A transistor comprising: a gallium nitride (GaN) substrate; a source region formed on the GaN substrate; a drain region formed on the GaN substrate and separate from the source region; 5 a gate region formed between the source region and the drain region; a pedestal formed on the GaN substrate and positioned between the gate region and the drain region, wherein the pedestal is not positioned between the gate region and the source region and the pedestal is formed from a material that is not doped; a field plate electrically coupled to the source region, the field plate extending towards the drain region, across a portion of the GaN substrate and across at least a portion of the pedestal; and a dielectric layer extending across at least a portion of the GaN substrate and extending across at least a portion of the pedestal, the dielectric layer being positioned between the pedestal and the field plate, wherein a starting position of the field plate is disposed between the gate region and the pedestal, and the starting position of the field plate is separated from the GaN substrate by a thickness of the dielectric layer; wherein a portion of the field plate is formed in shape of an angle; and wherein a value of the angle is determined by a ratio of a distance between a distal region of the field plate and the GaN substrate to a distance between a proximal region of the field plate and the GaN substrate.
The transistor of claim 8, wherein a proximal region of the field plate is separated from the GaN substrate by the thickness of the dielectric layer and wherein a distal region of the field plate is separated from the GaN substrate by the thickness of the dielectric layer and the thickness of the pedestal.
The transistor of claim 8, further comprising two or more pedestals.
A method of forming a transistor, the method com-prising: providing a gallium nitride (GaN) substrate; forming a source region formed on the GaN substrate; forming a drain region formed on the GaN substrate and separate from the source region; forming a gate region formed between the source region and the drain region; forming a pedestal formed on the GaN substrate and positioned between the gate region and the drain region, wherein the pedestal is not positioned between the gate region and the source region; and forming a field plate electrically coupled to the source region, the field plate extending from a proximal region positioned between the source region and the pedestal, towards the drain region, wherein a starting position of the field plate is disposed between the gate region and the pedestal and the starting position of the field plate is separated from the GaN substrate by a thickness of a dielectric layer that extends across at least a portion of the GaN substrate and across at least a portion of the pedestal, wherein the dielectric layer is positioned between the pedestal and the field plate, wherein at least a portion of the field plate overlaps at least a portion of the pedestal; wherein a portion of the field plate is formed at an angle with respect to the GaN substrate; and wherein a value of the angle is determined by a ratio of a distance between a distal region of the field plate and the GaN substrate to a distance between the proximal region of the field plate and the GaN substrate. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN high voltage lateral transistor with field plate and pedestal (P-type GaN or dielectric pedestal)
GaN high voltage lateral transistor with field plate and undoped pedestal
Materials described outside the worked examples.
gallium nitride
GaN
dielectric layer
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1A illustrates a cross-sectional view of a GaN transistor with field plate structures having a pedestal according to an embodiment of the disclosure;
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.6–0.8 um | — |
Thickness |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 5
Related documents with shared materials, methods, properties, or citations.
VERTICAL GALLIUM NITRIDE CONTAINING FIELD EFFECT TRANSISTOR WITH SILICON NITRIDE PASSIVATION AND GATE DIELECTRIC REGIONS
MONOLITHIC INTEGRATION OF HIGH AND LOW-SIDE GAN FETS WITH SCREENING BACK GATING EFFECT
Patent
Atlas literature
Patent
US 12,648,207 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1A illustrates a cross-sectional view of a GaN transistor with field plate structures having a pedestal according to an embodiment of the disclosure;
FIG. 2 illustrates a cross-sectional view of a GaN tran- sistor with field plate structures according to an embodiment of the disclosure;
FIG. 3A illustrates a cross-sectional view of a GaN transistor with field plate structures using dielectric layers according to an embodiment of the disclosure;
FIG. 4 illustrates a plan view of a GaN transistor accord- ing to an embodiment of the disclosure; 5
FIG. 5A illustrates a plan view of a GaN transistor with a field plate structure according to an embodiment of the disclosure;
FIG. 6A illustrates a cross-sectional view of a GaN transistor with multiple pedestals and with an additional layer for adjusting the thickness of the …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A transistor comprising: a gallium nitride (GaN) substrate; a source region formed on the GaN substrate; a drain region formed on the GaN substrate and separate from the source region; a gate region formed between the source region and the drain region; a pedestal formed on the GaN substrate and positioned between the gate region and the drain region, wherein the pedestal is not positioned between the gate region and the source region; and a field plate electrically coupled to the source region, the field plate extending from a proximal region positioned between the source region and the pedestal, towards the drain region, wherein a starting position of the field plate is disposed between the gate region and the pedestal, and the starting position of the field plate is separated from the GaN substrate by a thickness of a dielectric layer that extends across at least a portion of the GaN substrate and across at least a portion of the pedestal, wherein the dielectric layer is positioned between the pedestal and the field plate, wherein at least a portion of the field plate overlaps at least a portion of the pedestal wherein a portion of the field plate is formed at an angle with respect to the GaN substrate; and wherein a value of the angle is determined by a ratio of a distance between a distal region of the field plate and the GaN substrate to a distance between the proximal region of the field plate and the GaN substrate.
The transistor of claim 1, wherein the proximal region of the field plate is separated from the GaN substrate by the thickness of the dielectric layer and wherein a distal region of the field plate is separated from the GaN substrate by the thickness of the dielectric layer and the thickness of the pedestal.
The transistor of claim 1, wherein the pedestal is a first pedestal of a plurality of pedestals.
The transistor of claim 1, wherein the pedestal is formed from a P-type GaN layer.
The transistor of claim 1, wherein a value of the angle is between 5 to 175 degrees.
A transistor comprising: a gallium nitride (GaN) substrate; a source region formed on the GaN substrate; a drain region formed on the GaN substrate and separate from the source region; 5 a gate region formed between the source region and the drain region; a pedestal formed on the GaN substrate and positioned between the gate region and the drain region, wherein the pedestal is not positioned between the gate region and the source region and the pedestal is formed from a material that is not doped; a field plate electrically coupled to the source region, the field plate extending towards the drain region, across a portion of the GaN substrate and across at least a portion of the pedestal; and a dielectric layer extending across at least a portion of the GaN substrate and extending across at least a portion of the pedestal, the dielectric layer being positioned between the pedestal and the field plate, wherein a starting position of the field plate is disposed between the gate region and the pedestal, and the starting position of the field plate is separated from the GaN substrate by a thickness of the dielectric layer; wherein a portion of the field plate is formed in shape of an angle; and wherein a value of the angle is determined by a ratio of a distance between a distal region of the field plate and the GaN substrate to a distance between a proximal region of the field plate and the GaN substrate.
The transistor of claim 8, wherein a proximal region of the field plate is separated from the GaN substrate by the thickness of the dielectric layer and wherein a distal region of the field plate is separated from the GaN substrate by the thickness of the dielectric layer and the thickness of the pedestal.
The transistor of claim 8, further comprising two or more pedestals.
A method of forming a transistor, the method com-prising: providing a gallium nitride (GaN) substrate; forming a source region formed on the GaN substrate; forming a drain region formed on the GaN substrate and separate from the source region; forming a gate region formed between the source region and the drain region; forming a pedestal formed on the GaN substrate and positioned between the gate region and the drain region, wherein the pedestal is not positioned between the gate region and the source region; and forming a field plate electrically coupled to the source region, the field plate extending from a proximal region positioned between the source region and the pedestal, towards the drain region, wherein a starting position of the field plate is disposed between the gate region and the pedestal and the starting position of the field plate is separated from the GaN substrate by a thickness of a dielectric layer that extends across at least a portion of the GaN substrate and across at least a portion of the pedestal, wherein the dielectric layer is positioned between the pedestal and the field plate, wherein at least a portion of the field plate overlaps at least a portion of the pedestal; wherein a portion of the field plate is formed at an angle with respect to the GaN substrate; and wherein a value of the angle is determined by a ratio of a distance between a distal region of the field plate and the GaN substrate to a distance between the proximal region of the field plate and the GaN substrate. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN high voltage lateral transistor with field plate and pedestal (P-type GaN or dielectric pedestal)
GaN high voltage lateral transistor with field plate and undoped pedestal
Materials described outside the worked examples.
gallium nitride
GaN
dielectric layer
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1A illustrates a cross-sectional view of a GaN transistor with field plate structures having a pedestal according to an embodiment of the disclosure;
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.6–0.8 um | — |
Thickness |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 5
Related documents with shared materials, methods, properties, or citations.
VERTICAL GALLIUM NITRIDE CONTAINING FIELD EFFECT TRANSISTOR WITH SILICON NITRIDE PASSIVATION AND GATE DIELECTRIC REGIONS
MONOLITHIC INTEGRATION OF HIGH AND LOW-SIDE GAN FETS WITH SCREENING BACK GATING EFFECT
Patent
Atlas literature
Patent
US 12,648,207 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1A illustrates a cross-sectional view of a GaN transistor with field plate structures having a pedestal according to an embodiment of the disclosure;
FIG. 2 illustrates a cross-sectional view of a GaN tran- sistor with field plate structures according to an embodiment of the disclosure;
FIG. 3A illustrates a cross-sectional view of a GaN transistor with field plate structures using dielectric layers according to an embodiment of the disclosure;
FIG. 4 illustrates a plan view of a GaN transistor accord- ing to an embodiment of the disclosure; 5
FIG. 5A illustrates a plan view of a GaN transistor with a field plate structure according to an embodiment of the disclosure;
FIG. 6A illustrates a cross-sectional view of a GaN transistor with multiple pedestals and with an additional layer for adjusting the thickness of the …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A transistor comprising: a gallium nitride (GaN) substrate; a source region formed on the GaN substrate; a drain region formed on the GaN substrate and separate from the source region; a gate region formed between the source region and the drain region; a pedestal formed on the GaN substrate and positioned between the gate region and the drain region, wherein the pedestal is not positioned between the gate region and the source region; and a field plate electrically coupled to the source region, the field plate extending from a proximal region positioned between the source region and the pedestal, towards the drain region, wherein a starting position of the field plate is disposed between the gate region and the pedestal, and the starting position of the field plate is separated from the GaN substrate by a thickness of a dielectric layer that extends across at least a portion of the GaN substrate and across at least a portion of the pedestal, wherein the dielectric layer is positioned between the pedestal and the field plate, wherein at least a portion of the field plate overlaps at least a portion of the pedestal wherein a portion of the field plate is formed at an angle with respect to the GaN substrate; and wherein a value of the angle is determined by a ratio of a distance between a distal region of the field plate and the GaN substrate to a distance between the proximal region of the field plate and the GaN substrate.
The transistor of claim 1, wherein the proximal region of the field plate is separated from the GaN substrate by the thickness of the dielectric layer and wherein a distal region of the field plate is separated from the GaN substrate by the thickness of the dielectric layer and the thickness of the pedestal.
The transistor of claim 1, wherein the pedestal is a first pedestal of a plurality of pedestals.
The transistor of claim 1, wherein the pedestal is formed from a P-type GaN layer.
The transistor of claim 1, wherein a value of the angle is between 5 to 175 degrees.
A transistor comprising: a gallium nitride (GaN) substrate; a source region formed on the GaN substrate; a drain region formed on the GaN substrate and separate from the source region; 5 a gate region formed between the source region and the drain region; a pedestal formed on the GaN substrate and positioned between the gate region and the drain region, wherein the pedestal is not positioned between the gate region and the source region and the pedestal is formed from a material that is not doped; a field plate electrically coupled to the source region, the field plate extending towards the drain region, across a portion of the GaN substrate and across at least a portion of the pedestal; and a dielectric layer extending across at least a portion of the GaN substrate and extending across at least a portion of the pedestal, the dielectric layer being positioned between the pedestal and the field plate, wherein a starting position of the field plate is disposed between the gate region and the pedestal, and the starting position of the field plate is separated from the GaN substrate by a thickness of the dielectric layer; wherein a portion of the field plate is formed in shape of an angle; and wherein a value of the angle is determined by a ratio of a distance between a distal region of the field plate and the GaN substrate to a distance between a proximal region of the field plate and the GaN substrate.
The transistor of claim 8, wherein a proximal region of the field plate is separated from the GaN substrate by the thickness of the dielectric layer and wherein a distal region of the field plate is separated from the GaN substrate by the thickness of the dielectric layer and the thickness of the pedestal.
The transistor of claim 8, further comprising two or more pedestals.
A method of forming a transistor, the method com-prising: providing a gallium nitride (GaN) substrate; forming a source region formed on the GaN substrate; forming a drain region formed on the GaN substrate and separate from the source region; forming a gate region formed between the source region and the drain region; forming a pedestal formed on the GaN substrate and positioned between the gate region and the drain region, wherein the pedestal is not positioned between the gate region and the source region; and forming a field plate electrically coupled to the source region, the field plate extending from a proximal region positioned between the source region and the pedestal, towards the drain region, wherein a starting position of the field plate is disposed between the gate region and the pedestal and the starting position of the field plate is separated from the GaN substrate by a thickness of a dielectric layer that extends across at least a portion of the GaN substrate and across at least a portion of the pedestal, wherein the dielectric layer is positioned between the pedestal and the field plate, wherein at least a portion of the field plate overlaps at least a portion of the pedestal; wherein a portion of the field plate is formed at an angle with respect to the GaN substrate; and wherein a value of the angle is determined by a ratio of a distance between a distal region of the field plate and the GaN substrate to a distance between the proximal region of the field plate and the GaN substrate. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN high voltage lateral transistor with field plate and pedestal (P-type GaN or dielectric pedestal)
GaN high voltage lateral transistor with field plate and undoped pedestal
Materials described outside the worked examples.
gallium nitride
GaN
dielectric layer
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1A illustrates a cross-sectional view of a GaN transistor with field plate structures having a pedestal according to an embodiment of the disclosure;
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.6–0.8 um | — |
Thickness |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 5
Related documents with shared materials, methods, properties, or citations.
VERTICAL GALLIUM NITRIDE CONTAINING FIELD EFFECT TRANSISTOR WITH SILICON NITRIDE PASSIVATION AND GATE DIELECTRIC REGIONS
MONOLITHIC INTEGRATION OF HIGH AND LOW-SIDE GAN FETS WITH SCREENING BACK GATING EFFECT
GaN transistor 100A with field plate structures (described embodiment)
pedestal material (undoped)
P-type GaN
GaN:p
silicon nitride
Si₃N₄
AlGaN
Al0.20Ga0.80N
FIG. 1A illustrates a cross-sectional view of a GaN transistor with field plate structures having a pedestal according to an embodiment of the disclosure;
FIG. 3A illustrates a cross-sectional view of a GaN transistor with field plate structures using dielectric layers according to an embodiment of the disclosure;
FIG. 4 illustrates a plan view of a GaN transistor accord- ing to an embodiment of the disclosure; 5
FIG. 5A illustrates a plan view of a GaN transistor with a field plate structure according to an embodiment of the disclosure;
FIG. 6A illustrates a cross-sectional view of a GaN transistor with multiple pedestals and with an additional layer for adjusting the thickness of the …
FIG. 6A illustrates a cross-sectional view of a GaN transistor with multiple pedestals and with an additional layer for adjusting the thickness of the …
| 0.5–1 um |
| — |
Thickness | 0.1–5 um | — |
Thickness | 50–100 nm | — |
Thickness | 30–200 nm | — |
Thickness | 10–500 nm | — |
Thickness | 60–80 nm | — |
Voltage | 5–100 V | — |
Voltage | 150–800 V | — |
Thickness | 1–2 um | — |
Thickness | 0.1–1 um | — |
Cited non-patent literature · 1
GaN transistor 100A with field plate structures (described embodiment)
pedestal material (undoped)
P-type GaN
GaN:p
silicon nitride
Si₃N₄
AlGaN
Al0.20Ga0.80N
FIG. 1A illustrates a cross-sectional view of a GaN transistor with field plate structures having a pedestal according to an embodiment of the disclosure;
FIG. 3A illustrates a cross-sectional view of a GaN transistor with field plate structures using dielectric layers according to an embodiment of the disclosure;
FIG. 4 illustrates a plan view of a GaN transistor accord- ing to an embodiment of the disclosure; 5
FIG. 5A illustrates a plan view of a GaN transistor with a field plate structure according to an embodiment of the disclosure;
FIG. 6A illustrates a cross-sectional view of a GaN transistor with multiple pedestals and with an additional layer for adjusting the thickness of the …
FIG. 6A illustrates a cross-sectional view of a GaN transistor with multiple pedestals and with an additional layer for adjusting the thickness of the …
| 0.5–1 um |
| — |
Thickness | 0.1–5 um | — |
Thickness | 50–100 nm | — |
Thickness | 30–200 nm | — |
Thickness | 10–500 nm | — |
Thickness | 60–80 nm | — |
Voltage | 5–100 V | — |
Voltage | 150–800 V | — |
Thickness | 1–2 um | — |
Thickness | 0.1–1 um | — |
Cited non-patent literature · 1
GaN transistor 100A with field plate structures (described embodiment)
pedestal material (undoped)
P-type GaN
GaN:p
silicon nitride
Si₃N₄
AlGaN
Al0.20Ga0.80N
FIG. 1A illustrates a cross-sectional view of a GaN transistor with field plate structures having a pedestal according to an embodiment of the disclosure;
FIG. 3A illustrates a cross-sectional view of a GaN transistor with field plate structures using dielectric layers according to an embodiment of the disclosure;
FIG. 4 illustrates a plan view of a GaN transistor accord- ing to an embodiment of the disclosure; 5
FIG. 5A illustrates a plan view of a GaN transistor with a field plate structure according to an embodiment of the disclosure;
FIG. 6A illustrates a cross-sectional view of a GaN transistor with multiple pedestals and with an additional layer for adjusting the thickness of the …
FIG. 6A illustrates a cross-sectional view of a GaN transistor with multiple pedestals and with an additional layer for adjusting the thickness of the …
| 0.5–1 um |
| — |
Thickness | 0.1–5 um | — |
Thickness | 50–100 nm | — |
Thickness | 30–200 nm | — |
Thickness | 10–500 nm | — |
Thickness | 60–80 nm | — |
Voltage | 5–100 V | — |
Voltage | 150–800 V | — |
Thickness | 1–2 um | — |
Thickness | 0.1–1 um | — |
Cited non-patent literature · 1
GaN transistor 100A with field plate structures (described embodiment)
pedestal material (undoped)
P-type GaN
GaN:p
silicon nitride
Si₃N₄
AlGaN
Al0.20Ga0.80N
FIG. 1A illustrates a cross-sectional view of a GaN transistor with field plate structures having a pedestal according to an embodiment of the disclosure;
FIG. 3A illustrates a cross-sectional view of a GaN transistor with field plate structures using dielectric layers according to an embodiment of the disclosure;
FIG. 4 illustrates a plan view of a GaN transistor accord- ing to an embodiment of the disclosure; 5
FIG. 5A illustrates a plan view of a GaN transistor with a field plate structure according to an embodiment of the disclosure;
FIG. 6A illustrates a cross-sectional view of a GaN transistor with multiple pedestals and with an additional layer for adjusting the thickness of the …
FIG. 6A illustrates a cross-sectional view of a GaN transistor with multiple pedestals and with an additional layer for adjusting the thickness of the …
| 0.5–1 um |
| — |
Thickness | 0.1–5 um | — |
Thickness | 50–100 nm | — |
Thickness | 30–200 nm | — |
Thickness | 10–500 nm | — |
Thickness | 60–80 nm | — |
Voltage | 5–100 V | — |
Voltage | 150–800 V | — |
Thickness | 1–2 um | — |
Thickness | 0.1–1 um | — |
Cited non-patent literature · 1