Patent
US 10,469,041GALLIUM NITRIDE (GAN) POWER AMPLIFIERS (PA) WITH ANGLED ELECTRODES AND 100 CMOS AND METHOD FOR PRODUCING THE SAME
Anthony Kendall STAMPER
US
Copyright © 2026 Matter42. All rights reserved.
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Atlas literature
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US 10,469,041Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1, e.g., a FET, a NPN transistor, a HBT, a MOS capacitor, a deep trench capacitor, a flash memory cell, a magnetic memory cell, a poly resistor, a diffusion …
FIG. 2. The composition of the protective layer 201 is chosen to protect the device 101 during the subsequent GaN processing. The Protective layer 201 may be …
FIG. 3, a photoresist 301 is formed over the Si substrate 103 and the protective layer 201. Then, the photoresist 301 is exposed and developed in the center …
FIG. 4. Specifically, each side of the V-shaped groove 401 is formed at approximately 54.7 degrees, thus having a 111 angled Si surface. [0023] Next, the …
FIG. 5. Alternatively, as described above, the protective layer 201 could be under the opening 303 and may be removed by etching prior to forming the V-shaped …
FIG. 6, a buffer layer 601 is formed, e.g., by a physical vapor deposition (PVD), a chemical vapor deposition (CVD), an atomic layer deposition (ALD), a plasma …
FIG. 7, a conformal or semi-conformal spin-on or dry resist layer 701 is formed, e.g., to a thickness of 0.3 p m to 10 p m by a standard spin-on process and a …
FIG. 8. Next, the passivation layer 607 and the A l GaN layer 605 are etched, e.g., by a wet etching or a plasma etching with, e.g., BCL 3/CL 2 gases, through …
FIG. 9. In one instance, the A l GaN layer 605 may be partially etched, whereupon the etching stops. In another instance, portions of the GaN layer 603 may be …
FIG. 10. A resist layer 1101 is then conformally or semi-conformally formed, e.g., to a thickness of 0.3 p m to 10 p m by a standard spin-on process and a …
FIG. 12. In one instance, the openings 1201 may be formed either on the one side or on the both sides of the V-shaped groove 401 depending on the resultant …
FIG. 13, the passivation layer 607 is etched, e.g., by a wet or a dry etching, through the openings 1201 down to the A l GaN layer 605, forming openings 1201'. …
FIG. 14. [0027] Referring to
FIG. 15, an electrode layer 1501 is formed, e.g., of titanium nitride (TiN), molybdenum (Mo), or any other suitable conductor by CVD, ALD, PVD, or any other …
FIG. 16. In
FIG. 17, a conformal resist layer (not shown for illustrative convenience) is formed over the passivation layer 607 and the electrode structures 1501'. Then, …
FIG. 18, a dielectric layer 1801 is formed over the Si substrate 103 and then planarized as known in the art, e.g., by CMP, etch-back, etc.. Next, vias (not …
FIG. 19 is a cross-sectional view of a different embodiment of a CMOS device and a GaN PA structure formed on a 100 Si substrate having a 111 surface …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method comprising: providing a silicon (Si) substrate with a device over a portion of the Si substrate and a protective layer over the device and a portion of the Si substrate; forming a V-shaped groove in a portion of the Si substrate; forming a buffer layer, a gallium nitride (GaN) layer, an aluminum gallium nitride (AlGaN) layer and a passivation layer sequentially over the Si substrate; forming first trenches through the passivation layer and the AlGaN layer on one or both sides of the V-shaped groove; forming second trenches through the passivation layer on the one or both sides; forming electrode structures over portions of the passivation layer and filling the first trenches and the second trenches; removing portions of the passivation layer, the AlGaN layer and the GaN layer outside of the V-shaped groove down to the buffer layer; forming a dielectric layer over the Si substrate; and forming a via through the dielectric layer down to at least one of the electrode structure and the device.
The method according to claim 1, comprising forming the V-shaped groove by: forming a photo resist or a dielectric layer over the Si substrate; forming a trench through the photo resist or the dielectric layer down to the Si substrate; and performing a wet etch such that each side of the V-shaped groove is at 54.7 degrees.
The method according to claim 1, comprising forming the first trenches by: forming a conformal resist layer over the passivation layer; patterning the conformal resist layer down to the passivation layer; and etching the passivation layer and the AlGaN layer through the patterned conformal resist layer down to the GaN layer.
The method according to claim 1, comprising removing portions of the passivation layer, the AlGaN layer and the GaN layer down to the buffer layer by: forming a conformal resist layer over the passivation layer and the electrode structures; patterning the conformal resist layer over the Si substrate outside of the V-shaped groove down to the passivation layer; and etching the passivation layer, the AlGaN layer and the GaN layer through the patterned conformal resist layer down to the buffer layer.
A device comprising: a complementary metal oxide semiconductor (CMOS) transistor on a 100 silicon (Si); and a gallium nitride (GaN) high electron mobility transistor (HEMT) on a 111 Si, wherein the 100 Si and the 111 Si are contiguous.
The device according to claim 10, wherein the GaN HEMT comprises: a buffer layer over a portion of each surface of a V-shaped groove; a gallium nitride (GaN) layer over the buffer layer; an aluminum gallium nitride (AlGaN) layer over the GaN layer; a passivation layer over the AlGaN layer; a first electrode over a portion of the passivation layer and through the passivation layer and the AlGaN layer down to the GaN layer; a second electrode over a portion of the passivation layer and through the passivation layer down to the AlGaN layer; a dielectric layer over the 111 Si; and a metal-filled via through the dielectric layer down to at least one of the first electrode and the second electrode.
The device according to claim 10, further comprising: a protective layer over the CMOS transistor and on portions of the 100 Si; a dielectric layer over the 100 Si and the protective layer; and a metal-filled via through the dielectric layer and the protective layer to the CMOS transistor.
A device comprising: a first silicon (Si) layer; a silicon germanium (SiGe) layer over the first Si layer; a second Si layer over the SiGe layer with a trench down to the SiGe layer having angled sidewalls; a buffer layer over a portion of each angled sidewall of the trench; a gallium nitride (GaN) layer over the buffer layer; an aluminum gallium nitride (AlGaN) layer over a portion of the GaN layer; a passivation layer over the AlGaN layer; a first electrode structure through the passivation layer and the AlGaN layer down to the GaN layer; a second electrode structure through the passivation layer down to the AlGaN layer; a third electrode structure through the passivation layer and the AlGaN layer down to the GaN layer and over a portion of one of the angled sidewall and the SiGe layer within the trench; a dielectric layer over the first Si layer, filling the trench; a device over a portion of the second Si layer proximate to the trench; and a metal-filled via through the dielectric layer down to each of the first electrode structure, the second electrode structure and the third electrode structure.
The device according to claim 18, further comprising: a second device formed over the SiGe layer within the trench; and a second metal-filled via through the dielectric layer down to the second device.
The device according to claim 18, wherein each angled sidewall comprises 111 Si and has an angle of approximately 54.7 degrees and wherein the first Si layer and a remaining portion of the second Si layer comprise 100 Si.
Layer stacks claimed or described, ordered top of device to substrate.
GaN power amplifier structure on 100 Si with V-shaped groove
CMOS transistor on 100 Si
Materials described outside the worked examples.
silicon
Si
gallium nitride
GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1, e.g., a FET, a NPN transistor, a HBT, a MOS capacitor, a deep trench capacitor, a flash memory cell, a magnetic memory cell, a poly resistor, a diffusion …
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,469,041Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1, e.g., a FET, a NPN transistor, a HBT, a MOS capacitor, a deep trench capacitor, a flash memory cell, a magnetic memory cell, a poly resistor, a diffusion …
FIG. 2. The composition of the protective layer 201 is chosen to protect the device 101 during the subsequent GaN processing. The Protective layer 201 may be …
FIG. 3, a photoresist 301 is formed over the Si substrate 103 and the protective layer 201. Then, the photoresist 301 is exposed and developed in the center …
FIG. 4. Specifically, each side of the V-shaped groove 401 is formed at approximately 54.7 degrees, thus having a 111 angled Si surface. [0023] Next, the …
FIG. 5. Alternatively, as described above, the protective layer 201 could be under the opening 303 and may be removed by etching prior to forming the V-shaped …
FIG. 6, a buffer layer 601 is formed, e.g., by a physical vapor deposition (PVD), a chemical vapor deposition (CVD), an atomic layer deposition (ALD), a plasma …
FIG. 7, a conformal or semi-conformal spin-on or dry resist layer 701 is formed, e.g., to a thickness of 0.3 p m to 10 p m by a standard spin-on process and a …
FIG. 8. Next, the passivation layer 607 and the A l GaN layer 605 are etched, e.g., by a wet etching or a plasma etching with, e.g., BCL 3/CL 2 gases, through …
FIG. 9. In one instance, the A l GaN layer 605 may be partially etched, whereupon the etching stops. In another instance, portions of the GaN layer 603 may be …
FIG. 10. A resist layer 1101 is then conformally or semi-conformally formed, e.g., to a thickness of 0.3 p m to 10 p m by a standard spin-on process and a …
FIG. 12. In one instance, the openings 1201 may be formed either on the one side or on the both sides of the V-shaped groove 401 depending on the resultant …
FIG. 13, the passivation layer 607 is etched, e.g., by a wet or a dry etching, through the openings 1201 down to the A l GaN layer 605, forming openings 1201'. …
FIG. 14. [0027] Referring to
FIG. 15, an electrode layer 1501 is formed, e.g., of titanium nitride (TiN), molybdenum (Mo), or any other suitable conductor by CVD, ALD, PVD, or any other …
FIG. 16. In
FIG. 17, a conformal resist layer (not shown for illustrative convenience) is formed over the passivation layer 607 and the electrode structures 1501'. Then, …
FIG. 18, a dielectric layer 1801 is formed over the Si substrate 103 and then planarized as known in the art, e.g., by CMP, etch-back, etc.. Next, vias (not …
FIG. 19 is a cross-sectional view of a different embodiment of a CMOS device and a GaN PA structure formed on a 100 Si substrate having a 111 surface …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method comprising: providing a silicon (Si) substrate with a device over a portion of the Si substrate and a protective layer over the device and a portion of the Si substrate; forming a V-shaped groove in a portion of the Si substrate; forming a buffer layer, a gallium nitride (GaN) layer, an aluminum gallium nitride (AlGaN) layer and a passivation layer sequentially over the Si substrate; forming first trenches through the passivation layer and the AlGaN layer on one or both sides of the V-shaped groove; forming second trenches through the passivation layer on the one or both sides; forming electrode structures over portions of the passivation layer and filling the first trenches and the second trenches; removing portions of the passivation layer, the AlGaN layer and the GaN layer outside of the V-shaped groove down to the buffer layer; forming a dielectric layer over the Si substrate; and forming a via through the dielectric layer down to at least one of the electrode structure and the device.
The method according to claim 1, comprising forming the V-shaped groove by: forming a photo resist or a dielectric layer over the Si substrate; forming a trench through the photo resist or the dielectric layer down to the Si substrate; and performing a wet etch such that each side of the V-shaped groove is at 54.7 degrees.
The method according to claim 1, comprising forming the first trenches by: forming a conformal resist layer over the passivation layer; patterning the conformal resist layer down to the passivation layer; and etching the passivation layer and the AlGaN layer through the patterned conformal resist layer down to the GaN layer.
The method according to claim 1, comprising removing portions of the passivation layer, the AlGaN layer and the GaN layer down to the buffer layer by: forming a conformal resist layer over the passivation layer and the electrode structures; patterning the conformal resist layer over the Si substrate outside of the V-shaped groove down to the passivation layer; and etching the passivation layer, the AlGaN layer and the GaN layer through the patterned conformal resist layer down to the buffer layer.
A device comprising: a complementary metal oxide semiconductor (CMOS) transistor on a 100 silicon (Si); and a gallium nitride (GaN) high electron mobility transistor (HEMT) on a 111 Si, wherein the 100 Si and the 111 Si are contiguous.
The device according to claim 10, wherein the GaN HEMT comprises: a buffer layer over a portion of each surface of a V-shaped groove; a gallium nitride (GaN) layer over the buffer layer; an aluminum gallium nitride (AlGaN) layer over the GaN layer; a passivation layer over the AlGaN layer; a first electrode over a portion of the passivation layer and through the passivation layer and the AlGaN layer down to the GaN layer; a second electrode over a portion of the passivation layer and through the passivation layer down to the AlGaN layer; a dielectric layer over the 111 Si; and a metal-filled via through the dielectric layer down to at least one of the first electrode and the second electrode.
The device according to claim 10, further comprising: a protective layer over the CMOS transistor and on portions of the 100 Si; a dielectric layer over the 100 Si and the protective layer; and a metal-filled via through the dielectric layer and the protective layer to the CMOS transistor.
A device comprising: a first silicon (Si) layer; a silicon germanium (SiGe) layer over the first Si layer; a second Si layer over the SiGe layer with a trench down to the SiGe layer having angled sidewalls; a buffer layer over a portion of each angled sidewall of the trench; a gallium nitride (GaN) layer over the buffer layer; an aluminum gallium nitride (AlGaN) layer over a portion of the GaN layer; a passivation layer over the AlGaN layer; a first electrode structure through the passivation layer and the AlGaN layer down to the GaN layer; a second electrode structure through the passivation layer down to the AlGaN layer; a third electrode structure through the passivation layer and the AlGaN layer down to the GaN layer and over a portion of one of the angled sidewall and the SiGe layer within the trench; a dielectric layer over the first Si layer, filling the trench; a device over a portion of the second Si layer proximate to the trench; and a metal-filled via through the dielectric layer down to each of the first electrode structure, the second electrode structure and the third electrode structure.
The device according to claim 18, further comprising: a second device formed over the SiGe layer within the trench; and a second metal-filled via through the dielectric layer down to the second device.
The device according to claim 18, wherein each angled sidewall comprises 111 Si and has an angle of approximately 54.7 degrees and wherein the first Si layer and a remaining portion of the second Si layer comprise 100 Si.
Layer stacks claimed or described, ordered top of device to substrate.
GaN power amplifier structure on 100 Si with V-shaped groove
CMOS transistor on 100 Si
Materials described outside the worked examples.
silicon
Si
gallium nitride
GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1, e.g., a FET, a NPN transistor, a HBT, a MOS capacitor, a deep trench capacitor, a flash memory cell, a magnetic memory cell, a poly resistor, a diffusion …
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,469,041Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1, e.g., a FET, a NPN transistor, a HBT, a MOS capacitor, a deep trench capacitor, a flash memory cell, a magnetic memory cell, a poly resistor, a diffusion …
FIG. 2. The composition of the protective layer 201 is chosen to protect the device 101 during the subsequent GaN processing. The Protective layer 201 may be …
FIG. 3, a photoresist 301 is formed over the Si substrate 103 and the protective layer 201. Then, the photoresist 301 is exposed and developed in the center …
FIG. 4. Specifically, each side of the V-shaped groove 401 is formed at approximately 54.7 degrees, thus having a 111 angled Si surface. [0023] Next, the …
FIG. 5. Alternatively, as described above, the protective layer 201 could be under the opening 303 and may be removed by etching prior to forming the V-shaped …
FIG. 6, a buffer layer 601 is formed, e.g., by a physical vapor deposition (PVD), a chemical vapor deposition (CVD), an atomic layer deposition (ALD), a plasma …
FIG. 7, a conformal or semi-conformal spin-on or dry resist layer 701 is formed, e.g., to a thickness of 0.3 p m to 10 p m by a standard spin-on process and a …
FIG. 8. Next, the passivation layer 607 and the A l GaN layer 605 are etched, e.g., by a wet etching or a plasma etching with, e.g., BCL 3/CL 2 gases, through …
FIG. 9. In one instance, the A l GaN layer 605 may be partially etched, whereupon the etching stops. In another instance, portions of the GaN layer 603 may be …
FIG. 10. A resist layer 1101 is then conformally or semi-conformally formed, e.g., to a thickness of 0.3 p m to 10 p m by a standard spin-on process and a …
FIG. 12. In one instance, the openings 1201 may be formed either on the one side or on the both sides of the V-shaped groove 401 depending on the resultant …
FIG. 13, the passivation layer 607 is etched, e.g., by a wet or a dry etching, through the openings 1201 down to the A l GaN layer 605, forming openings 1201'. …
FIG. 14. [0027] Referring to
FIG. 15, an electrode layer 1501 is formed, e.g., of titanium nitride (TiN), molybdenum (Mo), or any other suitable conductor by CVD, ALD, PVD, or any other …
FIG. 16. In
FIG. 17, a conformal resist layer (not shown for illustrative convenience) is formed over the passivation layer 607 and the electrode structures 1501'. Then, …
FIG. 18, a dielectric layer 1801 is formed over the Si substrate 103 and then planarized as known in the art, e.g., by CMP, etch-back, etc.. Next, vias (not …
FIG. 19 is a cross-sectional view of a different embodiment of a CMOS device and a GaN PA structure formed on a 100 Si substrate having a 111 surface …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method comprising: providing a silicon (Si) substrate with a device over a portion of the Si substrate and a protective layer over the device and a portion of the Si substrate; forming a V-shaped groove in a portion of the Si substrate; forming a buffer layer, a gallium nitride (GaN) layer, an aluminum gallium nitride (AlGaN) layer and a passivation layer sequentially over the Si substrate; forming first trenches through the passivation layer and the AlGaN layer on one or both sides of the V-shaped groove; forming second trenches through the passivation layer on the one or both sides; forming electrode structures over portions of the passivation layer and filling the first trenches and the second trenches; removing portions of the passivation layer, the AlGaN layer and the GaN layer outside of the V-shaped groove down to the buffer layer; forming a dielectric layer over the Si substrate; and forming a via through the dielectric layer down to at least one of the electrode structure and the device.
The method according to claim 1, comprising forming the V-shaped groove by: forming a photo resist or a dielectric layer over the Si substrate; forming a trench through the photo resist or the dielectric layer down to the Si substrate; and performing a wet etch such that each side of the V-shaped groove is at 54.7 degrees.
The method according to claim 1, comprising forming the first trenches by: forming a conformal resist layer over the passivation layer; patterning the conformal resist layer down to the passivation layer; and etching the passivation layer and the AlGaN layer through the patterned conformal resist layer down to the GaN layer.
The method according to claim 1, comprising removing portions of the passivation layer, the AlGaN layer and the GaN layer down to the buffer layer by: forming a conformal resist layer over the passivation layer and the electrode structures; patterning the conformal resist layer over the Si substrate outside of the V-shaped groove down to the passivation layer; and etching the passivation layer, the AlGaN layer and the GaN layer through the patterned conformal resist layer down to the buffer layer.
A device comprising: a complementary metal oxide semiconductor (CMOS) transistor on a 100 silicon (Si); and a gallium nitride (GaN) high electron mobility transistor (HEMT) on a 111 Si, wherein the 100 Si and the 111 Si are contiguous.
The device according to claim 10, wherein the GaN HEMT comprises: a buffer layer over a portion of each surface of a V-shaped groove; a gallium nitride (GaN) layer over the buffer layer; an aluminum gallium nitride (AlGaN) layer over the GaN layer; a passivation layer over the AlGaN layer; a first electrode over a portion of the passivation layer and through the passivation layer and the AlGaN layer down to the GaN layer; a second electrode over a portion of the passivation layer and through the passivation layer down to the AlGaN layer; a dielectric layer over the 111 Si; and a metal-filled via through the dielectric layer down to at least one of the first electrode and the second electrode.
The device according to claim 10, further comprising: a protective layer over the CMOS transistor and on portions of the 100 Si; a dielectric layer over the 100 Si and the protective layer; and a metal-filled via through the dielectric layer and the protective layer to the CMOS transistor.
A device comprising: a first silicon (Si) layer; a silicon germanium (SiGe) layer over the first Si layer; a second Si layer over the SiGe layer with a trench down to the SiGe layer having angled sidewalls; a buffer layer over a portion of each angled sidewall of the trench; a gallium nitride (GaN) layer over the buffer layer; an aluminum gallium nitride (AlGaN) layer over a portion of the GaN layer; a passivation layer over the AlGaN layer; a first electrode structure through the passivation layer and the AlGaN layer down to the GaN layer; a second electrode structure through the passivation layer down to the AlGaN layer; a third electrode structure through the passivation layer and the AlGaN layer down to the GaN layer and over a portion of one of the angled sidewall and the SiGe layer within the trench; a dielectric layer over the first Si layer, filling the trench; a device over a portion of the second Si layer proximate to the trench; and a metal-filled via through the dielectric layer down to each of the first electrode structure, the second electrode structure and the third electrode structure.
The device according to claim 18, further comprising: a second device formed over the SiGe layer within the trench; and a second metal-filled via through the dielectric layer down to the second device.
The device according to claim 18, wherein each angled sidewall comprises 111 Si and has an angle of approximately 54.7 degrees and wherein the first Si layer and a remaining portion of the second Si layer comprise 100 Si.
Layer stacks claimed or described, ordered top of device to substrate.
GaN power amplifier structure on 100 Si with V-shaped groove
CMOS transistor on 100 Si
Materials described outside the worked examples.
silicon
Si
gallium nitride
GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1, e.g., a FET, a NPN transistor, a HBT, a MOS capacitor, a deep trench capacitor, a flash memory cell, a magnetic memory cell, a poly resistor, a diffusion …
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,469,041Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1, e.g., a FET, a NPN transistor, a HBT, a MOS capacitor, a deep trench capacitor, a flash memory cell, a magnetic memory cell, a poly resistor, a diffusion …
FIG. 2. The composition of the protective layer 201 is chosen to protect the device 101 during the subsequent GaN processing. The Protective layer 201 may be …
FIG. 3, a photoresist 301 is formed over the Si substrate 103 and the protective layer 201. Then, the photoresist 301 is exposed and developed in the center …
FIG. 4. Specifically, each side of the V-shaped groove 401 is formed at approximately 54.7 degrees, thus having a 111 angled Si surface. [0023] Next, the …
FIG. 5. Alternatively, as described above, the protective layer 201 could be under the opening 303 and may be removed by etching prior to forming the V-shaped …
FIG. 6, a buffer layer 601 is formed, e.g., by a physical vapor deposition (PVD), a chemical vapor deposition (CVD), an atomic layer deposition (ALD), a plasma …
FIG. 7, a conformal or semi-conformal spin-on or dry resist layer 701 is formed, e.g., to a thickness of 0.3 p m to 10 p m by a standard spin-on process and a …
FIG. 8. Next, the passivation layer 607 and the A l GaN layer 605 are etched, e.g., by a wet etching or a plasma etching with, e.g., BCL 3/CL 2 gases, through …
FIG. 9. In one instance, the A l GaN layer 605 may be partially etched, whereupon the etching stops. In another instance, portions of the GaN layer 603 may be …
FIG. 10. A resist layer 1101 is then conformally or semi-conformally formed, e.g., to a thickness of 0.3 p m to 10 p m by a standard spin-on process and a …
FIG. 12. In one instance, the openings 1201 may be formed either on the one side or on the both sides of the V-shaped groove 401 depending on the resultant …
FIG. 13, the passivation layer 607 is etched, e.g., by a wet or a dry etching, through the openings 1201 down to the A l GaN layer 605, forming openings 1201'. …
FIG. 14. [0027] Referring to
FIG. 15, an electrode layer 1501 is formed, e.g., of titanium nitride (TiN), molybdenum (Mo), or any other suitable conductor by CVD, ALD, PVD, or any other …
FIG. 16. In
FIG. 17, a conformal resist layer (not shown for illustrative convenience) is formed over the passivation layer 607 and the electrode structures 1501'. Then, …
FIG. 18, a dielectric layer 1801 is formed over the Si substrate 103 and then planarized as known in the art, e.g., by CMP, etch-back, etc.. Next, vias (not …
FIG. 19 is a cross-sectional view of a different embodiment of a CMOS device and a GaN PA structure formed on a 100 Si substrate having a 111 surface …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method comprising: providing a silicon (Si) substrate with a device over a portion of the Si substrate and a protective layer over the device and a portion of the Si substrate; forming a V-shaped groove in a portion of the Si substrate; forming a buffer layer, a gallium nitride (GaN) layer, an aluminum gallium nitride (AlGaN) layer and a passivation layer sequentially over the Si substrate; forming first trenches through the passivation layer and the AlGaN layer on one or both sides of the V-shaped groove; forming second trenches through the passivation layer on the one or both sides; forming electrode structures over portions of the passivation layer and filling the first trenches and the second trenches; removing portions of the passivation layer, the AlGaN layer and the GaN layer outside of the V-shaped groove down to the buffer layer; forming a dielectric layer over the Si substrate; and forming a via through the dielectric layer down to at least one of the electrode structure and the device.
The method according to claim 1, comprising forming the V-shaped groove by: forming a photo resist or a dielectric layer over the Si substrate; forming a trench through the photo resist or the dielectric layer down to the Si substrate; and performing a wet etch such that each side of the V-shaped groove is at 54.7 degrees.
The method according to claim 1, comprising forming the first trenches by: forming a conformal resist layer over the passivation layer; patterning the conformal resist layer down to the passivation layer; and etching the passivation layer and the AlGaN layer through the patterned conformal resist layer down to the GaN layer.
The method according to claim 1, comprising removing portions of the passivation layer, the AlGaN layer and the GaN layer down to the buffer layer by: forming a conformal resist layer over the passivation layer and the electrode structures; patterning the conformal resist layer over the Si substrate outside of the V-shaped groove down to the passivation layer; and etching the passivation layer, the AlGaN layer and the GaN layer through the patterned conformal resist layer down to the buffer layer.
A device comprising: a complementary metal oxide semiconductor (CMOS) transistor on a 100 silicon (Si); and a gallium nitride (GaN) high electron mobility transistor (HEMT) on a 111 Si, wherein the 100 Si and the 111 Si are contiguous.
The device according to claim 10, wherein the GaN HEMT comprises: a buffer layer over a portion of each surface of a V-shaped groove; a gallium nitride (GaN) layer over the buffer layer; an aluminum gallium nitride (AlGaN) layer over the GaN layer; a passivation layer over the AlGaN layer; a first electrode over a portion of the passivation layer and through the passivation layer and the AlGaN layer down to the GaN layer; a second electrode over a portion of the passivation layer and through the passivation layer down to the AlGaN layer; a dielectric layer over the 111 Si; and a metal-filled via through the dielectric layer down to at least one of the first electrode and the second electrode.
The device according to claim 10, further comprising: a protective layer over the CMOS transistor and on portions of the 100 Si; a dielectric layer over the 100 Si and the protective layer; and a metal-filled via through the dielectric layer and the protective layer to the CMOS transistor.
A device comprising: a first silicon (Si) layer; a silicon germanium (SiGe) layer over the first Si layer; a second Si layer over the SiGe layer with a trench down to the SiGe layer having angled sidewalls; a buffer layer over a portion of each angled sidewall of the trench; a gallium nitride (GaN) layer over the buffer layer; an aluminum gallium nitride (AlGaN) layer over a portion of the GaN layer; a passivation layer over the AlGaN layer; a first electrode structure through the passivation layer and the AlGaN layer down to the GaN layer; a second electrode structure through the passivation layer down to the AlGaN layer; a third electrode structure through the passivation layer and the AlGaN layer down to the GaN layer and over a portion of one of the angled sidewall and the SiGe layer within the trench; a dielectric layer over the first Si layer, filling the trench; a device over a portion of the second Si layer proximate to the trench; and a metal-filled via through the dielectric layer down to each of the first electrode structure, the second electrode structure and the third electrode structure.
The device according to claim 18, further comprising: a second device formed over the SiGe layer within the trench; and a second metal-filled via through the dielectric layer down to the second device.
The device according to claim 18, wherein each angled sidewall comprises 111 Si and has an angle of approximately 54.7 degrees and wherein the first Si layer and a remaining portion of the second Si layer comprise 100 Si.
Layer stacks claimed or described, ordered top of device to substrate.
GaN power amplifier structure on 100 Si with V-shaped groove
CMOS transistor on 100 Si
Materials described outside the worked examples.
silicon
Si
gallium nitride
GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1, e.g., a FET, a NPN transistor, a HBT, a MOS capacitor, a deep trench capacitor, a flash memory cell, a magnetic memory cell, a poly resistor, a diffusion …
Related documents with shared materials, methods, properties, or citations.
GaN HEMT on 111 Si
GaN HEMT device with SiGe stop layer and angled trench sidewalls
aluminum gallium nitride
AlGaN
passivation layer
buffer layer
silicon germanium
SiGe
FIG. 7, a conformal or semi-conformal spin-on or dry resist layer 701 is formed, e.g., to a thickness of 0.3 p m to 10 p m by a standard spin-on process and a …
FIG. 10. A resist layer 1101 is then conformally or semi-conformally formed, e.g., to a thickness of 0.3 p m to 10 p m by a standard spin-on process and a …
GaN HEMT on 111 Si
GaN HEMT device with SiGe stop layer and angled trench sidewalls
aluminum gallium nitride
AlGaN
passivation layer
buffer layer
silicon germanium
SiGe
FIG. 7, a conformal or semi-conformal spin-on or dry resist layer 701 is formed, e.g., to a thickness of 0.3 p m to 10 p m by a standard spin-on process and a …
FIG. 10. A resist layer 1101 is then conformally or semi-conformally formed, e.g., to a thickness of 0.3 p m to 10 p m by a standard spin-on process and a …
GaN HEMT on 111 Si
GaN HEMT device with SiGe stop layer and angled trench sidewalls
aluminum gallium nitride
AlGaN
passivation layer
buffer layer
silicon germanium
SiGe
FIG. 7, a conformal or semi-conformal spin-on or dry resist layer 701 is formed, e.g., to a thickness of 0.3 p m to 10 p m by a standard spin-on process and a …
FIG. 10. A resist layer 1101 is then conformally or semi-conformally formed, e.g., to a thickness of 0.3 p m to 10 p m by a standard spin-on process and a …
GaN HEMT on 111 Si
GaN HEMT device with SiGe stop layer and angled trench sidewalls
aluminum gallium nitride
AlGaN
passivation layer
buffer layer
silicon germanium
SiGe
FIG. 7, a conformal or semi-conformal spin-on or dry resist layer 701 is formed, e.g., to a thickness of 0.3 p m to 10 p m by a standard spin-on process and a …
FIG. 10. A resist layer 1101 is then conformally or semi-conformally formed, e.g., to a thickness of 0.3 p m to 10 p m by a standard spin-on process and a …