Patent
US 10,312,378LATERAL GALLIUM NITRIDE JFET WITH CONTROLLED DOPING PROFILE
Vladimir Odnoblyudov, Ozgur Aktas
Qromis, Inc.·US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 10,312,378Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1, lateral junction field-effect transistor (LJFET) 10 includes a substrate 100 of a first conductivity type having a high dopant concentration. For example, …
FIG. 2 is a cross-sectional view illustrating a lateral junction field-effect transistor 20 according to another embodiment of the present disclosure. Lateral …
FIG. 3A. The dopant concentration in Zone 5 is the lowest and is about 1 x 10 17 atoms/cm 3, while the dopant concentration in zone 1 is the highest and is …
FIG. 4 is a flowchart of a method 40 of manufacturing a semiconductor device according to one embodiment of the present disclosure. In the disclosure, each …
FIGS. 5A-5 F are cross-sectional views illustrating intermediate stages of a semiconductor device in a manufacturing method according to one embodiment of the …
FIG. 6. In another embodiment, multiple patterned hardmask layers together with multiple ion implantations with different energy and dopant doses may be used to …
FIG. 7, the dopant concentration in the first portion 2031 is constant (e.g., 2 x 10 19 atoms/cm 3), and the dopant concentration in the second portion 2032 …
FIG. 8 is suitable for a variety of electronic and optical applications. The engineered substrate includes a core 810 that can have a coefficient of thermal …
FIG. 9 is suitable for a variety of electronic and optical applications. The engineered substrate includes a core 910 that can have a coefficient of thermal …
FIG. 10, it will be appreciated that deposition of adhesion layer material on other portions of the core 1010 will not adversely impact the performance of the …
FIG. 11 is a simplified flowchart illustrating a method 1100 of fabricating an engineered substrate according to an embodiment of the present invention. The …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A lateral junction field-effect transistor comprising: a substrate of a first conductivity type having a dopant concentration; a first semiconductor layer of the first conductivity type having a first dopant concentration lower than the dopant concentration of the substrate and disposed on the substrate; a second semiconductor layer of a second conductivity type having a second dopant concentration, the second conductivity type being different from the first conductivity type, the second semiconductor layer disposed on the first semiconductor layer; a third semiconductor layer of the first conductivity type having a thir d dopant concentration, the thir d semiconductor layer disposed on the second semiconductor layer; a fourth semiconductor layer of the first conductivity type having a fourth dopant concentration lower than the dopant concentration, the fourth semiconductor layer disposed on the third semiconductor layer; and a source region and a drain region disposed in the second semiconductor layer and on opposite sides of the third semiconductor layer. Original
The lateral junction field-effect transistor of claim 1 further comprising: a source electrode on the source region; a drain electrode on the drain region; and a gate electrode on the fourth semiconductor layer. Original
The lateral junction field-effect transistor of claim 1 wherein the first dopant concentration and the fourth dopant concentration have a same dopant concentration. Original
The lateral junction field-effect transistor of claim 1 wherein the third dopant concentration of the third semiconductor layer comprises a first portion below the fourth semiconductor layer having a uniformly distributed dopant concentration and a second portion not below the fourth semiconductor layer having a gradually decreasing dopant concentration in a lateral direction toward the drain region. Original
The lateral junction field-effect transistor of claim 1 further comprising an air gap between the third semiconductor layer and the drain region. Original
- 20. Canceled
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
lateral GaN junction field-effect transistor (LJFET)
Materials described outside the worked examples.
GaN substrate (p-type, high dopant concentration)
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1, lateral junction field-effect transistor (LJFET) 10 includes a substrate 100 of a first conductivity type having a high dopant concentration. For example, …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
substrate (p-type GaN) dopant concentration | 10000000000000000000–50000000000000000000 atoms/cm³ | GaN |
first semiconductor layer (p-type GaN) dopant concentration | 500000000000000000–5000000000000000000 atoms/cm³ |
Related documents with shared materials, methods, properties, or citations.
Normally-Off Cubic Phase GaN (c-GaN) HEMT having a Gate Electrode Dielectrically Insulated from a c-AlGaN Capping Layer
ENHANCEMENT MODE GALLIUM NITRIDE TRANSISTOR WITH IMPROVED GATE CHARACTERISTICS
Patent
Atlas literature
Patent
US 10,312,378Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1, lateral junction field-effect transistor (LJFET) 10 includes a substrate 100 of a first conductivity type having a high dopant concentration. For example, …
FIG. 2 is a cross-sectional view illustrating a lateral junction field-effect transistor 20 according to another embodiment of the present disclosure. Lateral …
FIG. 3A. The dopant concentration in Zone 5 is the lowest and is about 1 x 10 17 atoms/cm 3, while the dopant concentration in zone 1 is the highest and is …
FIG. 4 is a flowchart of a method 40 of manufacturing a semiconductor device according to one embodiment of the present disclosure. In the disclosure, each …
FIGS. 5A-5 F are cross-sectional views illustrating intermediate stages of a semiconductor device in a manufacturing method according to one embodiment of the …
FIG. 6. In another embodiment, multiple patterned hardmask layers together with multiple ion implantations with different energy and dopant doses may be used to …
FIG. 7, the dopant concentration in the first portion 2031 is constant (e.g., 2 x 10 19 atoms/cm 3), and the dopant concentration in the second portion 2032 …
FIG. 8 is suitable for a variety of electronic and optical applications. The engineered substrate includes a core 810 that can have a coefficient of thermal …
FIG. 9 is suitable for a variety of electronic and optical applications. The engineered substrate includes a core 910 that can have a coefficient of thermal …
FIG. 10, it will be appreciated that deposition of adhesion layer material on other portions of the core 1010 will not adversely impact the performance of the …
FIG. 11 is a simplified flowchart illustrating a method 1100 of fabricating an engineered substrate according to an embodiment of the present invention. The …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A lateral junction field-effect transistor comprising: a substrate of a first conductivity type having a dopant concentration; a first semiconductor layer of the first conductivity type having a first dopant concentration lower than the dopant concentration of the substrate and disposed on the substrate; a second semiconductor layer of a second conductivity type having a second dopant concentration, the second conductivity type being different from the first conductivity type, the second semiconductor layer disposed on the first semiconductor layer; a third semiconductor layer of the first conductivity type having a thir d dopant concentration, the thir d semiconductor layer disposed on the second semiconductor layer; a fourth semiconductor layer of the first conductivity type having a fourth dopant concentration lower than the dopant concentration, the fourth semiconductor layer disposed on the third semiconductor layer; and a source region and a drain region disposed in the second semiconductor layer and on opposite sides of the third semiconductor layer. Original
The lateral junction field-effect transistor of claim 1 further comprising: a source electrode on the source region; a drain electrode on the drain region; and a gate electrode on the fourth semiconductor layer. Original
The lateral junction field-effect transistor of claim 1 wherein the first dopant concentration and the fourth dopant concentration have a same dopant concentration. Original
The lateral junction field-effect transistor of claim 1 wherein the third dopant concentration of the third semiconductor layer comprises a first portion below the fourth semiconductor layer having a uniformly distributed dopant concentration and a second portion not below the fourth semiconductor layer having a gradually decreasing dopant concentration in a lateral direction toward the drain region. Original
The lateral junction field-effect transistor of claim 1 further comprising an air gap between the third semiconductor layer and the drain region. Original
- 20. Canceled
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
lateral GaN junction field-effect transistor (LJFET)
Materials described outside the worked examples.
GaN substrate (p-type, high dopant concentration)
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1, lateral junction field-effect transistor (LJFET) 10 includes a substrate 100 of a first conductivity type having a high dopant concentration. For example, …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
substrate (p-type GaN) dopant concentration | 10000000000000000000–50000000000000000000 atoms/cm³ | GaN |
first semiconductor layer (p-type GaN) dopant concentration | 500000000000000000–5000000000000000000 atoms/cm³ |
Related documents with shared materials, methods, properties, or citations.
Normally-Off Cubic Phase GaN (c-GaN) HEMT having a Gate Electrode Dielectrically Insulated from a c-AlGaN Capping Layer
ENHANCEMENT MODE GALLIUM NITRIDE TRANSISTOR WITH IMPROVED GATE CHARACTERISTICS
Patent
Atlas literature
Patent
US 10,312,378Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1, lateral junction field-effect transistor (LJFET) 10 includes a substrate 100 of a first conductivity type having a high dopant concentration. For example, …
FIG. 2 is a cross-sectional view illustrating a lateral junction field-effect transistor 20 according to another embodiment of the present disclosure. Lateral …
FIG. 3A. The dopant concentration in Zone 5 is the lowest and is about 1 x 10 17 atoms/cm 3, while the dopant concentration in zone 1 is the highest and is …
FIG. 4 is a flowchart of a method 40 of manufacturing a semiconductor device according to one embodiment of the present disclosure. In the disclosure, each …
FIGS. 5A-5 F are cross-sectional views illustrating intermediate stages of a semiconductor device in a manufacturing method according to one embodiment of the …
FIG. 6. In another embodiment, multiple patterned hardmask layers together with multiple ion implantations with different energy and dopant doses may be used to …
FIG. 7, the dopant concentration in the first portion 2031 is constant (e.g., 2 x 10 19 atoms/cm 3), and the dopant concentration in the second portion 2032 …
FIG. 8 is suitable for a variety of electronic and optical applications. The engineered substrate includes a core 810 that can have a coefficient of thermal …
FIG. 9 is suitable for a variety of electronic and optical applications. The engineered substrate includes a core 910 that can have a coefficient of thermal …
FIG. 10, it will be appreciated that deposition of adhesion layer material on other portions of the core 1010 will not adversely impact the performance of the …
FIG. 11 is a simplified flowchart illustrating a method 1100 of fabricating an engineered substrate according to an embodiment of the present invention. The …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A lateral junction field-effect transistor comprising: a substrate of a first conductivity type having a dopant concentration; a first semiconductor layer of the first conductivity type having a first dopant concentration lower than the dopant concentration of the substrate and disposed on the substrate; a second semiconductor layer of a second conductivity type having a second dopant concentration, the second conductivity type being different from the first conductivity type, the second semiconductor layer disposed on the first semiconductor layer; a third semiconductor layer of the first conductivity type having a thir d dopant concentration, the thir d semiconductor layer disposed on the second semiconductor layer; a fourth semiconductor layer of the first conductivity type having a fourth dopant concentration lower than the dopant concentration, the fourth semiconductor layer disposed on the third semiconductor layer; and a source region and a drain region disposed in the second semiconductor layer and on opposite sides of the third semiconductor layer. Original
The lateral junction field-effect transistor of claim 1 further comprising: a source electrode on the source region; a drain electrode on the drain region; and a gate electrode on the fourth semiconductor layer. Original
The lateral junction field-effect transistor of claim 1 wherein the first dopant concentration and the fourth dopant concentration have a same dopant concentration. Original
The lateral junction field-effect transistor of claim 1 wherein the third dopant concentration of the third semiconductor layer comprises a first portion below the fourth semiconductor layer having a uniformly distributed dopant concentration and a second portion not below the fourth semiconductor layer having a gradually decreasing dopant concentration in a lateral direction toward the drain region. Original
The lateral junction field-effect transistor of claim 1 further comprising an air gap between the third semiconductor layer and the drain region. Original
- 20. Canceled
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
lateral GaN junction field-effect transistor (LJFET)
Materials described outside the worked examples.
GaN substrate (p-type, high dopant concentration)
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1, lateral junction field-effect transistor (LJFET) 10 includes a substrate 100 of a first conductivity type having a high dopant concentration. For example, …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
substrate (p-type GaN) dopant concentration | 10000000000000000000–50000000000000000000 atoms/cm³ | GaN |
first semiconductor layer (p-type GaN) dopant concentration | 500000000000000000–5000000000000000000 atoms/cm³ |
Related documents with shared materials, methods, properties, or citations.
Normally-Off Cubic Phase GaN (c-GaN) HEMT having a Gate Electrode Dielectrically Insulated from a c-AlGaN Capping Layer
ENHANCEMENT MODE GALLIUM NITRIDE TRANSISTOR WITH IMPROVED GATE CHARACTERISTICS
Patent
Atlas literature
Patent
US 10,312,378Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1, lateral junction field-effect transistor (LJFET) 10 includes a substrate 100 of a first conductivity type having a high dopant concentration. For example, …
FIG. 2 is a cross-sectional view illustrating a lateral junction field-effect transistor 20 according to another embodiment of the present disclosure. Lateral …
FIG. 3A. The dopant concentration in Zone 5 is the lowest and is about 1 x 10 17 atoms/cm 3, while the dopant concentration in zone 1 is the highest and is …
FIG. 4 is a flowchart of a method 40 of manufacturing a semiconductor device according to one embodiment of the present disclosure. In the disclosure, each …
FIGS. 5A-5 F are cross-sectional views illustrating intermediate stages of a semiconductor device in a manufacturing method according to one embodiment of the …
FIG. 6. In another embodiment, multiple patterned hardmask layers together with multiple ion implantations with different energy and dopant doses may be used to …
FIG. 7, the dopant concentration in the first portion 2031 is constant (e.g., 2 x 10 19 atoms/cm 3), and the dopant concentration in the second portion 2032 …
FIG. 8 is suitable for a variety of electronic and optical applications. The engineered substrate includes a core 810 that can have a coefficient of thermal …
FIG. 9 is suitable for a variety of electronic and optical applications. The engineered substrate includes a core 910 that can have a coefficient of thermal …
FIG. 10, it will be appreciated that deposition of adhesion layer material on other portions of the core 1010 will not adversely impact the performance of the …
FIG. 11 is a simplified flowchart illustrating a method 1100 of fabricating an engineered substrate according to an embodiment of the present invention. The …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A lateral junction field-effect transistor comprising: a substrate of a first conductivity type having a dopant concentration; a first semiconductor layer of the first conductivity type having a first dopant concentration lower than the dopant concentration of the substrate and disposed on the substrate; a second semiconductor layer of a second conductivity type having a second dopant concentration, the second conductivity type being different from the first conductivity type, the second semiconductor layer disposed on the first semiconductor layer; a third semiconductor layer of the first conductivity type having a thir d dopant concentration, the thir d semiconductor layer disposed on the second semiconductor layer; a fourth semiconductor layer of the first conductivity type having a fourth dopant concentration lower than the dopant concentration, the fourth semiconductor layer disposed on the third semiconductor layer; and a source region and a drain region disposed in the second semiconductor layer and on opposite sides of the third semiconductor layer. Original
The lateral junction field-effect transistor of claim 1 further comprising: a source electrode on the source region; a drain electrode on the drain region; and a gate electrode on the fourth semiconductor layer. Original
The lateral junction field-effect transistor of claim 1 wherein the first dopant concentration and the fourth dopant concentration have a same dopant concentration. Original
The lateral junction field-effect transistor of claim 1 wherein the third dopant concentration of the third semiconductor layer comprises a first portion below the fourth semiconductor layer having a uniformly distributed dopant concentration and a second portion not below the fourth semiconductor layer having a gradually decreasing dopant concentration in a lateral direction toward the drain region. Original
The lateral junction field-effect transistor of claim 1 further comprising an air gap between the third semiconductor layer and the drain region. Original
- 20. Canceled
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
lateral GaN junction field-effect transistor (LJFET)
Materials described outside the worked examples.
GaN substrate (p-type, high dopant concentration)
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1, lateral junction field-effect transistor (LJFET) 10 includes a substrate 100 of a first conductivity type having a high dopant concentration. For example, …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
substrate (p-type GaN) dopant concentration | 10000000000000000000–50000000000000000000 atoms/cm³ | GaN |
first semiconductor layer (p-type GaN) dopant concentration | 500000000000000000–5000000000000000000 atoms/cm³ |
Related documents with shared materials, methods, properties, or citations.
Normally-Off Cubic Phase GaN (c-GaN) HEMT having a Gate Electrode Dielectrically Insulated from a c-AlGaN Capping Layer
ENHANCEMENT MODE GALLIUM NITRIDE TRANSISTOR WITH IMPROVED GATE CHARACTERISTICS
FIG. 2 is a cross-sectional view illustrating a lateral junction field-effect transistor 20 according to another embodiment of the present disclosure. Lateral …
FIG. 3A. The dopant concentration in Zone 5 is the lowest and is about 1 x 10 17 atoms/cm 3, while the dopant concentration in zone 1 is the highest and is …
FIG. 6. In another embodiment, multiple patterned hardmask layers together with multiple ion implantations with different energy and dopant doses may be used to …
FIG. 7, the dopant concentration in the first portion 2031 is constant (e.g., 2 x 10 19 atoms/cm 3), and the dopant concentration in the second portion 2032 …
FIG. 10, it will be appreciated that deposition of adhesion layer material on other portions of the core 1010 will not adversely impact the performance of the …
FIG. 10, it will be appreciated that deposition of adhesion layer material on other portions of the core 1010 will not adversely impact the performance of the …
GaN |
second semiconductor layer (n-type GaN) dopant concentration | 5000000000000000–50000000000000000 atoms/cm³ | GaN |
third semiconductor layer (p-type GaN, blocking layer) dopant concentration | 1000000000000000–9000000000000000 atoms/cm³ | GaN |
fourth semiconductor layer (p-type GaN, gate layer) dopant concentration | 500000000000000000–5000000000000000000 atoms/cm³ | GaN |
third semiconductor layer (blocking layer) alternative dopant concentration range | 5000000000000000–50000000000000000 atoms/cm³ | GaN |
channel region thickness | — | GaN |
fourth semiconductor layer (gate) length | — | GaN |
Thickness | ≤ 0.1 nm | — |
Thickness | ≤ 1 nm | — |
Thickness | ≤ 0.5 nm | — |
Thickness | ≤ 0.2 nm | — |
Voltage | ≥ 600 V | — |
FIG. 2 is a cross-sectional view illustrating a lateral junction field-effect transistor 20 according to another embodiment of the present disclosure. Lateral …
FIG. 3A. The dopant concentration in Zone 5 is the lowest and is about 1 x 10 17 atoms/cm 3, while the dopant concentration in zone 1 is the highest and is …
FIG. 6. In another embodiment, multiple patterned hardmask layers together with multiple ion implantations with different energy and dopant doses may be used to …
FIG. 7, the dopant concentration in the first portion 2031 is constant (e.g., 2 x 10 19 atoms/cm 3), and the dopant concentration in the second portion 2032 …
FIG. 10, it will be appreciated that deposition of adhesion layer material on other portions of the core 1010 will not adversely impact the performance of the …
FIG. 10, it will be appreciated that deposition of adhesion layer material on other portions of the core 1010 will not adversely impact the performance of the …
GaN |
second semiconductor layer (n-type GaN) dopant concentration | 5000000000000000–50000000000000000 atoms/cm³ | GaN |
third semiconductor layer (p-type GaN, blocking layer) dopant concentration | 1000000000000000–9000000000000000 atoms/cm³ | GaN |
fourth semiconductor layer (p-type GaN, gate layer) dopant concentration | 500000000000000000–5000000000000000000 atoms/cm³ | GaN |
third semiconductor layer (blocking layer) alternative dopant concentration range | 5000000000000000–50000000000000000 atoms/cm³ | GaN |
channel region thickness | — | GaN |
fourth semiconductor layer (gate) length | — | GaN |
Thickness | ≤ 0.1 nm | — |
Thickness | ≤ 1 nm | — |
Thickness | ≤ 0.5 nm | — |
Thickness | ≤ 0.2 nm | — |
Voltage | ≥ 600 V | — |
FIG. 2 is a cross-sectional view illustrating a lateral junction field-effect transistor 20 according to another embodiment of the present disclosure. Lateral …
FIG. 3A. The dopant concentration in Zone 5 is the lowest and is about 1 x 10 17 atoms/cm 3, while the dopant concentration in zone 1 is the highest and is …
FIG. 6. In another embodiment, multiple patterned hardmask layers together with multiple ion implantations with different energy and dopant doses may be used to …
FIG. 7, the dopant concentration in the first portion 2031 is constant (e.g., 2 x 10 19 atoms/cm 3), and the dopant concentration in the second portion 2032 …
FIG. 10, it will be appreciated that deposition of adhesion layer material on other portions of the core 1010 will not adversely impact the performance of the …
FIG. 10, it will be appreciated that deposition of adhesion layer material on other portions of the core 1010 will not adversely impact the performance of the …
GaN |
second semiconductor layer (n-type GaN) dopant concentration | 5000000000000000–50000000000000000 atoms/cm³ | GaN |
third semiconductor layer (p-type GaN, blocking layer) dopant concentration | 1000000000000000–9000000000000000 atoms/cm³ | GaN |
fourth semiconductor layer (p-type GaN, gate layer) dopant concentration | 500000000000000000–5000000000000000000 atoms/cm³ | GaN |
third semiconductor layer (blocking layer) alternative dopant concentration range | 5000000000000000–50000000000000000 atoms/cm³ | GaN |
channel region thickness | — | GaN |
fourth semiconductor layer (gate) length | — | GaN |
Thickness | ≤ 0.1 nm | — |
Thickness | ≤ 1 nm | — |
Thickness | ≤ 0.5 nm | — |
Thickness | ≤ 0.2 nm | — |
Voltage | ≥ 600 V | — |
FIG. 2 is a cross-sectional view illustrating a lateral junction field-effect transistor 20 according to another embodiment of the present disclosure. Lateral …
FIG. 3A. The dopant concentration in Zone 5 is the lowest and is about 1 x 10 17 atoms/cm 3, while the dopant concentration in zone 1 is the highest and is …
FIG. 6. In another embodiment, multiple patterned hardmask layers together with multiple ion implantations with different energy and dopant doses may be used to …
FIG. 7, the dopant concentration in the first portion 2031 is constant (e.g., 2 x 10 19 atoms/cm 3), and the dopant concentration in the second portion 2032 …
FIG. 10, it will be appreciated that deposition of adhesion layer material on other portions of the core 1010 will not adversely impact the performance of the …
FIG. 10, it will be appreciated that deposition of adhesion layer material on other portions of the core 1010 will not adversely impact the performance of the …
GaN |
second semiconductor layer (n-type GaN) dopant concentration | 5000000000000000–50000000000000000 atoms/cm³ | GaN |
third semiconductor layer (p-type GaN, blocking layer) dopant concentration | 1000000000000000–9000000000000000 atoms/cm³ | GaN |
fourth semiconductor layer (p-type GaN, gate layer) dopant concentration | 500000000000000000–5000000000000000000 atoms/cm³ | GaN |
third semiconductor layer (blocking layer) alternative dopant concentration range | 5000000000000000–50000000000000000 atoms/cm³ | GaN |
channel region thickness | — | GaN |
fourth semiconductor layer (gate) length | — | GaN |
Thickness | ≤ 0.1 nm | — |
Thickness | ≤ 1 nm | — |
Thickness | ≤ 0.5 nm | — |
Thickness | ≤ 0.2 nm | — |
Voltage | ≥ 600 V | — |