Patent
US 8,964,491GRAPHENE-BASED MEMORY DEVICES AND METHODS THEREFOR
Franz Michael Schuette
US
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Atlas literature
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US 8,964,491Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 schematically represents a honeycomb crystal lattice 3 B₃-381 8 arrangement of carbon atoms typical in a sheet of graphene. [0012]
FIG. 2 schematically represents a side view showing the relative positions of the crystal lattices of two graphene monolayers arranged so that their lattice …
FIG. 3 schematically represents side and plan views showing the relative positions of the crystal lattices of three graphene monolayers arranged in a Bernal …
FIG. 4 schematically represents a perspective view of a memory cell of a semiconductor memory device, in which the memory cell comprises a graphene stack …
FIG. 5 schematically represents a plan view of a memory cell similar to
FIG. 6 schematically represents a perspective view of a memory cell similar to
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
The method of claim 9, further comprising sensing data stored in the memory cells as a level of conductance through the graphene stacks thereof in the plane defined thereby.
The method of claim 9, wherein the memory cells are arranged in rows and columns and the method further comprises addressing the rows and columns through a row-select and a column-select strobe.
The method of claim 9, further comprising generating an electrical field within at least one of the memory cells through an electrode separated from the graphene stack thereof by an insulating layer.
The method of claim 9, wherein the in-plane conductivity of the graphene stack is altered by applying the programming voltage to the bit line. Claim 14: The method of claim 9, wherein the in-plane conductivity of the graphene stack is altered by applying the programming voltage between a voltage connection and a second ground connection that are aligned to have a substantially orthogonal orientation to the conductive path defined by and between the bit line and the ground connection in the plane of the graphene stack.
In Claim 15: 1-2 Claim 15, Line, the phrase "a semiconductor memory device" has been changed to -the C ange W₅ app lied to d ocument, semiconductor memory device of claim 1 --;/J.A./+ 12/2)/201 4- Application/Control Number: 13/775,916 Page 5 Art Unit: 2827 3 Ch ange(s) appl i ed Claim 15, Line t, the phrase "providing at least three grapheme layers on a substrate" has been to doc um ent, changed to -providing the at least three grapheme layers on the substrate--; S₂₀₁₄ Claim 15, Line 4., the phrase "a graphene stack disposed in a plane" has been changed to --the graphene stack disposed in the plane "; Claim 15, Line s, the phrase "a bit line and a ground" has been changed to -the bit line and the ground--; and, Claim 15, Line A, the phrase "a conductive" has been changed to -the conductive--.
The method of claim 15, further comprising connecting the bit line via a select gate to a programming voltage source.
The method of claim 15, further comprising: connecting the graphene stack to a voltage connection and a second ground connection that are aligned to have a substantially orthogonal orientation to the conductive path defined by and between the bit line and the ground connection in the plane of the graphene stack; and connecting the voltage connection to a programming voltage source.
The method of claim 15, further comprising: depositing an insulating layer on the graphene stack; disposing an electrode on the insulating layer; and generating with the electrode an electrical field orthogonal to the plane defined by the graphene stack.
The method of claim 15, wherein the at least three graphene layers are provided on the substrate by epitaxial growth and/or deposition.
The method of claim 15, wherein the at least three graphene layers are provided on the substrate by creating and stacking carbon nano-ribbons on the substrate.
Layer stacks claimed or described, ordered top of device to substrate.
graphene-based semiconductor memory cell
Materials described outside the worked examples.
graphene stack
graphene monolayer
carbon nano-ribbons
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
carbon-carbon bond length in graphene | 0.142 nm | graphene monolayer |
interplanar spacing between decoupled graphene monolayers in graphite |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,964,491Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 schematically represents a honeycomb crystal lattice 3 B₃-381 8 arrangement of carbon atoms typical in a sheet of graphene. [0012]
FIG. 2 schematically represents a side view showing the relative positions of the crystal lattices of two graphene monolayers arranged so that their lattice …
FIG. 3 schematically represents side and plan views showing the relative positions of the crystal lattices of three graphene monolayers arranged in a Bernal …
FIG. 4 schematically represents a perspective view of a memory cell of a semiconductor memory device, in which the memory cell comprises a graphene stack …
FIG. 5 schematically represents a plan view of a memory cell similar to
FIG. 6 schematically represents a perspective view of a memory cell similar to
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
The method of claim 9, further comprising sensing data stored in the memory cells as a level of conductance through the graphene stacks thereof in the plane defined thereby.
The method of claim 9, wherein the memory cells are arranged in rows and columns and the method further comprises addressing the rows and columns through a row-select and a column-select strobe.
The method of claim 9, further comprising generating an electrical field within at least one of the memory cells through an electrode separated from the graphene stack thereof by an insulating layer.
The method of claim 9, wherein the in-plane conductivity of the graphene stack is altered by applying the programming voltage to the bit line. Claim 14: The method of claim 9, wherein the in-plane conductivity of the graphene stack is altered by applying the programming voltage between a voltage connection and a second ground connection that are aligned to have a substantially orthogonal orientation to the conductive path defined by and between the bit line and the ground connection in the plane of the graphene stack.
In Claim 15: 1-2 Claim 15, Line, the phrase "a semiconductor memory device" has been changed to -the C ange W₅ app lied to d ocument, semiconductor memory device of claim 1 --;/J.A./+ 12/2)/201 4- Application/Control Number: 13/775,916 Page 5 Art Unit: 2827 3 Ch ange(s) appl i ed Claim 15, Line t, the phrase "providing at least three grapheme layers on a substrate" has been to doc um ent, changed to -providing the at least three grapheme layers on the substrate--; S₂₀₁₄ Claim 15, Line 4., the phrase "a graphene stack disposed in a plane" has been changed to --the graphene stack disposed in the plane "; Claim 15, Line s, the phrase "a bit line and a ground" has been changed to -the bit line and the ground--; and, Claim 15, Line A, the phrase "a conductive" has been changed to -the conductive--.
The method of claim 15, further comprising connecting the bit line via a select gate to a programming voltage source.
The method of claim 15, further comprising: connecting the graphene stack to a voltage connection and a second ground connection that are aligned to have a substantially orthogonal orientation to the conductive path defined by and between the bit line and the ground connection in the plane of the graphene stack; and connecting the voltage connection to a programming voltage source.
The method of claim 15, further comprising: depositing an insulating layer on the graphene stack; disposing an electrode on the insulating layer; and generating with the electrode an electrical field orthogonal to the plane defined by the graphene stack.
The method of claim 15, wherein the at least three graphene layers are provided on the substrate by epitaxial growth and/or deposition.
The method of claim 15, wherein the at least three graphene layers are provided on the substrate by creating and stacking carbon nano-ribbons on the substrate.
Layer stacks claimed or described, ordered top of device to substrate.
graphene-based semiconductor memory cell
Materials described outside the worked examples.
graphene stack
graphene monolayer
carbon nano-ribbons
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
carbon-carbon bond length in graphene | 0.142 nm | graphene monolayer |
interplanar spacing between decoupled graphene monolayers in graphite |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,964,491Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 schematically represents a honeycomb crystal lattice 3 B₃-381 8 arrangement of carbon atoms typical in a sheet of graphene. [0012]
FIG. 2 schematically represents a side view showing the relative positions of the crystal lattices of two graphene monolayers arranged so that their lattice …
FIG. 3 schematically represents side and plan views showing the relative positions of the crystal lattices of three graphene monolayers arranged in a Bernal …
FIG. 4 schematically represents a perspective view of a memory cell of a semiconductor memory device, in which the memory cell comprises a graphene stack …
FIG. 5 schematically represents a plan view of a memory cell similar to
FIG. 6 schematically represents a perspective view of a memory cell similar to
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
The method of claim 9, further comprising sensing data stored in the memory cells as a level of conductance through the graphene stacks thereof in the plane defined thereby.
The method of claim 9, wherein the memory cells are arranged in rows and columns and the method further comprises addressing the rows and columns through a row-select and a column-select strobe.
The method of claim 9, further comprising generating an electrical field within at least one of the memory cells through an electrode separated from the graphene stack thereof by an insulating layer.
The method of claim 9, wherein the in-plane conductivity of the graphene stack is altered by applying the programming voltage to the bit line. Claim 14: The method of claim 9, wherein the in-plane conductivity of the graphene stack is altered by applying the programming voltage between a voltage connection and a second ground connection that are aligned to have a substantially orthogonal orientation to the conductive path defined by and between the bit line and the ground connection in the plane of the graphene stack.
In Claim 15: 1-2 Claim 15, Line, the phrase "a semiconductor memory device" has been changed to -the C ange W₅ app lied to d ocument, semiconductor memory device of claim 1 --;/J.A./+ 12/2)/201 4- Application/Control Number: 13/775,916 Page 5 Art Unit: 2827 3 Ch ange(s) appl i ed Claim 15, Line t, the phrase "providing at least three grapheme layers on a substrate" has been to doc um ent, changed to -providing the at least three grapheme layers on the substrate--; S₂₀₁₄ Claim 15, Line 4., the phrase "a graphene stack disposed in a plane" has been changed to --the graphene stack disposed in the plane "; Claim 15, Line s, the phrase "a bit line and a ground" has been changed to -the bit line and the ground--; and, Claim 15, Line A, the phrase "a conductive" has been changed to -the conductive--.
The method of claim 15, further comprising connecting the bit line via a select gate to a programming voltage source.
The method of claim 15, further comprising: connecting the graphene stack to a voltage connection and a second ground connection that are aligned to have a substantially orthogonal orientation to the conductive path defined by and between the bit line and the ground connection in the plane of the graphene stack; and connecting the voltage connection to a programming voltage source.
The method of claim 15, further comprising: depositing an insulating layer on the graphene stack; disposing an electrode on the insulating layer; and generating with the electrode an electrical field orthogonal to the plane defined by the graphene stack.
The method of claim 15, wherein the at least three graphene layers are provided on the substrate by epitaxial growth and/or deposition.
The method of claim 15, wherein the at least three graphene layers are provided on the substrate by creating and stacking carbon nano-ribbons on the substrate.
Layer stacks claimed or described, ordered top of device to substrate.
graphene-based semiconductor memory cell
Materials described outside the worked examples.
graphene stack
graphene monolayer
carbon nano-ribbons
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
carbon-carbon bond length in graphene | 0.142 nm | graphene monolayer |
interplanar spacing between decoupled graphene monolayers in graphite |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,964,491Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 schematically represents a honeycomb crystal lattice 3 B₃-381 8 arrangement of carbon atoms typical in a sheet of graphene. [0012]
FIG. 2 schematically represents a side view showing the relative positions of the crystal lattices of two graphene monolayers arranged so that their lattice …
FIG. 3 schematically represents side and plan views showing the relative positions of the crystal lattices of three graphene monolayers arranged in a Bernal …
FIG. 4 schematically represents a perspective view of a memory cell of a semiconductor memory device, in which the memory cell comprises a graphene stack …
FIG. 5 schematically represents a plan view of a memory cell similar to
FIG. 6 schematically represents a perspective view of a memory cell similar to
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
The method of claim 9, further comprising sensing data stored in the memory cells as a level of conductance through the graphene stacks thereof in the plane defined thereby.
The method of claim 9, wherein the memory cells are arranged in rows and columns and the method further comprises addressing the rows and columns through a row-select and a column-select strobe.
The method of claim 9, further comprising generating an electrical field within at least one of the memory cells through an electrode separated from the graphene stack thereof by an insulating layer.
The method of claim 9, wherein the in-plane conductivity of the graphene stack is altered by applying the programming voltage to the bit line. Claim 14: The method of claim 9, wherein the in-plane conductivity of the graphene stack is altered by applying the programming voltage between a voltage connection and a second ground connection that are aligned to have a substantially orthogonal orientation to the conductive path defined by and between the bit line and the ground connection in the plane of the graphene stack.
In Claim 15: 1-2 Claim 15, Line, the phrase "a semiconductor memory device" has been changed to -the C ange W₅ app lied to d ocument, semiconductor memory device of claim 1 --;/J.A./+ 12/2)/201 4- Application/Control Number: 13/775,916 Page 5 Art Unit: 2827 3 Ch ange(s) appl i ed Claim 15, Line t, the phrase "providing at least three grapheme layers on a substrate" has been to doc um ent, changed to -providing the at least three grapheme layers on the substrate--; S₂₀₁₄ Claim 15, Line 4., the phrase "a graphene stack disposed in a plane" has been changed to --the graphene stack disposed in the plane "; Claim 15, Line s, the phrase "a bit line and a ground" has been changed to -the bit line and the ground--; and, Claim 15, Line A, the phrase "a conductive" has been changed to -the conductive--.
The method of claim 15, further comprising connecting the bit line via a select gate to a programming voltage source.
The method of claim 15, further comprising: connecting the graphene stack to a voltage connection and a second ground connection that are aligned to have a substantially orthogonal orientation to the conductive path defined by and between the bit line and the ground connection in the plane of the graphene stack; and connecting the voltage connection to a programming voltage source.
The method of claim 15, further comprising: depositing an insulating layer on the graphene stack; disposing an electrode on the insulating layer; and generating with the electrode an electrical field orthogonal to the plane defined by the graphene stack.
The method of claim 15, wherein the at least three graphene layers are provided on the substrate by epitaxial growth and/or deposition.
The method of claim 15, wherein the at least three graphene layers are provided on the substrate by creating and stacking carbon nano-ribbons on the substrate.
Layer stacks claimed or described, ordered top of device to substrate.
graphene-based semiconductor memory cell
Materials described outside the worked examples.
graphene stack
graphene monolayer
carbon nano-ribbons
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
carbon-carbon bond length in graphene | 0.142 nm | graphene monolayer |
interplanar spacing between decoupled graphene monolayers in graphite |
Related documents with shared materials, methods, properties, or citations.
silicon carbide
SiC
insulating layer
| 0.335 nm |
graphene monolayer |
silicon carbide
SiC
insulating layer
| 0.335 nm |
graphene monolayer |
silicon carbide
SiC
insulating layer
| 0.335 nm |
graphene monolayer |
silicon carbide
SiC
insulating layer
| 0.335 nm |
graphene monolayer |