(Cu rr ently Amended) A monolithically integrated semiconductor assembly, comprising: a substrate comprising silicon carbide (Si C); a gallium nitride (GaN) semiconductor device fabricated on the substrate, wherein the GaN semiconductor device comprises a high electron mobility transistor (HEMT), a junction gate field effect transistor (J FET), or a metal-oxide-semiconductor field-effect transistor (MOSFET); and in addition to the GaN semiconductor device, at least one transient voltage suppressor (TVS) structure fabricated in or on the substrate, comprising: a first semiconductor region having a first conductivity type; a second semiconductor region having a second conductivity type, and in electrical contact with the first semiconductor region; and a third semiconductor region having a first conductivity type, and in electrical contact with the second semiconductor region, an d- whe fe-in such that the TVS structure is configured to operate in a punch-through mode, an avalanehe mode, or combinations ther when an applied voltage across the GaN semiconductor device is greater than a threshold voltage.

canceled

The monolithically integrated semiconductor assembly of claim [[5]] 1, wherein the first conductivity type is n + -type and the second conductivity type is p-type.

The monolithically integrated semiconductor assembly of claim [[5]] 1, wherein the first semiconductor region, the second semiconductor region, and the third semiconductor region are formed in the SiC substrate.

The monolithically integrated semiconductor assembly of claim [[5]] 1, wherein the first semiconductor region, the second semiconductor region, and the third semiconductor region are epitaxially grown on the SiC substrate.

The monolithically integrated semiconductor assembly of claim [[5]] 1, wherein the TVS structure further comprises a GaN layer disposed on at least a portion of the SiC substrate, and wherein the first semiconductor region, the second semiconductor region, and the third semiconductor region are formed in the GaN layer.

canceled

A monolithically integrated semiconductor assembly, comprising: a substrate comprising silicon carbide (SiC); a gallium nitride (GaN) semiconductor device fabricated on the substrate, wherein the GaN semiconductor device comprises a high electron mobility transistor (HEMT); and in addition to the GaN semiconductor device, at least one transient voltage suppressor (TVS) structure comprising silicon carbide (Si C) fabricated in or on the substrate, comprising: a first semiconductor region having a first conductivity type; 3 of 11 Application No. 13/931,363 Reply to Office Action of a second semiconductor region having a second conductivity type, and in electrical contact with the first semiconductor region; and a third semiconductor region having a first conductivity type, and in electrical contact with the second semiconductor region; wherein the TVS structure is in electrical contact with the GaN semiconductor device, and whe fe-ia such that the TVS structure is configured to operate in a punch-through mode when an applied voltage across the GaN semiconductor device is greater than a threshold voltage.

A method of making a monolithically integrated semiconductor assembly comprising: (a) providing a substrate comprising silicon carbide (SiC); (b) fabricating a gallium nitride (GaN) semiconductor device on the substrate, wherein the GaN semiconductor device comprises a high electron mobility transistor (HEMT), a junction gate field effect transistor (J FET), or a metal-oxide-semiconductor field-effect transistor (MOSFET); (c) in addition to the GaN semiconductor device, fabricating at least one transient voltage suppressor (TVS) in or on the substrate, the at least one TVS comprising: a first semiconductor region having a first conductivity type; a second semiconductor region having a second conductivity type, and in electrical contact with the first semiconductor region; and a third semiconductor region having a first conductivity type, and in electrical contact with the second semiconductor region; and 4 of 11 Application No. 13/931,363 Reply to Office Action of (d) electrically coupling the TVS structure with the GaN semiconductor device, wherein the TVS structure is configured to operate in a punch-through mode, an avalache mode, or ombinations thereof, when an applied voltage across the GaN semiconductor device is greater than a threshold voltage. currently amended

canceled

The method of claim [[17]] 16, wherein the first conductivity type is n+-type and the second conductivity type is p-type.

The method of claim [[17]] 16, wherein the step (c) comprises forming the first semiconductor region, the second semiconductor region, and the third semiconductor region in the SiC substrate by ion implantation.

The method of claim [[17]] 16, wherein the step (c) comprises epitaxially growing the first semiconductor region, the second semiconductor region, and the third semiconductor region on the SiC substrate.

The method of claim [[17]] 16, further comprising disposing a GaN layer on at least a portion of the SiC substrate, and forming the first semiconductor region, the second semiconductor region, and the third semiconductor region in the GaN layer.

canceled

The monolithically integrated semiconductor semiconductor region and the third semiconductor contact with the GaN semiconductor device via a combinations thereof.

The monolithically integrated semiconductor semiconductor region is in electrical contact with device, and the third semiconductor region is in terminal of the GaN semiconductor device.

(Cu rr ently Amended) A monolithically integrated semiconductor assembly, comprising: a substrate comprising silicon carbide (Si C); a gallium nitride (GaN) semiconductor device fabricated on the substrate, wherein the GaN semiconductor device comprises a high electron mobility transistor (HEMT), a junction gate field effect transistor (J FET), or a metal-oxide-semiconductor field-effect transistor (MOSFET); and in addition to the GaN semiconductor device, at least one transient voltage suppressor (TVS) structure fabricated in or on the substrate, comprising: a first semiconductor region having a first conductivity type; a second semiconductor region having a second conductivity type, and in electrical contact with the first semiconductor region; and a third semiconductor region having a first conductivity type, and in electrical contact with the second semiconductor region, an d- whe fe-in such that the TVS structure is configured to operate in a punch-through mode, an avalanehe mode, or combinations ther when an applied voltage across the GaN semiconductor device is greater than a threshold voltage.

canceled

The monolithically integrated semiconductor assembly of claim [[5]] 1, wherein the first conductivity type is n + -type and the second conductivity type is p-type.

The monolithically integrated semiconductor assembly of claim [[5]] 1, wherein the first semiconductor region, the second semiconductor region, and the third semiconductor region are formed in the SiC substrate.

The monolithically integrated semiconductor assembly of claim [[5]] 1, wherein the first semiconductor region, the second semiconductor region, and the third semiconductor region are epitaxially grown on the SiC substrate.

The monolithically integrated semiconductor assembly of claim [[5]] 1, wherein the TVS structure further comprises a GaN layer disposed on at least a portion of the SiC substrate, and wherein the first semiconductor region, the second semiconductor region, and the third semiconductor region are formed in the GaN layer.

canceled

A monolithically integrated semiconductor assembly, comprising: a substrate comprising silicon carbide (SiC); a gallium nitride (GaN) semiconductor device fabricated on the substrate, wherein the GaN semiconductor device comprises a high electron mobility transistor (HEMT); and in addition to the GaN semiconductor device, at least one transient voltage suppressor (TVS) structure comprising silicon carbide (Si C) fabricated in or on the substrate, comprising: a first semiconductor region having a first conductivity type; 3 of 11 Application No. 13/931,363 Reply to Office Action of a second semiconductor region having a second conductivity type, and in electrical contact with the first semiconductor region; and a third semiconductor region having a first conductivity type, and in electrical contact with the second semiconductor region; wherein the TVS structure is in electrical contact with the GaN semiconductor device, and whe fe-ia such that the TVS structure is configured to operate in a punch-through mode when an applied voltage across the GaN semiconductor device is greater than a threshold voltage.

A method of making a monolithically integrated semiconductor assembly comprising: (a) providing a substrate comprising silicon carbide (SiC); (b) fabricating a gallium nitride (GaN) semiconductor device on the substrate, wherein the GaN semiconductor device comprises a high electron mobility transistor (HEMT), a junction gate field effect transistor (J FET), or a metal-oxide-semiconductor field-effect transistor (MOSFET); (c) in addition to the GaN semiconductor device, fabricating at least one transient voltage suppressor (TVS) in or on the substrate, the at least one TVS comprising: a first semiconductor region having a first conductivity type; a second semiconductor region having a second conductivity type, and in electrical contact with the first semiconductor region; and a third semiconductor region having a first conductivity type, and in electrical contact with the second semiconductor region; and 4 of 11 Application No. 13/931,363 Reply to Office Action of (d) electrically coupling the TVS structure with the GaN semiconductor device, wherein the TVS structure is configured to operate in a punch-through mode, an avalache mode, or ombinations thereof, when an applied voltage across the GaN semiconductor device is greater than a threshold voltage. currently amended

canceled

The method of claim [[17]] 16, wherein the first conductivity type is n+-type and the second conductivity type is p-type.

The method of claim [[17]] 16, wherein the step (c) comprises forming the first semiconductor region, the second semiconductor region, and the third semiconductor region in the SiC substrate by ion implantation.

The method of claim [[17]] 16, wherein the step (c) comprises epitaxially growing the first semiconductor region, the second semiconductor region, and the third semiconductor region on the SiC substrate.

The method of claim [[17]] 16, further comprising disposing a GaN layer on at least a portion of the SiC substrate, and forming the first semiconductor region, the second semiconductor region, and the third semiconductor region in the GaN layer.

canceled

The monolithically integrated semiconductor semiconductor region and the third semiconductor contact with the GaN semiconductor device via a combinations thereof.

The monolithically integrated semiconductor semiconductor region is in electrical contact with device, and the third semiconductor region is in terminal of the GaN semiconductor device.

(Cu rr ently Amended) A monolithically integrated semiconductor assembly, comprising: a substrate comprising silicon carbide (Si C); a gallium nitride (GaN) semiconductor device fabricated on the substrate, wherein the GaN semiconductor device comprises a high electron mobility transistor (HEMT), a junction gate field effect transistor (J FET), or a metal-oxide-semiconductor field-effect transistor (MOSFET); and in addition to the GaN semiconductor device, at least one transient voltage suppressor (TVS) structure fabricated in or on the substrate, comprising: a first semiconductor region having a first conductivity type; a second semiconductor region having a second conductivity type, and in electrical contact with the first semiconductor region; and a third semiconductor region having a first conductivity type, and in electrical contact with the second semiconductor region, an d- whe fe-in such that the TVS structure is configured to operate in a punch-through mode, an avalanehe mode, or combinations ther when an applied voltage across the GaN semiconductor device is greater than a threshold voltage.

canceled

The monolithically integrated semiconductor assembly of claim [[5]] 1, wherein the first conductivity type is n + -type and the second conductivity type is p-type.

The monolithically integrated semiconductor assembly of claim [[5]] 1, wherein the first semiconductor region, the second semiconductor region, and the third semiconductor region are formed in the SiC substrate.

The monolithically integrated semiconductor assembly of claim [[5]] 1, wherein the first semiconductor region, the second semiconductor region, and the third semiconductor region are epitaxially grown on the SiC substrate.

The monolithically integrated semiconductor assembly of claim [[5]] 1, wherein the TVS structure further comprises a GaN layer disposed on at least a portion of the SiC substrate, and wherein the first semiconductor region, the second semiconductor region, and the third semiconductor region are formed in the GaN layer.

canceled

A monolithically integrated semiconductor assembly, comprising: a substrate comprising silicon carbide (SiC); a gallium nitride (GaN) semiconductor device fabricated on the substrate, wherein the GaN semiconductor device comprises a high electron mobility transistor (HEMT); and in addition to the GaN semiconductor device, at least one transient voltage suppressor (TVS) structure comprising silicon carbide (Si C) fabricated in or on the substrate, comprising: a first semiconductor region having a first conductivity type; 3 of 11 Application No. 13/931,363 Reply to Office Action of a second semiconductor region having a second conductivity type, and in electrical contact with the first semiconductor region; and a third semiconductor region having a first conductivity type, and in electrical contact with the second semiconductor region; wherein the TVS structure is in electrical contact with the GaN semiconductor device, and whe fe-ia such that the TVS structure is configured to operate in a punch-through mode when an applied voltage across the GaN semiconductor device is greater than a threshold voltage.

A method of making a monolithically integrated semiconductor assembly comprising: (a) providing a substrate comprising silicon carbide (SiC); (b) fabricating a gallium nitride (GaN) semiconductor device on the substrate, wherein the GaN semiconductor device comprises a high electron mobility transistor (HEMT), a junction gate field effect transistor (J FET), or a metal-oxide-semiconductor field-effect transistor (MOSFET); (c) in addition to the GaN semiconductor device, fabricating at least one transient voltage suppressor (TVS) in or on the substrate, the at least one TVS comprising: a first semiconductor region having a first conductivity type; a second semiconductor region having a second conductivity type, and in electrical contact with the first semiconductor region; and a third semiconductor region having a first conductivity type, and in electrical contact with the second semiconductor region; and 4 of 11 Application No. 13/931,363 Reply to Office Action of (d) electrically coupling the TVS structure with the GaN semiconductor device, wherein the TVS structure is configured to operate in a punch-through mode, an avalache mode, or ombinations thereof, when an applied voltage across the GaN semiconductor device is greater than a threshold voltage. currently amended

canceled

The method of claim [[17]] 16, wherein the first conductivity type is n+-type and the second conductivity type is p-type.

The method of claim [[17]] 16, wherein the step (c) comprises forming the first semiconductor region, the second semiconductor region, and the third semiconductor region in the SiC substrate by ion implantation.

The method of claim [[17]] 16, wherein the step (c) comprises epitaxially growing the first semiconductor region, the second semiconductor region, and the third semiconductor region on the SiC substrate.

The method of claim [[17]] 16, further comprising disposing a GaN layer on at least a portion of the SiC substrate, and forming the first semiconductor region, the second semiconductor region, and the third semiconductor region in the GaN layer.

canceled

The monolithically integrated semiconductor semiconductor region and the third semiconductor contact with the GaN semiconductor device via a combinations thereof.

The monolithically integrated semiconductor semiconductor region is in electrical contact with device, and the third semiconductor region is in terminal of the GaN semiconductor device.

(Cu rr ently Amended) A monolithically integrated semiconductor assembly, comprising: a substrate comprising silicon carbide (Si C); a gallium nitride (GaN) semiconductor device fabricated on the substrate, wherein the GaN semiconductor device comprises a high electron mobility transistor (HEMT), a junction gate field effect transistor (J FET), or a metal-oxide-semiconductor field-effect transistor (MOSFET); and in addition to the GaN semiconductor device, at least one transient voltage suppressor (TVS) structure fabricated in or on the substrate, comprising: a first semiconductor region having a first conductivity type; a second semiconductor region having a second conductivity type, and in electrical contact with the first semiconductor region; and a third semiconductor region having a first conductivity type, and in electrical contact with the second semiconductor region, an d- whe fe-in such that the TVS structure is configured to operate in a punch-through mode, an avalanehe mode, or combinations ther when an applied voltage across the GaN semiconductor device is greater than a threshold voltage.

canceled

The monolithically integrated semiconductor assembly of claim [[5]] 1, wherein the first conductivity type is n + -type and the second conductivity type is p-type.

The monolithically integrated semiconductor assembly of claim [[5]] 1, wherein the first semiconductor region, the second semiconductor region, and the third semiconductor region are formed in the SiC substrate.

The monolithically integrated semiconductor assembly of claim [[5]] 1, wherein the first semiconductor region, the second semiconductor region, and the third semiconductor region are epitaxially grown on the SiC substrate.

The monolithically integrated semiconductor assembly of claim [[5]] 1, wherein the TVS structure further comprises a GaN layer disposed on at least a portion of the SiC substrate, and wherein the first semiconductor region, the second semiconductor region, and the third semiconductor region are formed in the GaN layer.

canceled

A monolithically integrated semiconductor assembly, comprising: a substrate comprising silicon carbide (SiC); a gallium nitride (GaN) semiconductor device fabricated on the substrate, wherein the GaN semiconductor device comprises a high electron mobility transistor (HEMT); and in addition to the GaN semiconductor device, at least one transient voltage suppressor (TVS) structure comprising silicon carbide (Si C) fabricated in or on the substrate, comprising: a first semiconductor region having a first conductivity type; 3 of 11 Application No. 13/931,363 Reply to Office Action of a second semiconductor region having a second conductivity type, and in electrical contact with the first semiconductor region; and a third semiconductor region having a first conductivity type, and in electrical contact with the second semiconductor region; wherein the TVS structure is in electrical contact with the GaN semiconductor device, and whe fe-ia such that the TVS structure is configured to operate in a punch-through mode when an applied voltage across the GaN semiconductor device is greater than a threshold voltage.

A method of making a monolithically integrated semiconductor assembly comprising: (a) providing a substrate comprising silicon carbide (SiC); (b) fabricating a gallium nitride (GaN) semiconductor device on the substrate, wherein the GaN semiconductor device comprises a high electron mobility transistor (HEMT), a junction gate field effect transistor (J FET), or a metal-oxide-semiconductor field-effect transistor (MOSFET); (c) in addition to the GaN semiconductor device, fabricating at least one transient voltage suppressor (TVS) in or on the substrate, the at least one TVS comprising: a first semiconductor region having a first conductivity type; a second semiconductor region having a second conductivity type, and in electrical contact with the first semiconductor region; and a third semiconductor region having a first conductivity type, and in electrical contact with the second semiconductor region; and 4 of 11 Application No. 13/931,363 Reply to Office Action of (d) electrically coupling the TVS structure with the GaN semiconductor device, wherein the TVS structure is configured to operate in a punch-through mode, an avalache mode, or ombinations thereof, when an applied voltage across the GaN semiconductor device is greater than a threshold voltage. currently amended

canceled

The method of claim [[17]] 16, wherein the first conductivity type is n+-type and the second conductivity type is p-type.

The method of claim [[17]] 16, wherein the step (c) comprises forming the first semiconductor region, the second semiconductor region, and the third semiconductor region in the SiC substrate by ion implantation.

The method of claim [[17]] 16, wherein the step (c) comprises epitaxially growing the first semiconductor region, the second semiconductor region, and the third semiconductor region on the SiC substrate.

The method of claim [[17]] 16, further comprising disposing a GaN layer on at least a portion of the SiC substrate, and forming the first semiconductor region, the second semiconductor region, and the third semiconductor region in the GaN layer.

canceled

The monolithically integrated semiconductor semiconductor region and the third semiconductor contact with the GaN semiconductor device via a combinations thereof.

The monolithically integrated semiconductor semiconductor region is in electrical contact with device, and the third semiconductor region is in terminal of the GaN semiconductor device.