A silicon-on-insulator structure having an integrated graphene layer, comprising: a silicon material comprising a buried oxide layer within the silicon material, a silicon substrate on a first side of the buried oxide layer, and a silicon-on-insulator layer on a second side of the buried oxide layer; first and second laterally spaced apart alignment recesses in the silicon-on-insulator layer, wherein the first and second recesses extend through the silicon-on-insulator layer and into the buried oxide layer; a graphene layer positioned directly on the silicon-on-insulator layer in contact therewith and on a side thereof opposite to the buried oxide layer, the graphene layer being in metal-less contact with the silicon-on-insulator layer and being laterally between and spaced from the first and second recesses; source and drain regions in the silicon-on-insulator layer in the spaces between the graphene layer and the first and second recesses; a gate above the graphene layer; and a gate insulator positioned directly on the graphene layer, between the graphene layer and the gate; and wherein the graphene layer is above the bonded oxide layer and is directly above and in direct contact with the silicon-on-insulator layer, and opposite lateral ends of the graphene layer 2 I: \GF- I BM\2683\243 11 A\AMEND\2431 1A. AM6.docx are in direct contact with, respectively, the source and drain regions and laterally inside of the first and second recesses; and wherein the silicon material further comprises a backgate layer comprised of a doping ion in the silicon substrate directly beneath and contiguous with a portion of the buried oxide layer.

A silicon-on-insulator structure having an integrated graphene layer, comprising: a silicon material comprising a buried oxide layer fo rm ed within the silicon material, a silicon substrate on a bottom side of the buried oxide layer, a silicon-on-insulator layer on a top side of the buried oxide layer, and a backgate layer comprised of a doping ion species in the silicon substrate; first and second laterally spaced apart recesses in the silicon-on-insulator layer, wherein the first and second recesses extend through the silicon-on-insulator layer and into the buried oxide layer; a graphene layer positioned directly on a top side of the silicon-on-insulator layer in contact therewith, the graphene layer being in metal-less contact with the silicon-on-insulator layer and being laterally between and spaced from the first and second recesses; source and drain regions in the silicon-on-insulator layer in the spaces between the graphene layer and the first and second recesses and extending beneath the graphene layer; a gate above the graphene layer; and 3 I: \GF-I BM\2683\243 11 A\AMEND\2431 1A. AM6.docx a gate insulator directly on the graphene layer, between said graphene layer and said gate; and wherein the graphene layer is above the bonded oxide layer and is directly above and in direct contact with the silicon-on-insulator layer, and opposite lateral ends of the graphene layer are in direct contact with, respectively, the source and drain regions and laterally inside of the first and second recesses.

canceled

A silicon-on-insulator structure having an integrated graphene layer, comprising: a silicon material comprising a buried oxide layer within the silicon material, a silicon substrate on a first side of the buried oxide layer, and a silicon-on-insulator layer on a second side of the buried oxide layer; first and second laterally spaced apart alignment recesses in the silicon-on-insulator layer, wherein the first and second recesses extend through the silicon-on-insulator layer and into the buried oxide layer; a graphene layer positioned directly on the silicon-on-insulator layer in contact therewith and on a side thereof opposite to the buried oxide layer, the graphene layer being in metal-less contact with the silicon-on-insulator layer and being laterally between and spaced from the first and second recesses; source and drain regions in the silicon-on-insulator layer in the spaces between the graphene layer and the first and second recesses; a gate above the graphene layer; and a gate insulator positioned directly on the graphene layer, between the graphene layer and the gate; and wherein the graphene layer is above the bonded oxide layer and is directly above and in direct contact with the silicon-on-insulator layer, and opposite lateral ends of the graphene layer 2 I: \GF- I BM\2683\243 11 A\AMEND\2431 1A. AM6.docx are in direct contact with, respectively, the source and drain regions and laterally inside of the first and second recesses; and wherein the silicon material further comprises a backgate layer comprised of a doping ion in the silicon substrate directly beneath and contiguous with a portion of the buried oxide layer.

A silicon-on-insulator structure having an integrated graphene layer, comprising: a silicon material comprising a buried oxide layer fo rm ed within the silicon material, a silicon substrate on a bottom side of the buried oxide layer, a silicon-on-insulator layer on a top side of the buried oxide layer, and a backgate layer comprised of a doping ion species in the silicon substrate; first and second laterally spaced apart recesses in the silicon-on-insulator layer, wherein the first and second recesses extend through the silicon-on-insulator layer and into the buried oxide layer; a graphene layer positioned directly on a top side of the silicon-on-insulator layer in contact therewith, the graphene layer being in metal-less contact with the silicon-on-insulator layer and being laterally between and spaced from the first and second recesses; source and drain regions in the silicon-on-insulator layer in the spaces between the graphene layer and the first and second recesses and extending beneath the graphene layer; a gate above the graphene layer; and 3 I: \GF-I BM\2683\243 11 A\AMEND\2431 1A. AM6.docx a gate insulator directly on the graphene layer, between said graphene layer and said gate; and wherein the graphene layer is above the bonded oxide layer and is directly above and in direct contact with the silicon-on-insulator layer, and opposite lateral ends of the graphene layer are in direct contact with, respectively, the source and drain regions and laterally inside of the first and second recesses.

canceled

A silicon-on-insulator structure having an integrated graphene layer, comprising: a silicon material comprising a buried oxide layer within the silicon material, a silicon substrate on a first side of the buried oxide layer, and a silicon-on-insulator layer on a second side of the buried oxide layer; first and second laterally spaced apart alignment recesses in the silicon-on-insulator layer, wherein the first and second recesses extend through the silicon-on-insulator layer and into the buried oxide layer; a graphene layer positioned directly on the silicon-on-insulator layer in contact therewith and on a side thereof opposite to the buried oxide layer, the graphene layer being in metal-less contact with the silicon-on-insulator layer and being laterally between and spaced from the first and second recesses; source and drain regions in the silicon-on-insulator layer in the spaces between the graphene layer and the first and second recesses; a gate above the graphene layer; and a gate insulator positioned directly on the graphene layer, between the graphene layer and the gate; and wherein the graphene layer is above the bonded oxide layer and is directly above and in direct contact with the silicon-on-insulator layer, and opposite lateral ends of the graphene layer 2 I: \GF- I BM\2683\243 11 A\AMEND\2431 1A. AM6.docx are in direct contact with, respectively, the source and drain regions and laterally inside of the first and second recesses; and wherein the silicon material further comprises a backgate layer comprised of a doping ion in the silicon substrate directly beneath and contiguous with a portion of the buried oxide layer.

A silicon-on-insulator structure having an integrated graphene layer, comprising: a silicon material comprising a buried oxide layer fo rm ed within the silicon material, a silicon substrate on a bottom side of the buried oxide layer, a silicon-on-insulator layer on a top side of the buried oxide layer, and a backgate layer comprised of a doping ion species in the silicon substrate; first and second laterally spaced apart recesses in the silicon-on-insulator layer, wherein the first and second recesses extend through the silicon-on-insulator layer and into the buried oxide layer; a graphene layer positioned directly on a top side of the silicon-on-insulator layer in contact therewith, the graphene layer being in metal-less contact with the silicon-on-insulator layer and being laterally between and spaced from the first and second recesses; source and drain regions in the silicon-on-insulator layer in the spaces between the graphene layer and the first and second recesses and extending beneath the graphene layer; a gate above the graphene layer; and 3 I: \GF-I BM\2683\243 11 A\AMEND\2431 1A. AM6.docx a gate insulator directly on the graphene layer, between said graphene layer and said gate; and wherein the graphene layer is above the bonded oxide layer and is directly above and in direct contact with the silicon-on-insulator layer, and opposite lateral ends of the graphene layer are in direct contact with, respectively, the source and drain regions and laterally inside of the first and second recesses.

canceled

A silicon-on-insulator structure having an integrated graphene layer, comprising: a silicon material comprising a buried oxide layer within the silicon material, a silicon substrate on a first side of the buried oxide layer, and a silicon-on-insulator layer on a second side of the buried oxide layer; first and second laterally spaced apart alignment recesses in the silicon-on-insulator layer, wherein the first and second recesses extend through the silicon-on-insulator layer and into the buried oxide layer; a graphene layer positioned directly on the silicon-on-insulator layer in contact therewith and on a side thereof opposite to the buried oxide layer, the graphene layer being in metal-less contact with the silicon-on-insulator layer and being laterally between and spaced from the first and second recesses; source and drain regions in the silicon-on-insulator layer in the spaces between the graphene layer and the first and second recesses; a gate above the graphene layer; and a gate insulator positioned directly on the graphene layer, between the graphene layer and the gate; and wherein the graphene layer is above the bonded oxide layer and is directly above and in direct contact with the silicon-on-insulator layer, and opposite lateral ends of the graphene layer 2 I: \GF- I BM\2683\243 11 A\AMEND\2431 1A. AM6.docx are in direct contact with, respectively, the source and drain regions and laterally inside of the first and second recesses; and wherein the silicon material further comprises a backgate layer comprised of a doping ion in the silicon substrate directly beneath and contiguous with a portion of the buried oxide layer.

A silicon-on-insulator structure having an integrated graphene layer, comprising: a silicon material comprising a buried oxide layer fo rm ed within the silicon material, a silicon substrate on a bottom side of the buried oxide layer, a silicon-on-insulator layer on a top side of the buried oxide layer, and a backgate layer comprised of a doping ion species in the silicon substrate; first and second laterally spaced apart recesses in the silicon-on-insulator layer, wherein the first and second recesses extend through the silicon-on-insulator layer and into the buried oxide layer; a graphene layer positioned directly on a top side of the silicon-on-insulator layer in contact therewith, the graphene layer being in metal-less contact with the silicon-on-insulator layer and being laterally between and spaced from the first and second recesses; source and drain regions in the silicon-on-insulator layer in the spaces between the graphene layer and the first and second recesses and extending beneath the graphene layer; a gate above the graphene layer; and 3 I: \GF-I BM\2683\243 11 A\AMEND\2431 1A. AM6.docx a gate insulator directly on the graphene layer, between said graphene layer and said gate; and wherein the graphene layer is above the bonded oxide layer and is directly above and in direct contact with the silicon-on-insulator layer, and opposite lateral ends of the graphene layer are in direct contact with, respectively, the source and drain regions and laterally inside of the first and second recesses.

canceled