Patent
US 8,927,415Graphene Barrier Layers for Interconnects and Methods for Forming the Same
Sandip Niyogi, Chi-I Lang
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 8,927,415Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 illustrates a schematic diagram for implementing combinatorial processing and evaluation using primary, secondary, and tertiary screening.
Figure 2 is a simplified schematic diagram illustrating a general methodology for combinatorial process sequence integration that includes site isolated processing and/or conventional processing according to some embodiments. 10
Figure 3 is a simplified schematic diagram illustrating an integrated high productivity combinatorial (HP C) system according to some embodiments.
Figure 4 is a simplified schematic diagram illustrating a sputter processing chamber configured to perform combinatorial processing and full substrate processing according to some embodiments. 15
Figure 5 is a cross-sectional view of a dielectric body according to some embodiments.
Figure 6 is a cross-sectional view of the dielectric body of
Figure 7 is a cross-sectional view of the dielectric body of
Figure 8 is a cross-sectional view of the dielectric body of
Figure 9 is a cross-sectional view of the dielectric body of
Figure 10 is a cross-sectional view of the dielectric body of
Figure 11 is a cross-sectional view of the dielectric body of
Figure 12 is a cross-sectional view of a microelectronic assembly according to some 30 embodiments.
Figure 13 is a flow chart illustrating a method for forming an interconnect barrier according to some embodiments.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method comprising: providing a dielectric body having a trench formed in a surface thereof; forming a first layer above the dielectric body within the trench, wherein the first layer comprises amorphous carbon and completely fills at least a portion of the trench; forming a second layer above the first layer, wherein the second layer comprises a metal, and all of the second layer is positioned external to the at least a portion of the trench; and heating the dielectric body, the first layer, and the second layer to convert at least some of the amorphous carbon to graphene, wherein at least some of the graphene is positioned within the at least a portion of the trench, wherein the at least a portion of the trench comprises is a second portion having a second width, the trench further comprisin g a first portion having a first width, wherein the second width is less than the first width, the first portion of the trench is positioned between the second portion of the trench and the surface of the dielectric body, the first layer completely fills the second portion of the trench before the heating of the dielectric body, the first layer, and the second layer, and after the heating of the dielectric body, the first layer, and the second layer, the second portion of the trench is at least partially opened.
The method of claim 1, wherein a ratio of sp2 bonds to sp 3 bonds in the amorphous carbon is not more than about 2:1.
The method of claim 1, wherein the dielectric body is a dielectric layer formed above a substrate.
canceled
The method of claim [[4]] 1 wherein the heating is performed at a temperature of between about 120  °C and about 45 0° C.
The method of claim 5, wherein the second layer comprises at least one of copper, titanium, gold, or a combination thereof.
The method of claim [[4]] 1 wherein the graphene forms a graphene layer, and the graphene layer conforms to the shape of the second portion of the trench.
(Allowed) A method for forming a microelectronic assembly, the method comprising: providing a substrate having a microelectronic device, the substrate further comprising a dielectric layer formed above the microelectronic device, wherein the dielectric layer has a trench formed in a surface thereof, wherein the trench comprises 3 an upper portion having a first width and a lower portion having a second width, wherein the second width is less than the first width; forming a first layer above the dielectric layer within the trench, wherein the first layer comprises amorphous carbon and completely fills the lower portion of the trench; forming a second layer above the first layer, wherein the second layer comprises a metal, and all of the second layer is positioned external to the lower portion of the trench; heating the dielectric layer, the first layer, and the second layer to a temperature of between about 120  °C and about 90 0 °C to convert at least some of the amorphous carbon to graphene, wherein at least some of the graphene is positioned within the lower portion of the trench, and after the heating of the dielectric body, the first layer, and the second layer, the lower portion of the trench is at least partially opened; and forming a conductive body within the trench, wherein the conductive body is electrically connected to the microelectronic device, and a portion of the conductive body is positioned within the lower portion of the trench.
(Allowed) The method of claim 11, wherein the dielectric layer, the first layer, and the second layer are heated to a temperature of between about 120  °C and about 45 0° C.
(Allowed) A method for forming a microelectronic assembly, the method comprising: providing a substrate having a transistor, the substrate further comprising a dielectric layer formed above the transistor, wherein the dielectric layer has a trench formed in a surface thereof, wherein the trench comprises an upper portion having a first width and a lower portion having a second width, wherein the second width is less than the first width; forming a first layer above the dielectric layer within the trench, wherein the first layer comprises amorphous carbon and completely fills the lower portion of the trench; forming a second layer above the first layer, wherein the second layer comprises copper, nickel, cobalt, titanium, or a combination thereof, and all of the second layer is positioned external to the lower portion of the trench; heating the dielectric layer, the first layer, and the second layer to a temperature of between about 120  °C and about 45 0 °C to convert at least some of the amorphous carbon to graphene, wherein at least some of the graphene is positioned within the lower portion of the trench, and after the heating of the dielectric body, the first layer, and the second layer, the lower portion of the trench is at least partially opened; and forming a conductive body within the trench, wherein the conductive body is electrically connected to the transistor, and a portion of the conductive body is positioned within the lower portion of the trench.
(Allowed) The method of claim 16, wherein a ratio of sp2 bonds to sp 3 bonds in the amorphous carbon is not more than about 2:1.
Layer stacks claimed or described, ordered top of device to substrate.
microelectronic interconnect with graphene barrier
Materials described outside the worked examples.
amorphous carbon
metal (seed layer)
graphene
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1–10 nm | — |
Thickness | 0.5–1 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,927,415Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 illustrates a schematic diagram for implementing combinatorial processing and evaluation using primary, secondary, and tertiary screening.
Figure 2 is a simplified schematic diagram illustrating a general methodology for combinatorial process sequence integration that includes site isolated processing and/or conventional processing according to some embodiments. 10
Figure 3 is a simplified schematic diagram illustrating an integrated high productivity combinatorial (HP C) system according to some embodiments.
Figure 4 is a simplified schematic diagram illustrating a sputter processing chamber configured to perform combinatorial processing and full substrate processing according to some embodiments. 15
Figure 5 is a cross-sectional view of a dielectric body according to some embodiments.
Figure 6 is a cross-sectional view of the dielectric body of
Figure 7 is a cross-sectional view of the dielectric body of
Figure 8 is a cross-sectional view of the dielectric body of
Figure 9 is a cross-sectional view of the dielectric body of
Figure 10 is a cross-sectional view of the dielectric body of
Figure 11 is a cross-sectional view of the dielectric body of
Figure 12 is a cross-sectional view of a microelectronic assembly according to some 30 embodiments.
Figure 13 is a flow chart illustrating a method for forming an interconnect barrier according to some embodiments.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method comprising: providing a dielectric body having a trench formed in a surface thereof; forming a first layer above the dielectric body within the trench, wherein the first layer comprises amorphous carbon and completely fills at least a portion of the trench; forming a second layer above the first layer, wherein the second layer comprises a metal, and all of the second layer is positioned external to the at least a portion of the trench; and heating the dielectric body, the first layer, and the second layer to convert at least some of the amorphous carbon to graphene, wherein at least some of the graphene is positioned within the at least a portion of the trench, wherein the at least a portion of the trench comprises is a second portion having a second width, the trench further comprisin g a first portion having a first width, wherein the second width is less than the first width, the first portion of the trench is positioned between the second portion of the trench and the surface of the dielectric body, the first layer completely fills the second portion of the trench before the heating of the dielectric body, the first layer, and the second layer, and after the heating of the dielectric body, the first layer, and the second layer, the second portion of the trench is at least partially opened.
The method of claim 1, wherein a ratio of sp2 bonds to sp 3 bonds in the amorphous carbon is not more than about 2:1.
The method of claim 1, wherein the dielectric body is a dielectric layer formed above a substrate.
canceled
The method of claim [[4]] 1 wherein the heating is performed at a temperature of between about 120  °C and about 45 0° C.
The method of claim 5, wherein the second layer comprises at least one of copper, titanium, gold, or a combination thereof.
The method of claim [[4]] 1 wherein the graphene forms a graphene layer, and the graphene layer conforms to the shape of the second portion of the trench.
(Allowed) A method for forming a microelectronic assembly, the method comprising: providing a substrate having a microelectronic device, the substrate further comprising a dielectric layer formed above the microelectronic device, wherein the dielectric layer has a trench formed in a surface thereof, wherein the trench comprises 3 an upper portion having a first width and a lower portion having a second width, wherein the second width is less than the first width; forming a first layer above the dielectric layer within the trench, wherein the first layer comprises amorphous carbon and completely fills the lower portion of the trench; forming a second layer above the first layer, wherein the second layer comprises a metal, and all of the second layer is positioned external to the lower portion of the trench; heating the dielectric layer, the first layer, and the second layer to a temperature of between about 120  °C and about 90 0 °C to convert at least some of the amorphous carbon to graphene, wherein at least some of the graphene is positioned within the lower portion of the trench, and after the heating of the dielectric body, the first layer, and the second layer, the lower portion of the trench is at least partially opened; and forming a conductive body within the trench, wherein the conductive body is electrically connected to the microelectronic device, and a portion of the conductive body is positioned within the lower portion of the trench.
(Allowed) The method of claim 11, wherein the dielectric layer, the first layer, and the second layer are heated to a temperature of between about 120  °C and about 45 0° C.
(Allowed) A method for forming a microelectronic assembly, the method comprising: providing a substrate having a transistor, the substrate further comprising a dielectric layer formed above the transistor, wherein the dielectric layer has a trench formed in a surface thereof, wherein the trench comprises an upper portion having a first width and a lower portion having a second width, wherein the second width is less than the first width; forming a first layer above the dielectric layer within the trench, wherein the first layer comprises amorphous carbon and completely fills the lower portion of the trench; forming a second layer above the first layer, wherein the second layer comprises copper, nickel, cobalt, titanium, or a combination thereof, and all of the second layer is positioned external to the lower portion of the trench; heating the dielectric layer, the first layer, and the second layer to a temperature of between about 120  °C and about 45 0 °C to convert at least some of the amorphous carbon to graphene, wherein at least some of the graphene is positioned within the lower portion of the trench, and after the heating of the dielectric body, the first layer, and the second layer, the lower portion of the trench is at least partially opened; and forming a conductive body within the trench, wherein the conductive body is electrically connected to the transistor, and a portion of the conductive body is positioned within the lower portion of the trench.
(Allowed) The method of claim 16, wherein a ratio of sp2 bonds to sp 3 bonds in the amorphous carbon is not more than about 2:1.
Layer stacks claimed or described, ordered top of device to substrate.
microelectronic interconnect with graphene barrier
Materials described outside the worked examples.
amorphous carbon
metal (seed layer)
graphene
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1–10 nm | — |
Thickness | 0.5–1 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,927,415Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 illustrates a schematic diagram for implementing combinatorial processing and evaluation using primary, secondary, and tertiary screening.
Figure 2 is a simplified schematic diagram illustrating a general methodology for combinatorial process sequence integration that includes site isolated processing and/or conventional processing according to some embodiments. 10
Figure 3 is a simplified schematic diagram illustrating an integrated high productivity combinatorial (HP C) system according to some embodiments.
Figure 4 is a simplified schematic diagram illustrating a sputter processing chamber configured to perform combinatorial processing and full substrate processing according to some embodiments. 15
Figure 5 is a cross-sectional view of a dielectric body according to some embodiments.
Figure 6 is a cross-sectional view of the dielectric body of
Figure 7 is a cross-sectional view of the dielectric body of
Figure 8 is a cross-sectional view of the dielectric body of
Figure 9 is a cross-sectional view of the dielectric body of
Figure 10 is a cross-sectional view of the dielectric body of
Figure 11 is a cross-sectional view of the dielectric body of
Figure 12 is a cross-sectional view of a microelectronic assembly according to some 30 embodiments.
Figure 13 is a flow chart illustrating a method for forming an interconnect barrier according to some embodiments.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method comprising: providing a dielectric body having a trench formed in a surface thereof; forming a first layer above the dielectric body within the trench, wherein the first layer comprises amorphous carbon and completely fills at least a portion of the trench; forming a second layer above the first layer, wherein the second layer comprises a metal, and all of the second layer is positioned external to the at least a portion of the trench; and heating the dielectric body, the first layer, and the second layer to convert at least some of the amorphous carbon to graphene, wherein at least some of the graphene is positioned within the at least a portion of the trench, wherein the at least a portion of the trench comprises is a second portion having a second width, the trench further comprisin g a first portion having a first width, wherein the second width is less than the first width, the first portion of the trench is positioned between the second portion of the trench and the surface of the dielectric body, the first layer completely fills the second portion of the trench before the heating of the dielectric body, the first layer, and the second layer, and after the heating of the dielectric body, the first layer, and the second layer, the second portion of the trench is at least partially opened.
The method of claim 1, wherein a ratio of sp2 bonds to sp 3 bonds in the amorphous carbon is not more than about 2:1.
The method of claim 1, wherein the dielectric body is a dielectric layer formed above a substrate.
canceled
The method of claim [[4]] 1 wherein the heating is performed at a temperature of between about 120  °C and about 45 0° C.
The method of claim 5, wherein the second layer comprises at least one of copper, titanium, gold, or a combination thereof.
The method of claim [[4]] 1 wherein the graphene forms a graphene layer, and the graphene layer conforms to the shape of the second portion of the trench.
(Allowed) A method for forming a microelectronic assembly, the method comprising: providing a substrate having a microelectronic device, the substrate further comprising a dielectric layer formed above the microelectronic device, wherein the dielectric layer has a trench formed in a surface thereof, wherein the trench comprises 3 an upper portion having a first width and a lower portion having a second width, wherein the second width is less than the first width; forming a first layer above the dielectric layer within the trench, wherein the first layer comprises amorphous carbon and completely fills the lower portion of the trench; forming a second layer above the first layer, wherein the second layer comprises a metal, and all of the second layer is positioned external to the lower portion of the trench; heating the dielectric layer, the first layer, and the second layer to a temperature of between about 120  °C and about 90 0 °C to convert at least some of the amorphous carbon to graphene, wherein at least some of the graphene is positioned within the lower portion of the trench, and after the heating of the dielectric body, the first layer, and the second layer, the lower portion of the trench is at least partially opened; and forming a conductive body within the trench, wherein the conductive body is electrically connected to the microelectronic device, and a portion of the conductive body is positioned within the lower portion of the trench.
(Allowed) The method of claim 11, wherein the dielectric layer, the first layer, and the second layer are heated to a temperature of between about 120  °C and about 45 0° C.
(Allowed) A method for forming a microelectronic assembly, the method comprising: providing a substrate having a transistor, the substrate further comprising a dielectric layer formed above the transistor, wherein the dielectric layer has a trench formed in a surface thereof, wherein the trench comprises an upper portion having a first width and a lower portion having a second width, wherein the second width is less than the first width; forming a first layer above the dielectric layer within the trench, wherein the first layer comprises amorphous carbon and completely fills the lower portion of the trench; forming a second layer above the first layer, wherein the second layer comprises copper, nickel, cobalt, titanium, or a combination thereof, and all of the second layer is positioned external to the lower portion of the trench; heating the dielectric layer, the first layer, and the second layer to a temperature of between about 120  °C and about 45 0 °C to convert at least some of the amorphous carbon to graphene, wherein at least some of the graphene is positioned within the lower portion of the trench, and after the heating of the dielectric body, the first layer, and the second layer, the lower portion of the trench is at least partially opened; and forming a conductive body within the trench, wherein the conductive body is electrically connected to the transistor, and a portion of the conductive body is positioned within the lower portion of the trench.
(Allowed) The method of claim 16, wherein a ratio of sp2 bonds to sp 3 bonds in the amorphous carbon is not more than about 2:1.
Layer stacks claimed or described, ordered top of device to substrate.
microelectronic interconnect with graphene barrier
Materials described outside the worked examples.
amorphous carbon
metal (seed layer)
graphene
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1–10 nm | — |
Thickness | 0.5–1 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,927,415Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 illustrates a schematic diagram for implementing combinatorial processing and evaluation using primary, secondary, and tertiary screening.
Figure 2 is a simplified schematic diagram illustrating a general methodology for combinatorial process sequence integration that includes site isolated processing and/or conventional processing according to some embodiments. 10
Figure 3 is a simplified schematic diagram illustrating an integrated high productivity combinatorial (HP C) system according to some embodiments.
Figure 4 is a simplified schematic diagram illustrating a sputter processing chamber configured to perform combinatorial processing and full substrate processing according to some embodiments. 15
Figure 5 is a cross-sectional view of a dielectric body according to some embodiments.
Figure 6 is a cross-sectional view of the dielectric body of
Figure 7 is a cross-sectional view of the dielectric body of
Figure 8 is a cross-sectional view of the dielectric body of
Figure 9 is a cross-sectional view of the dielectric body of
Figure 10 is a cross-sectional view of the dielectric body of
Figure 11 is a cross-sectional view of the dielectric body of
Figure 12 is a cross-sectional view of a microelectronic assembly according to some 30 embodiments.
Figure 13 is a flow chart illustrating a method for forming an interconnect barrier according to some embodiments.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method comprising: providing a dielectric body having a trench formed in a surface thereof; forming a first layer above the dielectric body within the trench, wherein the first layer comprises amorphous carbon and completely fills at least a portion of the trench; forming a second layer above the first layer, wherein the second layer comprises a metal, and all of the second layer is positioned external to the at least a portion of the trench; and heating the dielectric body, the first layer, and the second layer to convert at least some of the amorphous carbon to graphene, wherein at least some of the graphene is positioned within the at least a portion of the trench, wherein the at least a portion of the trench comprises is a second portion having a second width, the trench further comprisin g a first portion having a first width, wherein the second width is less than the first width, the first portion of the trench is positioned between the second portion of the trench and the surface of the dielectric body, the first layer completely fills the second portion of the trench before the heating of the dielectric body, the first layer, and the second layer, and after the heating of the dielectric body, the first layer, and the second layer, the second portion of the trench is at least partially opened.
The method of claim 1, wherein a ratio of sp2 bonds to sp 3 bonds in the amorphous carbon is not more than about 2:1.
The method of claim 1, wherein the dielectric body is a dielectric layer formed above a substrate.
canceled
The method of claim [[4]] 1 wherein the heating is performed at a temperature of between about 120  °C and about 45 0° C.
The method of claim 5, wherein the second layer comprises at least one of copper, titanium, gold, or a combination thereof.
The method of claim [[4]] 1 wherein the graphene forms a graphene layer, and the graphene layer conforms to the shape of the second portion of the trench.
(Allowed) A method for forming a microelectronic assembly, the method comprising: providing a substrate having a microelectronic device, the substrate further comprising a dielectric layer formed above the microelectronic device, wherein the dielectric layer has a trench formed in a surface thereof, wherein the trench comprises 3 an upper portion having a first width and a lower portion having a second width, wherein the second width is less than the first width; forming a first layer above the dielectric layer within the trench, wherein the first layer comprises amorphous carbon and completely fills the lower portion of the trench; forming a second layer above the first layer, wherein the second layer comprises a metal, and all of the second layer is positioned external to the lower portion of the trench; heating the dielectric layer, the first layer, and the second layer to a temperature of between about 120  °C and about 90 0 °C to convert at least some of the amorphous carbon to graphene, wherein at least some of the graphene is positioned within the lower portion of the trench, and after the heating of the dielectric body, the first layer, and the second layer, the lower portion of the trench is at least partially opened; and forming a conductive body within the trench, wherein the conductive body is electrically connected to the microelectronic device, and a portion of the conductive body is positioned within the lower portion of the trench.
(Allowed) The method of claim 11, wherein the dielectric layer, the first layer, and the second layer are heated to a temperature of between about 120  °C and about 45 0° C.
(Allowed) A method for forming a microelectronic assembly, the method comprising: providing a substrate having a transistor, the substrate further comprising a dielectric layer formed above the transistor, wherein the dielectric layer has a trench formed in a surface thereof, wherein the trench comprises an upper portion having a first width and a lower portion having a second width, wherein the second width is less than the first width; forming a first layer above the dielectric layer within the trench, wherein the first layer comprises amorphous carbon and completely fills the lower portion of the trench; forming a second layer above the first layer, wherein the second layer comprises copper, nickel, cobalt, titanium, or a combination thereof, and all of the second layer is positioned external to the lower portion of the trench; heating the dielectric layer, the first layer, and the second layer to a temperature of between about 120  °C and about 45 0 °C to convert at least some of the amorphous carbon to graphene, wherein at least some of the graphene is positioned within the lower portion of the trench, and after the heating of the dielectric body, the first layer, and the second layer, the lower portion of the trench is at least partially opened; and forming a conductive body within the trench, wherein the conductive body is electrically connected to the transistor, and a portion of the conductive body is positioned within the lower portion of the trench.
(Allowed) The method of claim 16, wherein a ratio of sp2 bonds to sp 3 bonds in the amorphous carbon is not more than about 2:1.
Layer stacks claimed or described, ordered top of device to substrate.
microelectronic interconnect with graphene barrier
Materials described outside the worked examples.
amorphous carbon
metal (seed layer)
graphene
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1–10 nm | — |
Thickness | 0.5–1 nm |
Related documents with shared materials, methods, properties, or citations.
microelectronic assembly with transistor and graphene barrier interconnect
hydrogen
H₂
copper
Cu
titanium
Ti
gold
Au
nickel
Ni
cobalt
Co
silicon oxide
SiO₂
silicon nitride
Si₃N₄
low-k dielectric material
tantalum nitride
TaN
| — |
Temperature | 120–1200 °C | — |
Temperature | 120–900 °C | — |
Temperature | 120–450 °C | — |
Duration | 1–60 minutes | — |
Thickness | 0.1–0.4 nm | — |
Temperature | 20–25 °C | — |
Temperature | ≤ 900 °C | — |
Temperature | ≥ 900 °C | — |
microelectronic assembly with transistor and graphene barrier interconnect
hydrogen
H₂
copper
Cu
titanium
Ti
gold
Au
nickel
Ni
cobalt
Co
silicon oxide
SiO₂
silicon nitride
Si₃N₄
low-k dielectric material
tantalum nitride
TaN
| — |
Temperature | 120–1200 °C | — |
Temperature | 120–900 °C | — |
Temperature | 120–450 °C | — |
Duration | 1–60 minutes | — |
Thickness | 0.1–0.4 nm | — |
Temperature | 20–25 °C | — |
Temperature | ≤ 900 °C | — |
Temperature | ≥ 900 °C | — |
microelectronic assembly with transistor and graphene barrier interconnect
hydrogen
H₂
copper
Cu
titanium
Ti
gold
Au
nickel
Ni
cobalt
Co
silicon oxide
SiO₂
silicon nitride
Si₃N₄
low-k dielectric material
tantalum nitride
TaN
| — |
Temperature | 120–1200 °C | — |
Temperature | 120–900 °C | — |
Temperature | 120–450 °C | — |
Duration | 1–60 minutes | — |
Thickness | 0.1–0.4 nm | — |
Temperature | 20–25 °C | — |
Temperature | ≤ 900 °C | — |
Temperature | ≥ 900 °C | — |
microelectronic assembly with transistor and graphene barrier interconnect
hydrogen
H₂
copper
Cu
titanium
Ti
gold
Au
nickel
Ni
cobalt
Co
silicon oxide
SiO₂
silicon nitride
Si₃N₄
low-k dielectric material
tantalum nitride
TaN
| — |
Temperature | 120–1200 °C | — |
Temperature | 120–900 °C | — |
Temperature | 120–450 °C | — |
Duration | 1–60 minutes | — |
Thickness | 0.1–0.4 nm | — |
Temperature | 20–25 °C | — |
Temperature | ≤ 900 °C | — |
Temperature | ≥ 900 °C | — |