Patent
US 10,014,291SiC Crystalline on Si Substrates to Allow Integration of GaN and Si Electronics
Kong-Beng THEI
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 10,014,291Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A silicon substrate with a GaN-based device and a Si-based device on the silicon substrate, comprising: the GaN-based device on a SiC crystalline region, wherein the SiC crystalline region is over a portion of the silicon substrate, [[and]] a bottom-most surface of the GaN-based device is above a top-most surface of the silicon substrate, and the SiC crystalline region is spaced from each isolation structures in the silicon substrate; and the Si-based device in direct contact with a silicon region of the silicon substrate, wherein the silicon region directly contacts a portion of a sidewall of the SiC crystalline region adjacent a top surface of the silicon substrate, and the silicon region is adjacent to the SiC crystalline region on the silicon substrate. Currently amended
The silicon substrate of claim 1, wherein a surface of the SiC crystalline region is at about the same level as a surface of the silicon region. Previously presented
(Withdrawn- Previously Presented) The silicon substrate of claim 1, wherein the GaN- based device is selected from the group consisting of light-emitting device, power switching device, regulator, battery protector, panel display driver, and telecommunication device.
The silicon substrate of claim 1, wherein the GaN-based device is a metal- oxide-semiconductor high-electron-mobility-transistor (MOS-HEMT) or an H EMT. Original
The silicon substrate of claim 1, wherein the Si-based device is a MOS field effect transistor (F ET). Original
The silicon substrate of claim 1, wherein the silicon substrate directly contacts a bottom surface of the SiC crystalline region. Previously presented
The silicon substrate of claim 1, further comprising a metal interconnect layer connecting the GaN-based device and the Si-based device. Previously presented
A semiconductor device comprising: a silicon substrate having a first region in the silicon substrate and a second region in the silicon substrate; a plurality of isolation structures in the silicon substrate; a silicon carbide (SiC) crystalline layer over the first region, wherein the SiC crystalline layer is formed by ion implantation in the silicon substrate, a sidewall of the silicon substrate directly contacts a portion of a sidewall of the SiC crystalline la v er ad j acent a top surface of the silicon substrate, the SiC crystalline region is spaced from each isolation structure of the plurality of isolation structures, and a top surface of the SiC crystalline layer is substantially co-planar with a top-most surface of the silicon substrate; a gallium nitride (GaN) device formed on a top-most surface of the SiC crystalline layer; and a metal-oxide-semiconductor (MOS) device formed on the second region. Currently amended
The semiconductor device of claim 8, wherein the MOS device comprises a dielectric layer over the second region, and a thickness of the dielectric layer ranges from about 100 A to about 5000 A. Previously presented
The semiconductor device of claim 8, wherein the GaN device comprises: a GaN layer over the SiC crystalline layer; an aluminum gallium nitride (A l GaN) layer over the GaN layer; and a buffer layer between the GaN layer and the SiC crystalline layer. Original
The semiconductor device of claim 8, further comprising an interconnect structure over the GaN device and the MOS device, wherein the interconnect structure electrically connects the GaN device and the MOS device. Original
The semiconductor device of claim 8, further comprising an isolation structure between the GaN device and the MOS device. Original
The semiconductor device of claim 8, further comprising: a first via connected to a terminal of the GaN device; and a second via connected to a terminal of the MOS device, wherein the first via is in a metal layer farther from the silicon substrate than the second via. Original
Canceled
A semiconductor device comprising: a silicon carbide (SiC) crystalline layer in a substrate, wherein the substrate directly contacts a portion of a sidewall of the SiC crystalline region ad j acent a top surface of the substrate and a bottom surface of the SiC crystalline layer; a plurality of isolation structures in the substrate, wherein each isolation structure of the plurality of isolation structures is spaced from the SiC crystalline region; a first transistor on a top-most surface of the SiC crystalline layer, the first transistor having a first terminal, wherein a first direction from the SiC crystalline layer to the first transistor is normal to a top surface of the substrate, and an interface between the first transistor and the SiC crystalline layer is above a top-most surface of the substrate; a second transistor on a silicon region of the substrate, wherein the silicon region of the substrate is spaced from the SiC crystalline layer in a second direction perpendicular to the first direction, and the second transistor has a first terminal; and an interconnect structure configured to electrically connect the first terminal of the first transistor to the first terminal of the second transistor. Currently amended
The semiconductor device of claim 15, wherein the first transistor is a high electron mobility transistor (HE MT). Previously presented
The semiconductor device of claim 15, wherein a distance from the first terminal of the first transistor to the substrate is greater than a distance from the first terminal of the second transistor to the substrate. Original
The semiconductor device of claim 15, wherein the first transistor comprises a group I II -V compound material. Original
The semiconductor device of claim 15, wherein an isolation structure of the plurality of isolation structures is between the first transistor and the second transistor. Currently amended
The semiconductor device of claim 15, further comprising a dielectric layer for isolating the interconnect structure. Previously presented
The semiconductor device of claim 15, wherein the second transistor is a metal-oxide-semiconductor (MOS) transistor. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based device (MOS-HEMT or HEMT)
Materials described outside the worked examples.
silicon carbide crystalline
SiC
gallium nitride
GaN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
implant-stop layer thickness range | 100–5000 Angstrom | SiO₂ |
MOS device dielectric layer thickness range (claim 10) | 100–5000 Angstrom |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,014,291Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A silicon substrate with a GaN-based device and a Si-based device on the silicon substrate, comprising: the GaN-based device on a SiC crystalline region, wherein the SiC crystalline region is over a portion of the silicon substrate, [[and]] a bottom-most surface of the GaN-based device is above a top-most surface of the silicon substrate, and the SiC crystalline region is spaced from each isolation structures in the silicon substrate; and the Si-based device in direct contact with a silicon region of the silicon substrate, wherein the silicon region directly contacts a portion of a sidewall of the SiC crystalline region adjacent a top surface of the silicon substrate, and the silicon region is adjacent to the SiC crystalline region on the silicon substrate. Currently amended
The silicon substrate of claim 1, wherein a surface of the SiC crystalline region is at about the same level as a surface of the silicon region. Previously presented
(Withdrawn- Previously Presented) The silicon substrate of claim 1, wherein the GaN- based device is selected from the group consisting of light-emitting device, power switching device, regulator, battery protector, panel display driver, and telecommunication device.
The silicon substrate of claim 1, wherein the GaN-based device is a metal- oxide-semiconductor high-electron-mobility-transistor (MOS-HEMT) or an H EMT. Original
The silicon substrate of claim 1, wherein the Si-based device is a MOS field effect transistor (F ET). Original
The silicon substrate of claim 1, wherein the silicon substrate directly contacts a bottom surface of the SiC crystalline region. Previously presented
The silicon substrate of claim 1, further comprising a metal interconnect layer connecting the GaN-based device and the Si-based device. Previously presented
A semiconductor device comprising: a silicon substrate having a first region in the silicon substrate and a second region in the silicon substrate; a plurality of isolation structures in the silicon substrate; a silicon carbide (SiC) crystalline layer over the first region, wherein the SiC crystalline layer is formed by ion implantation in the silicon substrate, a sidewall of the silicon substrate directly contacts a portion of a sidewall of the SiC crystalline la v er ad j acent a top surface of the silicon substrate, the SiC crystalline region is spaced from each isolation structure of the plurality of isolation structures, and a top surface of the SiC crystalline layer is substantially co-planar with a top-most surface of the silicon substrate; a gallium nitride (GaN) device formed on a top-most surface of the SiC crystalline layer; and a metal-oxide-semiconductor (MOS) device formed on the second region. Currently amended
The semiconductor device of claim 8, wherein the MOS device comprises a dielectric layer over the second region, and a thickness of the dielectric layer ranges from about 100 A to about 5000 A. Previously presented
The semiconductor device of claim 8, wherein the GaN device comprises: a GaN layer over the SiC crystalline layer; an aluminum gallium nitride (A l GaN) layer over the GaN layer; and a buffer layer between the GaN layer and the SiC crystalline layer. Original
The semiconductor device of claim 8, further comprising an interconnect structure over the GaN device and the MOS device, wherein the interconnect structure electrically connects the GaN device and the MOS device. Original
The semiconductor device of claim 8, further comprising an isolation structure between the GaN device and the MOS device. Original
The semiconductor device of claim 8, further comprising: a first via connected to a terminal of the GaN device; and a second via connected to a terminal of the MOS device, wherein the first via is in a metal layer farther from the silicon substrate than the second via. Original
Canceled
A semiconductor device comprising: a silicon carbide (SiC) crystalline layer in a substrate, wherein the substrate directly contacts a portion of a sidewall of the SiC crystalline region ad j acent a top surface of the substrate and a bottom surface of the SiC crystalline layer; a plurality of isolation structures in the substrate, wherein each isolation structure of the plurality of isolation structures is spaced from the SiC crystalline region; a first transistor on a top-most surface of the SiC crystalline layer, the first transistor having a first terminal, wherein a first direction from the SiC crystalline layer to the first transistor is normal to a top surface of the substrate, and an interface between the first transistor and the SiC crystalline layer is above a top-most surface of the substrate; a second transistor on a silicon region of the substrate, wherein the silicon region of the substrate is spaced from the SiC crystalline layer in a second direction perpendicular to the first direction, and the second transistor has a first terminal; and an interconnect structure configured to electrically connect the first terminal of the first transistor to the first terminal of the second transistor. Currently amended
The semiconductor device of claim 15, wherein the first transistor is a high electron mobility transistor (HE MT). Previously presented
The semiconductor device of claim 15, wherein a distance from the first terminal of the first transistor to the substrate is greater than a distance from the first terminal of the second transistor to the substrate. Original
The semiconductor device of claim 15, wherein the first transistor comprises a group I II -V compound material. Original
The semiconductor device of claim 15, wherein an isolation structure of the plurality of isolation structures is between the first transistor and the second transistor. Currently amended
The semiconductor device of claim 15, further comprising a dielectric layer for isolating the interconnect structure. Previously presented
The semiconductor device of claim 15, wherein the second transistor is a metal-oxide-semiconductor (MOS) transistor. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based device (MOS-HEMT or HEMT)
Materials described outside the worked examples.
silicon carbide crystalline
SiC
gallium nitride
GaN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
implant-stop layer thickness range | 100–5000 Angstrom | SiO₂ |
MOS device dielectric layer thickness range (claim 10) | 100–5000 Angstrom |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,014,291Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A silicon substrate with a GaN-based device and a Si-based device on the silicon substrate, comprising: the GaN-based device on a SiC crystalline region, wherein the SiC crystalline region is over a portion of the silicon substrate, [[and]] a bottom-most surface of the GaN-based device is above a top-most surface of the silicon substrate, and the SiC crystalline region is spaced from each isolation structures in the silicon substrate; and the Si-based device in direct contact with a silicon region of the silicon substrate, wherein the silicon region directly contacts a portion of a sidewall of the SiC crystalline region adjacent a top surface of the silicon substrate, and the silicon region is adjacent to the SiC crystalline region on the silicon substrate. Currently amended
The silicon substrate of claim 1, wherein a surface of the SiC crystalline region is at about the same level as a surface of the silicon region. Previously presented
(Withdrawn- Previously Presented) The silicon substrate of claim 1, wherein the GaN- based device is selected from the group consisting of light-emitting device, power switching device, regulator, battery protector, panel display driver, and telecommunication device.
The silicon substrate of claim 1, wherein the GaN-based device is a metal- oxide-semiconductor high-electron-mobility-transistor (MOS-HEMT) or an H EMT. Original
The silicon substrate of claim 1, wherein the Si-based device is a MOS field effect transistor (F ET). Original
The silicon substrate of claim 1, wherein the silicon substrate directly contacts a bottom surface of the SiC crystalline region. Previously presented
The silicon substrate of claim 1, further comprising a metal interconnect layer connecting the GaN-based device and the Si-based device. Previously presented
A semiconductor device comprising: a silicon substrate having a first region in the silicon substrate and a second region in the silicon substrate; a plurality of isolation structures in the silicon substrate; a silicon carbide (SiC) crystalline layer over the first region, wherein the SiC crystalline layer is formed by ion implantation in the silicon substrate, a sidewall of the silicon substrate directly contacts a portion of a sidewall of the SiC crystalline la v er ad j acent a top surface of the silicon substrate, the SiC crystalline region is spaced from each isolation structure of the plurality of isolation structures, and a top surface of the SiC crystalline layer is substantially co-planar with a top-most surface of the silicon substrate; a gallium nitride (GaN) device formed on a top-most surface of the SiC crystalline layer; and a metal-oxide-semiconductor (MOS) device formed on the second region. Currently amended
The semiconductor device of claim 8, wherein the MOS device comprises a dielectric layer over the second region, and a thickness of the dielectric layer ranges from about 100 A to about 5000 A. Previously presented
The semiconductor device of claim 8, wherein the GaN device comprises: a GaN layer over the SiC crystalline layer; an aluminum gallium nitride (A l GaN) layer over the GaN layer; and a buffer layer between the GaN layer and the SiC crystalline layer. Original
The semiconductor device of claim 8, further comprising an interconnect structure over the GaN device and the MOS device, wherein the interconnect structure electrically connects the GaN device and the MOS device. Original
The semiconductor device of claim 8, further comprising an isolation structure between the GaN device and the MOS device. Original
The semiconductor device of claim 8, further comprising: a first via connected to a terminal of the GaN device; and a second via connected to a terminal of the MOS device, wherein the first via is in a metal layer farther from the silicon substrate than the second via. Original
Canceled
A semiconductor device comprising: a silicon carbide (SiC) crystalline layer in a substrate, wherein the substrate directly contacts a portion of a sidewall of the SiC crystalline region ad j acent a top surface of the substrate and a bottom surface of the SiC crystalline layer; a plurality of isolation structures in the substrate, wherein each isolation structure of the plurality of isolation structures is spaced from the SiC crystalline region; a first transistor on a top-most surface of the SiC crystalline layer, the first transistor having a first terminal, wherein a first direction from the SiC crystalline layer to the first transistor is normal to a top surface of the substrate, and an interface between the first transistor and the SiC crystalline layer is above a top-most surface of the substrate; a second transistor on a silicon region of the substrate, wherein the silicon region of the substrate is spaced from the SiC crystalline layer in a second direction perpendicular to the first direction, and the second transistor has a first terminal; and an interconnect structure configured to electrically connect the first terminal of the first transistor to the first terminal of the second transistor. Currently amended
The semiconductor device of claim 15, wherein the first transistor is a high electron mobility transistor (HE MT). Previously presented
The semiconductor device of claim 15, wherein a distance from the first terminal of the first transistor to the substrate is greater than a distance from the first terminal of the second transistor to the substrate. Original
The semiconductor device of claim 15, wherein the first transistor comprises a group I II -V compound material. Original
The semiconductor device of claim 15, wherein an isolation structure of the plurality of isolation structures is between the first transistor and the second transistor. Currently amended
The semiconductor device of claim 15, further comprising a dielectric layer for isolating the interconnect structure. Previously presented
The semiconductor device of claim 15, wherein the second transistor is a metal-oxide-semiconductor (MOS) transistor. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based device (MOS-HEMT or HEMT)
Materials described outside the worked examples.
silicon carbide crystalline
SiC
gallium nitride
GaN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
implant-stop layer thickness range | 100–5000 Angstrom | SiO₂ |
MOS device dielectric layer thickness range (claim 10) | 100–5000 Angstrom |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,014,291Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A silicon substrate with a GaN-based device and a Si-based device on the silicon substrate, comprising: the GaN-based device on a SiC crystalline region, wherein the SiC crystalline region is over a portion of the silicon substrate, [[and]] a bottom-most surface of the GaN-based device is above a top-most surface of the silicon substrate, and the SiC crystalline region is spaced from each isolation structures in the silicon substrate; and the Si-based device in direct contact with a silicon region of the silicon substrate, wherein the silicon region directly contacts a portion of a sidewall of the SiC crystalline region adjacent a top surface of the silicon substrate, and the silicon region is adjacent to the SiC crystalline region on the silicon substrate. Currently amended
The silicon substrate of claim 1, wherein a surface of the SiC crystalline region is at about the same level as a surface of the silicon region. Previously presented
(Withdrawn- Previously Presented) The silicon substrate of claim 1, wherein the GaN- based device is selected from the group consisting of light-emitting device, power switching device, regulator, battery protector, panel display driver, and telecommunication device.
The silicon substrate of claim 1, wherein the GaN-based device is a metal- oxide-semiconductor high-electron-mobility-transistor (MOS-HEMT) or an H EMT. Original
The silicon substrate of claim 1, wherein the Si-based device is a MOS field effect transistor (F ET). Original
The silicon substrate of claim 1, wherein the silicon substrate directly contacts a bottom surface of the SiC crystalline region. Previously presented
The silicon substrate of claim 1, further comprising a metal interconnect layer connecting the GaN-based device and the Si-based device. Previously presented
A semiconductor device comprising: a silicon substrate having a first region in the silicon substrate and a second region in the silicon substrate; a plurality of isolation structures in the silicon substrate; a silicon carbide (SiC) crystalline layer over the first region, wherein the SiC crystalline layer is formed by ion implantation in the silicon substrate, a sidewall of the silicon substrate directly contacts a portion of a sidewall of the SiC crystalline la v er ad j acent a top surface of the silicon substrate, the SiC crystalline region is spaced from each isolation structure of the plurality of isolation structures, and a top surface of the SiC crystalline layer is substantially co-planar with a top-most surface of the silicon substrate; a gallium nitride (GaN) device formed on a top-most surface of the SiC crystalline layer; and a metal-oxide-semiconductor (MOS) device formed on the second region. Currently amended
The semiconductor device of claim 8, wherein the MOS device comprises a dielectric layer over the second region, and a thickness of the dielectric layer ranges from about 100 A to about 5000 A. Previously presented
The semiconductor device of claim 8, wherein the GaN device comprises: a GaN layer over the SiC crystalline layer; an aluminum gallium nitride (A l GaN) layer over the GaN layer; and a buffer layer between the GaN layer and the SiC crystalline layer. Original
The semiconductor device of claim 8, further comprising an interconnect structure over the GaN device and the MOS device, wherein the interconnect structure electrically connects the GaN device and the MOS device. Original
The semiconductor device of claim 8, further comprising an isolation structure between the GaN device and the MOS device. Original
The semiconductor device of claim 8, further comprising: a first via connected to a terminal of the GaN device; and a second via connected to a terminal of the MOS device, wherein the first via is in a metal layer farther from the silicon substrate than the second via. Original
Canceled
A semiconductor device comprising: a silicon carbide (SiC) crystalline layer in a substrate, wherein the substrate directly contacts a portion of a sidewall of the SiC crystalline region ad j acent a top surface of the substrate and a bottom surface of the SiC crystalline layer; a plurality of isolation structures in the substrate, wherein each isolation structure of the plurality of isolation structures is spaced from the SiC crystalline region; a first transistor on a top-most surface of the SiC crystalline layer, the first transistor having a first terminal, wherein a first direction from the SiC crystalline layer to the first transistor is normal to a top surface of the substrate, and an interface between the first transistor and the SiC crystalline layer is above a top-most surface of the substrate; a second transistor on a silicon region of the substrate, wherein the silicon region of the substrate is spaced from the SiC crystalline layer in a second direction perpendicular to the first direction, and the second transistor has a first terminal; and an interconnect structure configured to electrically connect the first terminal of the first transistor to the first terminal of the second transistor. Currently amended
The semiconductor device of claim 15, wherein the first transistor is a high electron mobility transistor (HE MT). Previously presented
The semiconductor device of claim 15, wherein a distance from the first terminal of the first transistor to the substrate is greater than a distance from the first terminal of the second transistor to the substrate. Original
The semiconductor device of claim 15, wherein the first transistor comprises a group I II -V compound material. Original
The semiconductor device of claim 15, wherein an isolation structure of the plurality of isolation structures is between the first transistor and the second transistor. Currently amended
The semiconductor device of claim 15, further comprising a dielectric layer for isolating the interconnect structure. Previously presented
The semiconductor device of claim 15, wherein the second transistor is a metal-oxide-semiconductor (MOS) transistor. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based device (MOS-HEMT or HEMT)
Materials described outside the worked examples.
silicon carbide crystalline
SiC
gallium nitride
GaN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
implant-stop layer thickness range | 100–5000 Angstrom | SiO₂ |
MOS device dielectric layer thickness range (claim 10) | 100–5000 Angstrom |
Related documents with shared materials, methods, properties, or citations.
Si-based MOS field effect transistor
first transistor (GaN/III-V HEMT) on SiC crystalline layer
second transistor (MOS transistor) on silicon region
Si
aluminum gallium nitride
AlGaN
buffer layer
aluminum oxide gate dielectric
Al₂O₃
group III-V compound material
silicon dioxide implant-stop layer
SiO₂
carbon implant species
C
Temperature | 500–900 °C | — |
Temperature | 900–1200 °C | — |
Duration | 2–45 minutes | — |
Duration | 1800–14400 s | — |
Temperature | 200–1200 °C | — |
Thickness | 10–1000 nm | — |
Si-based MOS field effect transistor
first transistor (GaN/III-V HEMT) on SiC crystalline layer
second transistor (MOS transistor) on silicon region
Si
aluminum gallium nitride
AlGaN
buffer layer
aluminum oxide gate dielectric
Al₂O₃
group III-V compound material
silicon dioxide implant-stop layer
SiO₂
carbon implant species
C
Temperature | 500–900 °C | — |
Temperature | 900–1200 °C | — |
Duration | 2–45 minutes | — |
Duration | 1800–14400 s | — |
Temperature | 200–1200 °C | — |
Thickness | 10–1000 nm | — |
Si-based MOS field effect transistor
first transistor (GaN/III-V HEMT) on SiC crystalline layer
second transistor (MOS transistor) on silicon region
Si
aluminum gallium nitride
AlGaN
buffer layer
aluminum oxide gate dielectric
Al₂O₃
group III-V compound material
silicon dioxide implant-stop layer
SiO₂
carbon implant species
C
Temperature | 500–900 °C | — |
Temperature | 900–1200 °C | — |
Duration | 2–45 minutes | — |
Duration | 1800–14400 s | — |
Temperature | 200–1200 °C | — |
Thickness | 10–1000 nm | — |
Si-based MOS field effect transistor
first transistor (GaN/III-V HEMT) on SiC crystalline layer
second transistor (MOS transistor) on silicon region
Si
aluminum gallium nitride
AlGaN
buffer layer
aluminum oxide gate dielectric
Al₂O₃
group III-V compound material
silicon dioxide implant-stop layer
SiO₂
carbon implant species
C
Temperature | 500–900 °C | — |
Temperature | 900–1200 °C | — |
Duration | 2–45 minutes | — |
Duration | 1800–14400 s | — |
Temperature | 200–1200 °C | — |
Thickness | 10–1000 nm | — |