Patent
US 8,198,707ESTABLISHING A UNIFORMLY THIN DIELECTRIC LAYER ON GRAPHENE IN A SEMICONDUCTOR DEVICE WITHOUT AFFECTING THE PROPERTIES OF GRAPHENE
Luigi Colombo
US
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Patent
Atlas literature
Patent
US 8,198,707Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 is a flowchart of a method for forming a uniformly thin dielectric layer on graphene in accordance with an embodiment of the present invention;
Figures 2A-D depict cross-sectional views of a semiconductor device during the fabrication of the steps described in
Figure 3 is an alternative method for forming a uniformly thin dielectric layer on graphene in accordance with an embodiment of the present invention;
Figures 4A-D depict cross-sectional views of a semiconductor device during the fabrication of the steps described in
Figure 5 is another alternative method for forming a uniformly thin dielectric layer on graphene in accordance with an embodiment of the present invention; and
Figures 6 A-E depict cross-sectional views of a semiconductor device during the fabrication of the steps described in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
CLAIMS: 1 1. A semiconductor device, comprising: 2 a silicon base layer; 3 a first dielectric layer on said silicon base layer; 4 a graphene layer on said first dielectric layer; and 5 one of a metal and a semiconductor layer on said graphene layer, wherein said 6 one of said metal and semiconductor layer acts as a nucleation layer for said graphene 7 layer.
84-P O₄₀ US Page 15 of 21 PATENT 1 7. The semiconductor device as recited in claim 1, wherein one of said metal and 2 said semiconductor layer is deposited on said graphene layer via physical vapor 3 deposition.
Layer stacks claimed or described, ordered top of device to substrate.
graphene-based semiconductor device
graphene semiconductor device with gate dielectric formed via oxidized nucleation layer
Materials described outside the worked examples.
silicon
Si
dielectric
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
graphene dielectric thickness range (target) | — | metal-oxide dielectric layer |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,198,707Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 is a flowchart of a method for forming a uniformly thin dielectric layer on graphene in accordance with an embodiment of the present invention;
Figures 2A-D depict cross-sectional views of a semiconductor device during the fabrication of the steps described in
Figure 3 is an alternative method for forming a uniformly thin dielectric layer on graphene in accordance with an embodiment of the present invention;
Figures 4A-D depict cross-sectional views of a semiconductor device during the fabrication of the steps described in
Figure 5 is another alternative method for forming a uniformly thin dielectric layer on graphene in accordance with an embodiment of the present invention; and
Figures 6 A-E depict cross-sectional views of a semiconductor device during the fabrication of the steps described in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
CLAIMS: 1 1. A semiconductor device, comprising: 2 a silicon base layer; 3 a first dielectric layer on said silicon base layer; 4 a graphene layer on said first dielectric layer; and 5 one of a metal and a semiconductor layer on said graphene layer, wherein said 6 one of said metal and semiconductor layer acts as a nucleation layer for said graphene 7 layer.
84-P O₄₀ US Page 15 of 21 PATENT 1 7. The semiconductor device as recited in claim 1, wherein one of said metal and 2 said semiconductor layer is deposited on said graphene layer via physical vapor 3 deposition.
Layer stacks claimed or described, ordered top of device to substrate.
graphene-based semiconductor device
graphene semiconductor device with gate dielectric formed via oxidized nucleation layer
Materials described outside the worked examples.
silicon
Si
dielectric
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
graphene dielectric thickness range (target) | — | metal-oxide dielectric layer |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,198,707Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 is a flowchart of a method for forming a uniformly thin dielectric layer on graphene in accordance with an embodiment of the present invention;
Figures 2A-D depict cross-sectional views of a semiconductor device during the fabrication of the steps described in
Figure 3 is an alternative method for forming a uniformly thin dielectric layer on graphene in accordance with an embodiment of the present invention;
Figures 4A-D depict cross-sectional views of a semiconductor device during the fabrication of the steps described in
Figure 5 is another alternative method for forming a uniformly thin dielectric layer on graphene in accordance with an embodiment of the present invention; and
Figures 6 A-E depict cross-sectional views of a semiconductor device during the fabrication of the steps described in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
CLAIMS: 1 1. A semiconductor device, comprising: 2 a silicon base layer; 3 a first dielectric layer on said silicon base layer; 4 a graphene layer on said first dielectric layer; and 5 one of a metal and a semiconductor layer on said graphene layer, wherein said 6 one of said metal and semiconductor layer acts as a nucleation layer for said graphene 7 layer.
84-P O₄₀ US Page 15 of 21 PATENT 1 7. The semiconductor device as recited in claim 1, wherein one of said metal and 2 said semiconductor layer is deposited on said graphene layer via physical vapor 3 deposition.
Layer stacks claimed or described, ordered top of device to substrate.
graphene-based semiconductor device
graphene semiconductor device with gate dielectric formed via oxidized nucleation layer
Materials described outside the worked examples.
silicon
Si
dielectric
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
graphene dielectric thickness range (target) | — | metal-oxide dielectric layer |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,198,707Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 is a flowchart of a method for forming a uniformly thin dielectric layer on graphene in accordance with an embodiment of the present invention;
Figures 2A-D depict cross-sectional views of a semiconductor device during the fabrication of the steps described in
Figure 3 is an alternative method for forming a uniformly thin dielectric layer on graphene in accordance with an embodiment of the present invention;
Figures 4A-D depict cross-sectional views of a semiconductor device during the fabrication of the steps described in
Figure 5 is another alternative method for forming a uniformly thin dielectric layer on graphene in accordance with an embodiment of the present invention; and
Figures 6 A-E depict cross-sectional views of a semiconductor device during the fabrication of the steps described in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
CLAIMS: 1 1. A semiconductor device, comprising: 2 a silicon base layer; 3 a first dielectric layer on said silicon base layer; 4 a graphene layer on said first dielectric layer; and 5 one of a metal and a semiconductor layer on said graphene layer, wherein said 6 one of said metal and semiconductor layer acts as a nucleation layer for said graphene 7 layer.
84-P O₄₀ US Page 15 of 21 PATENT 1 7. The semiconductor device as recited in claim 1, wherein one of said metal and 2 said semiconductor layer is deposited on said graphene layer via physical vapor 3 deposition.
Layer stacks claimed or described, ordered top of device to substrate.
graphene-based semiconductor device
graphene semiconductor device with gate dielectric formed via oxidized nucleation layer
Materials described outside the worked examples.
silicon
Si
dielectric
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
graphene dielectric thickness range (target) | — | metal-oxide dielectric layer |
Related documents with shared materials, methods, properties, or citations.
graphene
metal or semiconductor nucleation layer
metal-oxide dielectric layer
silicon carbide
SiC
silicon dioxide
SiO₂
Method of Manufacturing N-Doped Graphene and Electrical Component Using NH4F, and Graphene and Electrical Component Thereby
graphene
metal or semiconductor nucleation layer
metal-oxide dielectric layer
silicon carbide
SiC
silicon dioxide
SiO₂
Method of Manufacturing N-Doped Graphene and Electrical Component Using NH4F, and Graphene and Electrical Component Thereby
graphene
metal or semiconductor nucleation layer
metal-oxide dielectric layer
silicon carbide
SiC
silicon dioxide
SiO₂
Method of Manufacturing N-Doped Graphene and Electrical Component Using NH4F, and Graphene and Electrical Component Thereby
graphene
metal or semiconductor nucleation layer
metal-oxide dielectric layer
silicon carbide
SiC
silicon dioxide
SiO₂
Method of Manufacturing N-Doped Graphene and Electrical Component Using NH4F, and Graphene and Electrical Component Thereby