Patent
US 8,383,499Method for Forming Gallium Nitride Semiconductor Device With Improved Forward Conduction
TingGang Zhu
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
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US 8,383,499Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 duplicates
Figure 3A of U.S. Patent No. 7,084,475 B 1 and illustrates a GaN semiconductor device.
Figure 2 duplicates
Figure 6A of U.S. Patent No. 7,084,475 B 1 and illustrates a GaN semiconductor device.
Figure 3 is a perspective view of a GaN Schottky diode according to a first embodiment of the present invention.
Figure 4 is a top view of the GaN Schottky diode of
Figure 5 is a top view of the GaN Schottky diode according to a second embodiment of the present invention.
Figure 6 is a top view of the GaN Schottky diode according to a third embodiment of the present invention.
Figure 7 is a flow chart illustrating the fabrication process for fabricating the GaN Schottky diode of
Figure 8 is a cross-sectional view of a GaN Schottky diode according to an alternate embodiment of the present invention.
Figure 9 is a flow chart illustrating the fabrication process for fabricating the GaN Schottky diode of
Figure 10 is a flow chart illustrating the fabrication process for fabricating the GaN Schottky diode of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for forming a gallium nitride based semiconductor diode, comprising: providing a substrate; forming a semiconductor body comprising a first GaN layer of a first conductivity type formed on the substrate and a second GaN layer of the first conductivity type on the first GaN layer, the second GaN layer being more lightly doped than the first GaN layer; forming a plurality of mesas in the semiconductor body projecting upwardly from a lower surface, the lower surface extending partially into the first GaN layer, each of the plurality of mesas including the second GaN layer and a portion of the first GaN layer; forming a first metal layer on an upper surface of the plurality of mesas for forming a Schottky junction with the second GaN layer; forming a second metal layer on the lower surface between the plurality of mesas to form ohmic contacts to the first GaN layer; forming an insulating layer over the first and second metal layers; forming a first plurality of vias in the insulating layer to form openings to the first metal layer, the first plurality of vias being filled with a via metal; forming a second plurality of vias in the insulating layer between the plurality of mesas to form openings to the second metal layer, the second plurality of vias being filled with the via metal;-17-forming a first metal pad overlying the insulating layer and in electrical contact with the first plurality of vias, the first metal pad forming an anode electrode; and forming a second metal pad formed overlying the insulating layer and in electrical contact with the second plurality of vias, the second metal pad forming a cathode electrode.
The method of claim 1, wherein providing a substrate comprises providing an insulating substrate.
The method of claim 1, wherein providing a substrate comprises providing a conducting substrate and an overlying buffer layer.
The method of claim 1, wherein the first conductivity type comprises N-type conductivity.
The method of claim 1, wherein forming a plurality of mesas in the semiconductor body comprises forming the plurality of mesas as separated parallel elongated linear regions of the second GaN layer and the portion of the first GaN layer, the linear regions being interdigitated with the ohmic contacts in the lower surface.
The method of claim 1, wherein forming a plurality of mesas in the semiconductor body comprises forming the plurality of mesas as separated concentric ring-shaped regions of the second GaN layer and the portion of the first GaN layer, the concentric regions being interdigitated with the ohmic contacts in the lower surface of the semiconductor body.
The method of claim 1, wherein the first metal layer comprises a metal selected from the group of Ni, Pt, Au, Co, Pd, Cr, Rh, Re, PtSi, V, W, WSi and NiSi.
The method of claim 1, wherein the second metal layer comprises a metal selected from the group of Al, AlSi, Ti, TiSi, Mo, and MoSi.
The method of claim 1, wherein the via metal comprises a metal selected from the group of W, TiW, Al, Au, Cu, Ti, Ag and AlCuSi.
The method of claim 1, wherein the third metal layer comprises a metal selected from the group of Al, AlCuSi, Au, Ag, Cu and Ti.
- 20-18. A method for forming a gallium nitride based semiconductor diode, comprising: providing a conducting substrate; forming an insulating buffer layer on a first surface of the conducting substrate; forming a semiconductor body comprising a first GaN layer of a first conductivity type formed on the insulating buffer layer and a second GaN layer of the first conductivity type formed on the first GaN layer, the second GaN layer being more lightly doped than the first GaN layer; forming a plurality of mesas projecting upwardly from a lower surface, the lower surface extending partially into the first GaN layer, each of the plurality of mesas including the second GaN layer and a portion of the first GaN layer; forming a second plurality of vias in the semiconductor body and the insulating buffer layer at the lower surface of the plurality of mesas, the second plurality of vias being filled with a second via metal; forming a first metal layer on an upper surface of the plurality of mesas for forming a Schottky junction with the second GaN layer; forming a second metal layer on the lower surface of the semiconductor body between the plurality of mesas for forming ohmic contacts to the first GaN layer, the second metal layer being electrically connected to the conducting substrate through the second plurality of vias; forming an insulating layer over the first and second metal layers;-21-forming a first plurality of vias in the insulating layer to form openings to the first metal layer, the first plurality of vias being filled with a first via metal; forming a first metal pad overlying the insulating layer and in electrical contact with the first plurality of vias, the first metal pad forming an anode electrode; and forming a second metal pad on a second surface of the conducting substrate, the second surface being opposite the first surface, the second metal pad forming a cathode electrode.
The method of claim 18, wherein the first conductivity type comprises N-type conductivity.
The method of claim 18, wherein forming a plurality of mesas in the semiconductor body comprises forming the plurality of mesas as separated parallel elongated linear regions of the second GaN layer and the portion of the first GaN layer, the linear regions being interdigitated with the ohmic contacts formed on the lower surface of the semiconductor body.
The method of claim 18, wherein forming a plurality of mesas in the semiconductor body comprises forming the plurality of mesas as separated concentric ring-shaped regions of the second GaN layer and the portion of the first GaN layer, the concentric regions being interdigitated with the ohmic contacts in the lower surface of the semiconductor body.
The method of claim 18, wherein forming a second plurality of vias in the semiconductor body and the insulating buffer layer is carried out before forming a plurality of mesas, the second plurality of vias being formed at a location in the semiconductor body where the lower surface of the plurality of mesas is to be formed.
The method of claim 18, wherein the first metal group of Ni, Pt, Au, Co, Pd, Cr, Rh, Re, PtSi, V,
The method of claim 18, wherein the via metal W, TiW, Al, Au, Cu, Ti, Ag and AlCuSi. layer comprises a metal selected from the W, WSi and NiSi. comprises a metal selected from the group of
Layer stacks claimed or described, ordered top of device to substrate.
GaN Schottky diode (lateral cathode, insulating substrate)
Materials described outside the worked examples.
GaN (first layer, heavily doped)
GaN
ohmic contact metal (Al, AlSi, Ti, TiSi, Mo, MoSi)
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,383,499Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 duplicates
Figure 3A of U.S. Patent No. 7,084,475 B 1 and illustrates a GaN semiconductor device.
Figure 2 duplicates
Figure 6A of U.S. Patent No. 7,084,475 B 1 and illustrates a GaN semiconductor device.
Figure 3 is a perspective view of a GaN Schottky diode according to a first embodiment of the present invention.
Figure 4 is a top view of the GaN Schottky diode of
Figure 5 is a top view of the GaN Schottky diode according to a second embodiment of the present invention.
Figure 6 is a top view of the GaN Schottky diode according to a third embodiment of the present invention.
Figure 7 is a flow chart illustrating the fabrication process for fabricating the GaN Schottky diode of
Figure 8 is a cross-sectional view of a GaN Schottky diode according to an alternate embodiment of the present invention.
Figure 9 is a flow chart illustrating the fabrication process for fabricating the GaN Schottky diode of
Figure 10 is a flow chart illustrating the fabrication process for fabricating the GaN Schottky diode of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for forming a gallium nitride based semiconductor diode, comprising: providing a substrate; forming a semiconductor body comprising a first GaN layer of a first conductivity type formed on the substrate and a second GaN layer of the first conductivity type on the first GaN layer, the second GaN layer being more lightly doped than the first GaN layer; forming a plurality of mesas in the semiconductor body projecting upwardly from a lower surface, the lower surface extending partially into the first GaN layer, each of the plurality of mesas including the second GaN layer and a portion of the first GaN layer; forming a first metal layer on an upper surface of the plurality of mesas for forming a Schottky junction with the second GaN layer; forming a second metal layer on the lower surface between the plurality of mesas to form ohmic contacts to the first GaN layer; forming an insulating layer over the first and second metal layers; forming a first plurality of vias in the insulating layer to form openings to the first metal layer, the first plurality of vias being filled with a via metal; forming a second plurality of vias in the insulating layer between the plurality of mesas to form openings to the second metal layer, the second plurality of vias being filled with the via metal;-17-forming a first metal pad overlying the insulating layer and in electrical contact with the first plurality of vias, the first metal pad forming an anode electrode; and forming a second metal pad formed overlying the insulating layer and in electrical contact with the second plurality of vias, the second metal pad forming a cathode electrode.
The method of claim 1, wherein providing a substrate comprises providing an insulating substrate.
The method of claim 1, wherein providing a substrate comprises providing a conducting substrate and an overlying buffer layer.
The method of claim 1, wherein the first conductivity type comprises N-type conductivity.
The method of claim 1, wherein forming a plurality of mesas in the semiconductor body comprises forming the plurality of mesas as separated parallel elongated linear regions of the second GaN layer and the portion of the first GaN layer, the linear regions being interdigitated with the ohmic contacts in the lower surface.
The method of claim 1, wherein forming a plurality of mesas in the semiconductor body comprises forming the plurality of mesas as separated concentric ring-shaped regions of the second GaN layer and the portion of the first GaN layer, the concentric regions being interdigitated with the ohmic contacts in the lower surface of the semiconductor body.
The method of claim 1, wherein the first metal layer comprises a metal selected from the group of Ni, Pt, Au, Co, Pd, Cr, Rh, Re, PtSi, V, W, WSi and NiSi.
The method of claim 1, wherein the second metal layer comprises a metal selected from the group of Al, AlSi, Ti, TiSi, Mo, and MoSi.
The method of claim 1, wherein the via metal comprises a metal selected from the group of W, TiW, Al, Au, Cu, Ti, Ag and AlCuSi.
The method of claim 1, wherein the third metal layer comprises a metal selected from the group of Al, AlCuSi, Au, Ag, Cu and Ti.
- 20-18. A method for forming a gallium nitride based semiconductor diode, comprising: providing a conducting substrate; forming an insulating buffer layer on a first surface of the conducting substrate; forming a semiconductor body comprising a first GaN layer of a first conductivity type formed on the insulating buffer layer and a second GaN layer of the first conductivity type formed on the first GaN layer, the second GaN layer being more lightly doped than the first GaN layer; forming a plurality of mesas projecting upwardly from a lower surface, the lower surface extending partially into the first GaN layer, each of the plurality of mesas including the second GaN layer and a portion of the first GaN layer; forming a second plurality of vias in the semiconductor body and the insulating buffer layer at the lower surface of the plurality of mesas, the second plurality of vias being filled with a second via metal; forming a first metal layer on an upper surface of the plurality of mesas for forming a Schottky junction with the second GaN layer; forming a second metal layer on the lower surface of the semiconductor body between the plurality of mesas for forming ohmic contacts to the first GaN layer, the second metal layer being electrically connected to the conducting substrate through the second plurality of vias; forming an insulating layer over the first and second metal layers;-21-forming a first plurality of vias in the insulating layer to form openings to the first metal layer, the first plurality of vias being filled with a first via metal; forming a first metal pad overlying the insulating layer and in electrical contact with the first plurality of vias, the first metal pad forming an anode electrode; and forming a second metal pad on a second surface of the conducting substrate, the second surface being opposite the first surface, the second metal pad forming a cathode electrode.
The method of claim 18, wherein the first conductivity type comprises N-type conductivity.
The method of claim 18, wherein forming a plurality of mesas in the semiconductor body comprises forming the plurality of mesas as separated parallel elongated linear regions of the second GaN layer and the portion of the first GaN layer, the linear regions being interdigitated with the ohmic contacts formed on the lower surface of the semiconductor body.
The method of claim 18, wherein forming a plurality of mesas in the semiconductor body comprises forming the plurality of mesas as separated concentric ring-shaped regions of the second GaN layer and the portion of the first GaN layer, the concentric regions being interdigitated with the ohmic contacts in the lower surface of the semiconductor body.
The method of claim 18, wherein forming a second plurality of vias in the semiconductor body and the insulating buffer layer is carried out before forming a plurality of mesas, the second plurality of vias being formed at a location in the semiconductor body where the lower surface of the plurality of mesas is to be formed.
The method of claim 18, wherein the first metal group of Ni, Pt, Au, Co, Pd, Cr, Rh, Re, PtSi, V,
The method of claim 18, wherein the via metal W, TiW, Al, Au, Cu, Ti, Ag and AlCuSi. layer comprises a metal selected from the W, WSi and NiSi. comprises a metal selected from the group of
Layer stacks claimed or described, ordered top of device to substrate.
GaN Schottky diode (lateral cathode, insulating substrate)
Materials described outside the worked examples.
GaN (first layer, heavily doped)
GaN
ohmic contact metal (Al, AlSi, Ti, TiSi, Mo, MoSi)
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,383,499Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 duplicates
Figure 3A of U.S. Patent No. 7,084,475 B 1 and illustrates a GaN semiconductor device.
Figure 2 duplicates
Figure 6A of U.S. Patent No. 7,084,475 B 1 and illustrates a GaN semiconductor device.
Figure 3 is a perspective view of a GaN Schottky diode according to a first embodiment of the present invention.
Figure 4 is a top view of the GaN Schottky diode of
Figure 5 is a top view of the GaN Schottky diode according to a second embodiment of the present invention.
Figure 6 is a top view of the GaN Schottky diode according to a third embodiment of the present invention.
Figure 7 is a flow chart illustrating the fabrication process for fabricating the GaN Schottky diode of
Figure 8 is a cross-sectional view of a GaN Schottky diode according to an alternate embodiment of the present invention.
Figure 9 is a flow chart illustrating the fabrication process for fabricating the GaN Schottky diode of
Figure 10 is a flow chart illustrating the fabrication process for fabricating the GaN Schottky diode of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for forming a gallium nitride based semiconductor diode, comprising: providing a substrate; forming a semiconductor body comprising a first GaN layer of a first conductivity type formed on the substrate and a second GaN layer of the first conductivity type on the first GaN layer, the second GaN layer being more lightly doped than the first GaN layer; forming a plurality of mesas in the semiconductor body projecting upwardly from a lower surface, the lower surface extending partially into the first GaN layer, each of the plurality of mesas including the second GaN layer and a portion of the first GaN layer; forming a first metal layer on an upper surface of the plurality of mesas for forming a Schottky junction with the second GaN layer; forming a second metal layer on the lower surface between the plurality of mesas to form ohmic contacts to the first GaN layer; forming an insulating layer over the first and second metal layers; forming a first plurality of vias in the insulating layer to form openings to the first metal layer, the first plurality of vias being filled with a via metal; forming a second plurality of vias in the insulating layer between the plurality of mesas to form openings to the second metal layer, the second plurality of vias being filled with the via metal;-17-forming a first metal pad overlying the insulating layer and in electrical contact with the first plurality of vias, the first metal pad forming an anode electrode; and forming a second metal pad formed overlying the insulating layer and in electrical contact with the second plurality of vias, the second metal pad forming a cathode electrode.
The method of claim 1, wherein providing a substrate comprises providing an insulating substrate.
The method of claim 1, wherein providing a substrate comprises providing a conducting substrate and an overlying buffer layer.
The method of claim 1, wherein the first conductivity type comprises N-type conductivity.
The method of claim 1, wherein forming a plurality of mesas in the semiconductor body comprises forming the plurality of mesas as separated parallel elongated linear regions of the second GaN layer and the portion of the first GaN layer, the linear regions being interdigitated with the ohmic contacts in the lower surface.
The method of claim 1, wherein forming a plurality of mesas in the semiconductor body comprises forming the plurality of mesas as separated concentric ring-shaped regions of the second GaN layer and the portion of the first GaN layer, the concentric regions being interdigitated with the ohmic contacts in the lower surface of the semiconductor body.
The method of claim 1, wherein the first metal layer comprises a metal selected from the group of Ni, Pt, Au, Co, Pd, Cr, Rh, Re, PtSi, V, W, WSi and NiSi.
The method of claim 1, wherein the second metal layer comprises a metal selected from the group of Al, AlSi, Ti, TiSi, Mo, and MoSi.
The method of claim 1, wherein the via metal comprises a metal selected from the group of W, TiW, Al, Au, Cu, Ti, Ag and AlCuSi.
The method of claim 1, wherein the third metal layer comprises a metal selected from the group of Al, AlCuSi, Au, Ag, Cu and Ti.
- 20-18. A method for forming a gallium nitride based semiconductor diode, comprising: providing a conducting substrate; forming an insulating buffer layer on a first surface of the conducting substrate; forming a semiconductor body comprising a first GaN layer of a first conductivity type formed on the insulating buffer layer and a second GaN layer of the first conductivity type formed on the first GaN layer, the second GaN layer being more lightly doped than the first GaN layer; forming a plurality of mesas projecting upwardly from a lower surface, the lower surface extending partially into the first GaN layer, each of the plurality of mesas including the second GaN layer and a portion of the first GaN layer; forming a second plurality of vias in the semiconductor body and the insulating buffer layer at the lower surface of the plurality of mesas, the second plurality of vias being filled with a second via metal; forming a first metal layer on an upper surface of the plurality of mesas for forming a Schottky junction with the second GaN layer; forming a second metal layer on the lower surface of the semiconductor body between the plurality of mesas for forming ohmic contacts to the first GaN layer, the second metal layer being electrically connected to the conducting substrate through the second plurality of vias; forming an insulating layer over the first and second metal layers;-21-forming a first plurality of vias in the insulating layer to form openings to the first metal layer, the first plurality of vias being filled with a first via metal; forming a first metal pad overlying the insulating layer and in electrical contact with the first plurality of vias, the first metal pad forming an anode electrode; and forming a second metal pad on a second surface of the conducting substrate, the second surface being opposite the first surface, the second metal pad forming a cathode electrode.
The method of claim 18, wherein the first conductivity type comprises N-type conductivity.
The method of claim 18, wherein forming a plurality of mesas in the semiconductor body comprises forming the plurality of mesas as separated parallel elongated linear regions of the second GaN layer and the portion of the first GaN layer, the linear regions being interdigitated with the ohmic contacts formed on the lower surface of the semiconductor body.
The method of claim 18, wherein forming a plurality of mesas in the semiconductor body comprises forming the plurality of mesas as separated concentric ring-shaped regions of the second GaN layer and the portion of the first GaN layer, the concentric regions being interdigitated with the ohmic contacts in the lower surface of the semiconductor body.
The method of claim 18, wherein forming a second plurality of vias in the semiconductor body and the insulating buffer layer is carried out before forming a plurality of mesas, the second plurality of vias being formed at a location in the semiconductor body where the lower surface of the plurality of mesas is to be formed.
The method of claim 18, wherein the first metal group of Ni, Pt, Au, Co, Pd, Cr, Rh, Re, PtSi, V,
The method of claim 18, wherein the via metal W, TiW, Al, Au, Cu, Ti, Ag and AlCuSi. layer comprises a metal selected from the W, WSi and NiSi. comprises a metal selected from the group of
Layer stacks claimed or described, ordered top of device to substrate.
GaN Schottky diode (lateral cathode, insulating substrate)
Materials described outside the worked examples.
GaN (first layer, heavily doped)
GaN
ohmic contact metal (Al, AlSi, Ti, TiSi, Mo, MoSi)
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,383,499Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 duplicates
Figure 3A of U.S. Patent No. 7,084,475 B 1 and illustrates a GaN semiconductor device.
Figure 2 duplicates
Figure 6A of U.S. Patent No. 7,084,475 B 1 and illustrates a GaN semiconductor device.
Figure 3 is a perspective view of a GaN Schottky diode according to a first embodiment of the present invention.
Figure 4 is a top view of the GaN Schottky diode of
Figure 5 is a top view of the GaN Schottky diode according to a second embodiment of the present invention.
Figure 6 is a top view of the GaN Schottky diode according to a third embodiment of the present invention.
Figure 7 is a flow chart illustrating the fabrication process for fabricating the GaN Schottky diode of
Figure 8 is a cross-sectional view of a GaN Schottky diode according to an alternate embodiment of the present invention.
Figure 9 is a flow chart illustrating the fabrication process for fabricating the GaN Schottky diode of
Figure 10 is a flow chart illustrating the fabrication process for fabricating the GaN Schottky diode of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for forming a gallium nitride based semiconductor diode, comprising: providing a substrate; forming a semiconductor body comprising a first GaN layer of a first conductivity type formed on the substrate and a second GaN layer of the first conductivity type on the first GaN layer, the second GaN layer being more lightly doped than the first GaN layer; forming a plurality of mesas in the semiconductor body projecting upwardly from a lower surface, the lower surface extending partially into the first GaN layer, each of the plurality of mesas including the second GaN layer and a portion of the first GaN layer; forming a first metal layer on an upper surface of the plurality of mesas for forming a Schottky junction with the second GaN layer; forming a second metal layer on the lower surface between the plurality of mesas to form ohmic contacts to the first GaN layer; forming an insulating layer over the first and second metal layers; forming a first plurality of vias in the insulating layer to form openings to the first metal layer, the first plurality of vias being filled with a via metal; forming a second plurality of vias in the insulating layer between the plurality of mesas to form openings to the second metal layer, the second plurality of vias being filled with the via metal;-17-forming a first metal pad overlying the insulating layer and in electrical contact with the first plurality of vias, the first metal pad forming an anode electrode; and forming a second metal pad formed overlying the insulating layer and in electrical contact with the second plurality of vias, the second metal pad forming a cathode electrode.
The method of claim 1, wherein providing a substrate comprises providing an insulating substrate.
The method of claim 1, wherein providing a substrate comprises providing a conducting substrate and an overlying buffer layer.
The method of claim 1, wherein the first conductivity type comprises N-type conductivity.
The method of claim 1, wherein forming a plurality of mesas in the semiconductor body comprises forming the plurality of mesas as separated parallel elongated linear regions of the second GaN layer and the portion of the first GaN layer, the linear regions being interdigitated with the ohmic contacts in the lower surface.
The method of claim 1, wherein forming a plurality of mesas in the semiconductor body comprises forming the plurality of mesas as separated concentric ring-shaped regions of the second GaN layer and the portion of the first GaN layer, the concentric regions being interdigitated with the ohmic contacts in the lower surface of the semiconductor body.
The method of claim 1, wherein the first metal layer comprises a metal selected from the group of Ni, Pt, Au, Co, Pd, Cr, Rh, Re, PtSi, V, W, WSi and NiSi.
The method of claim 1, wherein the second metal layer comprises a metal selected from the group of Al, AlSi, Ti, TiSi, Mo, and MoSi.
The method of claim 1, wherein the via metal comprises a metal selected from the group of W, TiW, Al, Au, Cu, Ti, Ag and AlCuSi.
The method of claim 1, wherein the third metal layer comprises a metal selected from the group of Al, AlCuSi, Au, Ag, Cu and Ti.
- 20-18. A method for forming a gallium nitride based semiconductor diode, comprising: providing a conducting substrate; forming an insulating buffer layer on a first surface of the conducting substrate; forming a semiconductor body comprising a first GaN layer of a first conductivity type formed on the insulating buffer layer and a second GaN layer of the first conductivity type formed on the first GaN layer, the second GaN layer being more lightly doped than the first GaN layer; forming a plurality of mesas projecting upwardly from a lower surface, the lower surface extending partially into the first GaN layer, each of the plurality of mesas including the second GaN layer and a portion of the first GaN layer; forming a second plurality of vias in the semiconductor body and the insulating buffer layer at the lower surface of the plurality of mesas, the second plurality of vias being filled with a second via metal; forming a first metal layer on an upper surface of the plurality of mesas for forming a Schottky junction with the second GaN layer; forming a second metal layer on the lower surface of the semiconductor body between the plurality of mesas for forming ohmic contacts to the first GaN layer, the second metal layer being electrically connected to the conducting substrate through the second plurality of vias; forming an insulating layer over the first and second metal layers;-21-forming a first plurality of vias in the insulating layer to form openings to the first metal layer, the first plurality of vias being filled with a first via metal; forming a first metal pad overlying the insulating layer and in electrical contact with the first plurality of vias, the first metal pad forming an anode electrode; and forming a second metal pad on a second surface of the conducting substrate, the second surface being opposite the first surface, the second metal pad forming a cathode electrode.
The method of claim 18, wherein the first conductivity type comprises N-type conductivity.
The method of claim 18, wherein forming a plurality of mesas in the semiconductor body comprises forming the plurality of mesas as separated parallel elongated linear regions of the second GaN layer and the portion of the first GaN layer, the linear regions being interdigitated with the ohmic contacts formed on the lower surface of the semiconductor body.
The method of claim 18, wherein forming a plurality of mesas in the semiconductor body comprises forming the plurality of mesas as separated concentric ring-shaped regions of the second GaN layer and the portion of the first GaN layer, the concentric regions being interdigitated with the ohmic contacts in the lower surface of the semiconductor body.
The method of claim 18, wherein forming a second plurality of vias in the semiconductor body and the insulating buffer layer is carried out before forming a plurality of mesas, the second plurality of vias being formed at a location in the semiconductor body where the lower surface of the plurality of mesas is to be formed.
The method of claim 18, wherein the first metal group of Ni, Pt, Au, Co, Pd, Cr, Rh, Re, PtSi, V,
The method of claim 18, wherein the via metal W, TiW, Al, Au, Cu, Ti, Ag and AlCuSi. layer comprises a metal selected from the W, WSi and NiSi. comprises a metal selected from the group of
Layer stacks claimed or described, ordered top of device to substrate.
GaN Schottky diode (lateral cathode, insulating substrate)
Materials described outside the worked examples.
GaN (first layer, heavily doped)
GaN
ohmic contact metal (Al, AlSi, Ti, TiSi, Mo, MoSi)
Related documents with shared materials, methods, properties, or citations.
GaN Schottky diode (vertical cathode, conducting substrate)
Schottky contact metal (Ni, Pt, Au, Co, Pd, Cr, Rh, Re, PtSi, V, W, WSi, NiSi)
via metal (W, TiW, Al, Au, Cu, Ti, Ag, AlCuSi)
insulating substrate
third metal layer (Al, AlCuSi, Au, Ag, Cu, Ti)
insulating buffer layer
insulating substrate (sapphire, ZnO, AlN, GaN, semi-insulating SiC, glass)
insulating layer (SiOx, SiNx, Al₂O3, AlN, polymer, spin on glass)
GaN-BASED SCHOTTKY DIODE HAVING PARTIALLY RECESSED ANODE
GaN Schottky diode (vertical cathode, conducting substrate)
Schottky contact metal (Ni, Pt, Au, Co, Pd, Cr, Rh, Re, PtSi, V, W, WSi, NiSi)
via metal (W, TiW, Al, Au, Cu, Ti, Ag, AlCuSi)
insulating substrate
third metal layer (Al, AlCuSi, Au, Ag, Cu, Ti)
insulating buffer layer
insulating substrate (sapphire, ZnO, AlN, GaN, semi-insulating SiC, glass)
insulating layer (SiOx, SiNx, Al₂O3, AlN, polymer, spin on glass)
GaN-BASED SCHOTTKY DIODE HAVING PARTIALLY RECESSED ANODE
GaN Schottky diode (vertical cathode, conducting substrate)
Schottky contact metal (Ni, Pt, Au, Co, Pd, Cr, Rh, Re, PtSi, V, W, WSi, NiSi)
via metal (W, TiW, Al, Au, Cu, Ti, Ag, AlCuSi)
insulating substrate
third metal layer (Al, AlCuSi, Au, Ag, Cu, Ti)
insulating buffer layer
insulating substrate (sapphire, ZnO, AlN, GaN, semi-insulating SiC, glass)
insulating layer (SiOx, SiNx, Al₂O3, AlN, polymer, spin on glass)
GaN-BASED SCHOTTKY DIODE HAVING PARTIALLY RECESSED ANODE
GaN Schottky diode (vertical cathode, conducting substrate)
Schottky contact metal (Ni, Pt, Au, Co, Pd, Cr, Rh, Re, PtSi, V, W, WSi, NiSi)
via metal (W, TiW, Al, Au, Cu, Ti, Ag, AlCuSi)
insulating substrate
third metal layer (Al, AlCuSi, Au, Ag, Cu, Ti)
insulating buffer layer
insulating substrate (sapphire, ZnO, AlN, GaN, semi-insulating SiC, glass)
insulating layer (SiOx, SiNx, Al₂O3, AlN, polymer, spin on glass)
GaN-BASED SCHOTTKY DIODE HAVING PARTIALLY RECESSED ANODE