Patent
US 12,084,790 B2LOW ETCH PIT DENSITY 6 INCH SEMI-INSULATING GALLIUM ARSENIDE WAFERS
Rajaram Shetty, Weiguo Liu, Morris Young
AXT, Inc., Fremont, CA (US)·Sep. 10, 2024·US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 12,084,790 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a diagram illustrating a vertical gradient freeze reactor, in accordance with an example embodiment of the disclosure.
FIGS. 2A and 2B illustrates etch pit density results for 6" gallium arsenide wafers manufactured in accordance with an 55 embodiment of the disclosure.
FIG. 3 illustrates a flow chart for fabricating gallium arsenide wafers using a vertical gradient freeze process, in accordance with an example embodiment of …
FIG. 4 illustrates devices fabricated on low etch pit 60 density 6 inch semi-insulating gallium arsenide wafers, in accordance with an example embodiment of …
FIG. 25 1. This process results in 6 inch semi-insulating GaAs substrates with less than 1000 cm2 etch pit density. This process may also be used to fabricate …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for forming single crystal gallium arsenide substrates, the method comprising: sealing charge material comprising polycrystalline gal-lium arsenide, a gallium arsenide seed crystal, B₂O₃ encapsulant, and carbon in a crucible; sealing the crucible in a quartz ampoule; performing a vertical gradient freeze crystal growth pro-cess by heating the ampoule using a multi-zone heating system to progressively melt the charge material until a portion of the seed crystal is melted; starting growth from the partially melted seed by imple-menting a controlled cooling of the multi-zone heating system at a rate of 0.1 to 2 degree C./hour; applying a temperature gradient of between 0.2 to 5 C/cm at a melt-crystal interface; and maintaining a ratio of 1.0 to 4 between a temperature gradient above the melt-crystal interface to a tempera-ture gradient below the melt-crystal interface in the multi-zone heating system to form a solidified gallium arsenide crystal.
The method according to claim 1, comprising control-ling the cooling of the multi-zone heating system at a rate of 0.1-2 C/hour to make a uniform temperature with axial gradients of 0.2 to 2 degree C./cm.
The method according to claim 1, wherein the solidified gallium arsenide crystal has a diameter of 6 inches or more.
The method according to claim 1, comprising further forming a wafer from the solidified gallium arsenide crystal.
The method according to claim, 1, comprising evacu-ating the crucible before sealing it into the quartz ampoule.
A method for forming single crystal gallium arsenide substrates, the method comprising: sealing charge material comprising polycrystalline gal-lium arsenide, a gallium arsenide seed crystal, B₂O₃ encapsulant, and carbon in a crucible; sealing the crucible in a quartz ampoule; performing a vertical gradient freeze crystal growth pro-cess by heating the ampoule using a multi-zone heating system to melt the charge material until a portion of the seed crystal is melted; starting growth from the partially melted seed by imple-menting a controlled cooling of the multi-zone heating system at a rate of 1 to 2 degrees C./hour; applying a temperature gradient of between 0.5 to 2.5 C/cm at a melt-crystal interface; and forming a solidified gallium arsenide crystal with a diam-eter of 6 inches or more.
The method according to claim 15, comprising further shaping the solidified gallium arsenide crystal as a rounded ingot.
The method according to claim 15, comprising further Slicing the rounded ingot into wafers.
The method according to claim 15, comprising further maintaining a ratio of 1.0 to 4 between a temperature gradient above the melt-crystal interface to a temperature gradient below the melt-crystal interface in the multi-zone heating system to form the solidified gallium arsenide crys-tal.
The method according to claim 15, comprising further cooling the solidified gallium arsenide crystal by 300 C at a ramp rate of 5 to 15 degrees C./hour.
The method according to claim 15, comprising further evacuating the crucible before sealing it into the quartz ampoule. ∗ ∗ ∗ ∗ ∗
Embodiments described in the patent, grouped by the materials and process steps they use.
4 materials1 process step
A VGF process for 6-inch semi-insulating GaAs single crystal growth. Polycrystalline GaAs charge with B₂O₃ encapsulant and carbon is loaded in a PBN crucible sealed in a quartz ampoule. Crystal growth uses axial gradients of 0.5–2.5 C/cm at the melt/crystal interface with growth rates of 1–3 mm/h, maintaining a ratio of 1.3–3.0 between the temperature gradient below to above the solid-liquid interface. Post-solidification cooling uses Step 1 at 0.1–0.8 C/hour to near-isothermal, Step 2 at 5–15 C/hour to 200°C below solidification, Step 3 at 30 C/hour to 600°C, and final cooling at 50 C/hour to room temperature. Result: 6-inch GaAs wafers with average EPD of 427/cm2 (seed end) and 558/cm2 (tail end), resistivity >1×10⁷ ohm-cm, carrier concentration 1×10⁶–1×10⁷ cm⁻³, carrier mobility ~3×10³ cm2/V-sec, IR absorption <2 cm⁻¹ at 1050 nm and <4 cm⁻¹ at 940 nm.
Layer stacks claimed or described, ordered top of device to substrate.
semi-insulating GaAs wafer
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 25 1. This process results in 6 inch semi-insulating GaAs substrates with less than 1000 cm2 etch pit density. This process may also be used to fabricate …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
EPD average seed end | 427 | GaAs |
EPD maximum seed end |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 2
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,084,790 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a diagram illustrating a vertical gradient freeze reactor, in accordance with an example embodiment of the disclosure.
FIGS. 2A and 2B illustrates etch pit density results for 6" gallium arsenide wafers manufactured in accordance with an 55 embodiment of the disclosure.
FIG. 3 illustrates a flow chart for fabricating gallium arsenide wafers using a vertical gradient freeze process, in accordance with an example embodiment of …
FIG. 4 illustrates devices fabricated on low etch pit 60 density 6 inch semi-insulating gallium arsenide wafers, in accordance with an example embodiment of …
FIG. 25 1. This process results in 6 inch semi-insulating GaAs substrates with less than 1000 cm2 etch pit density. This process may also be used to fabricate …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for forming single crystal gallium arsenide substrates, the method comprising: sealing charge material comprising polycrystalline gal-lium arsenide, a gallium arsenide seed crystal, B₂O₃ encapsulant, and carbon in a crucible; sealing the crucible in a quartz ampoule; performing a vertical gradient freeze crystal growth pro-cess by heating the ampoule using a multi-zone heating system to progressively melt the charge material until a portion of the seed crystal is melted; starting growth from the partially melted seed by imple-menting a controlled cooling of the multi-zone heating system at a rate of 0.1 to 2 degree C./hour; applying a temperature gradient of between 0.2 to 5 C/cm at a melt-crystal interface; and maintaining a ratio of 1.0 to 4 between a temperature gradient above the melt-crystal interface to a tempera-ture gradient below the melt-crystal interface in the multi-zone heating system to form a solidified gallium arsenide crystal.
The method according to claim 1, comprising control-ling the cooling of the multi-zone heating system at a rate of 0.1-2 C/hour to make a uniform temperature with axial gradients of 0.2 to 2 degree C./cm.
The method according to claim 1, wherein the solidified gallium arsenide crystal has a diameter of 6 inches or more.
The method according to claim 1, comprising further forming a wafer from the solidified gallium arsenide crystal.
The method according to claim, 1, comprising evacu-ating the crucible before sealing it into the quartz ampoule.
A method for forming single crystal gallium arsenide substrates, the method comprising: sealing charge material comprising polycrystalline gal-lium arsenide, a gallium arsenide seed crystal, B₂O₃ encapsulant, and carbon in a crucible; sealing the crucible in a quartz ampoule; performing a vertical gradient freeze crystal growth pro-cess by heating the ampoule using a multi-zone heating system to melt the charge material until a portion of the seed crystal is melted; starting growth from the partially melted seed by imple-menting a controlled cooling of the multi-zone heating system at a rate of 1 to 2 degrees C./hour; applying a temperature gradient of between 0.5 to 2.5 C/cm at a melt-crystal interface; and forming a solidified gallium arsenide crystal with a diam-eter of 6 inches or more.
The method according to claim 15, comprising further shaping the solidified gallium arsenide crystal as a rounded ingot.
The method according to claim 15, comprising further Slicing the rounded ingot into wafers.
The method according to claim 15, comprising further maintaining a ratio of 1.0 to 4 between a temperature gradient above the melt-crystal interface to a temperature gradient below the melt-crystal interface in the multi-zone heating system to form the solidified gallium arsenide crys-tal.
The method according to claim 15, comprising further cooling the solidified gallium arsenide crystal by 300 C at a ramp rate of 5 to 15 degrees C./hour.
The method according to claim 15, comprising further evacuating the crucible before sealing it into the quartz ampoule. ∗ ∗ ∗ ∗ ∗
Embodiments described in the patent, grouped by the materials and process steps they use.
4 materials1 process step
A VGF process for 6-inch semi-insulating GaAs single crystal growth. Polycrystalline GaAs charge with B₂O₃ encapsulant and carbon is loaded in a PBN crucible sealed in a quartz ampoule. Crystal growth uses axial gradients of 0.5–2.5 C/cm at the melt/crystal interface with growth rates of 1–3 mm/h, maintaining a ratio of 1.3–3.0 between the temperature gradient below to above the solid-liquid interface. Post-solidification cooling uses Step 1 at 0.1–0.8 C/hour to near-isothermal, Step 2 at 5–15 C/hour to 200°C below solidification, Step 3 at 30 C/hour to 600°C, and final cooling at 50 C/hour to room temperature. Result: 6-inch GaAs wafers with average EPD of 427/cm2 (seed end) and 558/cm2 (tail end), resistivity >1×10⁷ ohm-cm, carrier concentration 1×10⁶–1×10⁷ cm⁻³, carrier mobility ~3×10³ cm2/V-sec, IR absorption <2 cm⁻¹ at 1050 nm and <4 cm⁻¹ at 940 nm.
Layer stacks claimed or described, ordered top of device to substrate.
semi-insulating GaAs wafer
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 25 1. This process results in 6 inch semi-insulating GaAs substrates with less than 1000 cm2 etch pit density. This process may also be used to fabricate …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
EPD average seed end | 427 | GaAs |
EPD maximum seed end |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 2
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,084,790 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a diagram illustrating a vertical gradient freeze reactor, in accordance with an example embodiment of the disclosure.
FIGS. 2A and 2B illustrates etch pit density results for 6" gallium arsenide wafers manufactured in accordance with an 55 embodiment of the disclosure.
FIG. 3 illustrates a flow chart for fabricating gallium arsenide wafers using a vertical gradient freeze process, in accordance with an example embodiment of …
FIG. 4 illustrates devices fabricated on low etch pit 60 density 6 inch semi-insulating gallium arsenide wafers, in accordance with an example embodiment of …
FIG. 25 1. This process results in 6 inch semi-insulating GaAs substrates with less than 1000 cm2 etch pit density. This process may also be used to fabricate …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for forming single crystal gallium arsenide substrates, the method comprising: sealing charge material comprising polycrystalline gal-lium arsenide, a gallium arsenide seed crystal, B₂O₃ encapsulant, and carbon in a crucible; sealing the crucible in a quartz ampoule; performing a vertical gradient freeze crystal growth pro-cess by heating the ampoule using a multi-zone heating system to progressively melt the charge material until a portion of the seed crystal is melted; starting growth from the partially melted seed by imple-menting a controlled cooling of the multi-zone heating system at a rate of 0.1 to 2 degree C./hour; applying a temperature gradient of between 0.2 to 5 C/cm at a melt-crystal interface; and maintaining a ratio of 1.0 to 4 between a temperature gradient above the melt-crystal interface to a tempera-ture gradient below the melt-crystal interface in the multi-zone heating system to form a solidified gallium arsenide crystal.
The method according to claim 1, comprising control-ling the cooling of the multi-zone heating system at a rate of 0.1-2 C/hour to make a uniform temperature with axial gradients of 0.2 to 2 degree C./cm.
The method according to claim 1, wherein the solidified gallium arsenide crystal has a diameter of 6 inches or more.
The method according to claim 1, comprising further forming a wafer from the solidified gallium arsenide crystal.
The method according to claim, 1, comprising evacu-ating the crucible before sealing it into the quartz ampoule.
A method for forming single crystal gallium arsenide substrates, the method comprising: sealing charge material comprising polycrystalline gal-lium arsenide, a gallium arsenide seed crystal, B₂O₃ encapsulant, and carbon in a crucible; sealing the crucible in a quartz ampoule; performing a vertical gradient freeze crystal growth pro-cess by heating the ampoule using a multi-zone heating system to melt the charge material until a portion of the seed crystal is melted; starting growth from the partially melted seed by imple-menting a controlled cooling of the multi-zone heating system at a rate of 1 to 2 degrees C./hour; applying a temperature gradient of between 0.5 to 2.5 C/cm at a melt-crystal interface; and forming a solidified gallium arsenide crystal with a diam-eter of 6 inches or more.
The method according to claim 15, comprising further shaping the solidified gallium arsenide crystal as a rounded ingot.
The method according to claim 15, comprising further Slicing the rounded ingot into wafers.
The method according to claim 15, comprising further maintaining a ratio of 1.0 to 4 between a temperature gradient above the melt-crystal interface to a temperature gradient below the melt-crystal interface in the multi-zone heating system to form the solidified gallium arsenide crys-tal.
The method according to claim 15, comprising further cooling the solidified gallium arsenide crystal by 300 C at a ramp rate of 5 to 15 degrees C./hour.
The method according to claim 15, comprising further evacuating the crucible before sealing it into the quartz ampoule. ∗ ∗ ∗ ∗ ∗
Embodiments described in the patent, grouped by the materials and process steps they use.
4 materials1 process step
A VGF process for 6-inch semi-insulating GaAs single crystal growth. Polycrystalline GaAs charge with B₂O₃ encapsulant and carbon is loaded in a PBN crucible sealed in a quartz ampoule. Crystal growth uses axial gradients of 0.5–2.5 C/cm at the melt/crystal interface with growth rates of 1–3 mm/h, maintaining a ratio of 1.3–3.0 between the temperature gradient below to above the solid-liquid interface. Post-solidification cooling uses Step 1 at 0.1–0.8 C/hour to near-isothermal, Step 2 at 5–15 C/hour to 200°C below solidification, Step 3 at 30 C/hour to 600°C, and final cooling at 50 C/hour to room temperature. Result: 6-inch GaAs wafers with average EPD of 427/cm2 (seed end) and 558/cm2 (tail end), resistivity >1×10⁷ ohm-cm, carrier concentration 1×10⁶–1×10⁷ cm⁻³, carrier mobility ~3×10³ cm2/V-sec, IR absorption <2 cm⁻¹ at 1050 nm and <4 cm⁻¹ at 940 nm.
Layer stacks claimed or described, ordered top of device to substrate.
semi-insulating GaAs wafer
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 25 1. This process results in 6 inch semi-insulating GaAs substrates with less than 1000 cm2 etch pit density. This process may also be used to fabricate …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
EPD average seed end | 427 | GaAs |
EPD maximum seed end |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 2
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,084,790 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a diagram illustrating a vertical gradient freeze reactor, in accordance with an example embodiment of the disclosure.
FIGS. 2A and 2B illustrates etch pit density results for 6" gallium arsenide wafers manufactured in accordance with an 55 embodiment of the disclosure.
FIG. 3 illustrates a flow chart for fabricating gallium arsenide wafers using a vertical gradient freeze process, in accordance with an example embodiment of …
FIG. 4 illustrates devices fabricated on low etch pit 60 density 6 inch semi-insulating gallium arsenide wafers, in accordance with an example embodiment of …
FIG. 25 1. This process results in 6 inch semi-insulating GaAs substrates with less than 1000 cm2 etch pit density. This process may also be used to fabricate …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for forming single crystal gallium arsenide substrates, the method comprising: sealing charge material comprising polycrystalline gal-lium arsenide, a gallium arsenide seed crystal, B₂O₃ encapsulant, and carbon in a crucible; sealing the crucible in a quartz ampoule; performing a vertical gradient freeze crystal growth pro-cess by heating the ampoule using a multi-zone heating system to progressively melt the charge material until a portion of the seed crystal is melted; starting growth from the partially melted seed by imple-menting a controlled cooling of the multi-zone heating system at a rate of 0.1 to 2 degree C./hour; applying a temperature gradient of between 0.2 to 5 C/cm at a melt-crystal interface; and maintaining a ratio of 1.0 to 4 between a temperature gradient above the melt-crystal interface to a tempera-ture gradient below the melt-crystal interface in the multi-zone heating system to form a solidified gallium arsenide crystal.
The method according to claim 1, comprising control-ling the cooling of the multi-zone heating system at a rate of 0.1-2 C/hour to make a uniform temperature with axial gradients of 0.2 to 2 degree C./cm.
The method according to claim 1, wherein the solidified gallium arsenide crystal has a diameter of 6 inches or more.
The method according to claim 1, comprising further forming a wafer from the solidified gallium arsenide crystal.
The method according to claim, 1, comprising evacu-ating the crucible before sealing it into the quartz ampoule.
A method for forming single crystal gallium arsenide substrates, the method comprising: sealing charge material comprising polycrystalline gal-lium arsenide, a gallium arsenide seed crystal, B₂O₃ encapsulant, and carbon in a crucible; sealing the crucible in a quartz ampoule; performing a vertical gradient freeze crystal growth pro-cess by heating the ampoule using a multi-zone heating system to melt the charge material until a portion of the seed crystal is melted; starting growth from the partially melted seed by imple-menting a controlled cooling of the multi-zone heating system at a rate of 1 to 2 degrees C./hour; applying a temperature gradient of between 0.5 to 2.5 C/cm at a melt-crystal interface; and forming a solidified gallium arsenide crystal with a diam-eter of 6 inches or more.
The method according to claim 15, comprising further shaping the solidified gallium arsenide crystal as a rounded ingot.
The method according to claim 15, comprising further Slicing the rounded ingot into wafers.
The method according to claim 15, comprising further maintaining a ratio of 1.0 to 4 between a temperature gradient above the melt-crystal interface to a temperature gradient below the melt-crystal interface in the multi-zone heating system to form the solidified gallium arsenide crys-tal.
The method according to claim 15, comprising further cooling the solidified gallium arsenide crystal by 300 C at a ramp rate of 5 to 15 degrees C./hour.
The method according to claim 15, comprising further evacuating the crucible before sealing it into the quartz ampoule. ∗ ∗ ∗ ∗ ∗
Embodiments described in the patent, grouped by the materials and process steps they use.
4 materials1 process step
A VGF process for 6-inch semi-insulating GaAs single crystal growth. Polycrystalline GaAs charge with B₂O₃ encapsulant and carbon is loaded in a PBN crucible sealed in a quartz ampoule. Crystal growth uses axial gradients of 0.5–2.5 C/cm at the melt/crystal interface with growth rates of 1–3 mm/h, maintaining a ratio of 1.3–3.0 between the temperature gradient below to above the solid-liquid interface. Post-solidification cooling uses Step 1 at 0.1–0.8 C/hour to near-isothermal, Step 2 at 5–15 C/hour to 200°C below solidification, Step 3 at 30 C/hour to 600°C, and final cooling at 50 C/hour to room temperature. Result: 6-inch GaAs wafers with average EPD of 427/cm2 (seed end) and 558/cm2 (tail end), resistivity >1×10⁷ ohm-cm, carrier concentration 1×10⁶–1×10⁷ cm⁻³, carrier mobility ~3×10³ cm2/V-sec, IR absorption <2 cm⁻¹ at 1050 nm and <4 cm⁻¹ at 940 nm.
Layer stacks claimed or described, ordered top of device to substrate.
semi-insulating GaAs wafer
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 25 1. This process results in 6 inch semi-insulating GaAs substrates with less than 1000 cm2 etch pit density. This process may also be used to fabricate …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
EPD average seed end | 427 | GaAs |
EPD maximum seed end |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 2
Related documents with shared materials, methods, properties, or citations.
| 1500 |
GaAs |
EPD average tail end | 558 | GaAs |
EPD maximum tail end | 2083 | GaAs |
semi-insulating resistivity | >1e7 | GaAs |
carrier concentration range | 1e6 to 1e7 | GaAs |
carrier mobility | ~3000 | GaAs |
IR absorption at 1050 nm | <2 | GaAs |
IR absorption at 940 nm | <4 | GaAs |
optical absorption claim limit at 940 nm (6 cm^-1) | <=6 | GaAs |
optical absorption claim limit at 940 nm (4 cm^-1) | <=4 | GaAs |
optical absorption claim limit at 940 nm (3 cm^-1) | <=3 | GaAs |
carrier mobility claim limit | >=3000 | GaAs |
carrier concentration claim limit | <=1.1e7 | GaAs |
Thickness | 1–3 mm | — |
Thickness | 3000–4800 cm | — |
Thickness | ≤ 600 cm | — |
Thickness | ≤ 2 cm | — |
Thickness | ≤ 4 cm | — |
Thickness | ≤ 1 cm | — |
Thickness | ≤ 6 cm | — |
Thickness | ≤ 3 cm | — |
| 1500 |
GaAs |
EPD average tail end | 558 | GaAs |
EPD maximum tail end | 2083 | GaAs |
semi-insulating resistivity | >1e7 | GaAs |
carrier concentration range | 1e6 to 1e7 | GaAs |
carrier mobility | ~3000 | GaAs |
IR absorption at 1050 nm | <2 | GaAs |
IR absorption at 940 nm | <4 | GaAs |
optical absorption claim limit at 940 nm (6 cm^-1) | <=6 | GaAs |
optical absorption claim limit at 940 nm (4 cm^-1) | <=4 | GaAs |
optical absorption claim limit at 940 nm (3 cm^-1) | <=3 | GaAs |
carrier mobility claim limit | >=3000 | GaAs |
carrier concentration claim limit | <=1.1e7 | GaAs |
Thickness | 1–3 mm | — |
Thickness | 3000–4800 cm | — |
Thickness | ≤ 600 cm | — |
Thickness | ≤ 2 cm | — |
Thickness | ≤ 4 cm | — |
Thickness | ≤ 1 cm | — |
Thickness | ≤ 6 cm | — |
Thickness | ≤ 3 cm | — |
| 1500 |
GaAs |
EPD average tail end | 558 | GaAs |
EPD maximum tail end | 2083 | GaAs |
semi-insulating resistivity | >1e7 | GaAs |
carrier concentration range | 1e6 to 1e7 | GaAs |
carrier mobility | ~3000 | GaAs |
IR absorption at 1050 nm | <2 | GaAs |
IR absorption at 940 nm | <4 | GaAs |
optical absorption claim limit at 940 nm (6 cm^-1) | <=6 | GaAs |
optical absorption claim limit at 940 nm (4 cm^-1) | <=4 | GaAs |
optical absorption claim limit at 940 nm (3 cm^-1) | <=3 | GaAs |
carrier mobility claim limit | >=3000 | GaAs |
carrier concentration claim limit | <=1.1e7 | GaAs |
Thickness | 1–3 mm | — |
Thickness | 3000–4800 cm | — |
Thickness | ≤ 600 cm | — |
Thickness | ≤ 2 cm | — |
Thickness | ≤ 4 cm | — |
Thickness | ≤ 1 cm | — |
Thickness | ≤ 6 cm | — |
Thickness | ≤ 3 cm | — |
| 1500 |
GaAs |
EPD average tail end | 558 | GaAs |
EPD maximum tail end | 2083 | GaAs |
semi-insulating resistivity | >1e7 | GaAs |
carrier concentration range | 1e6 to 1e7 | GaAs |
carrier mobility | ~3000 | GaAs |
IR absorption at 1050 nm | <2 | GaAs |
IR absorption at 940 nm | <4 | GaAs |
optical absorption claim limit at 940 nm (6 cm^-1) | <=6 | GaAs |
optical absorption claim limit at 940 nm (4 cm^-1) | <=4 | GaAs |
optical absorption claim limit at 940 nm (3 cm^-1) | <=3 | GaAs |
carrier mobility claim limit | >=3000 | GaAs |
carrier concentration claim limit | <=1.1e7 | GaAs |
Thickness | 1–3 mm | — |
Thickness | 3000–4800 cm | — |
Thickness | ≤ 600 cm | — |
Thickness | ≤ 2 cm | — |
Thickness | ≤ 4 cm | — |
Thickness | ≤ 1 cm | — |
Thickness | ≤ 6 cm | — |
Thickness | ≤ 3 cm | — |