Patent
US 8,546,884HIGH VALUE RESISTORS IN GALLIUM ARSENIDE
Michael L. Frank
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 8,546,884Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 illustrates a prior art GaAs field effect transistor.
Figure 2 illustrates a plan view of a prior art GaAs resistor.
Figure 3 illustrates a space charge region for a GaAs FET.
Figure 4 illustrates a plan view of the resistor of the present invention.
Figure 5 illustrates a cross-sectional view of the resistor shown in
Figure 6 illustrates another embodiment of the resistor of the present invention.
Figure 7 illustrates another embodiment of the resistor of the present invention. DETAILS OF THE INVENTION [0013] When metal is patterned onto a semiconductor, a space charge region is formed. In a GaAs FET, this space charge region reduces the conductivity of the channel. In a depletion mode …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
Amendments to the Claims: A listing of the entire set of pending claims (including amendments to the claims, if any) is submitted herewith per 37 C FR 1.121. This listing of claims will replace all prior versions, and listings, of claims in the application.
2.
A device comprising: a resistor including: a semi-insulating substrate; an active layer, positioned over the semi-insulating substrate, including an epitaxial layer des i gned for enhancement mode operation; a first channel region positioned over the active layer; a first gate metal covering a portion of the first channel region; ohmic contact material positioned at opposing ends of the active layer; a second gate metal covering a portion of the first channel region; and metal positioned over the opposing ends of the active layer to form input/output pads.
A device comprising: a resistor including: a semi-insulating substrate; an active layer, positioned over the semi- insulating substrate, including an epitaxial layer designed for enhancement mode operation; a first channel region positioned over the active layer;-a first gate metal covering a portion of the first channel region; ohmic contact material positioned at opposing ends of the active layer; a second channel region covering a portion of the active layer; a second gate metal covering a portion of the second channel region; and metal positioned over the opposing ends of the active layer to form input/output pads.
. A device comprising: a resistor including: a semi-insulating substrate; an active layer, positioned over the semi- insulating substrate, including an epitaxial laye r designed for enhancement mode operation; a first channel region having a serpentine shape, positioned over the active l ayer; a first gate metal covering a portion of the first channel region; 4 PAGE 4111 2 RCVD AT 1 17112006 7:0 0:42 PM [Easte rn Standard Time]* SVR:USPT₀EFXRF-628' DNIS:27383 00'* CSID:610 375 8 380 DURAT IO N (mm ~ ss): 01.46 11/27/2006 N ON 19:01 FAx 610 3758380 I 005/0 11 Appl i cat i on Serial Number 10/283,971 Response to Of fi ce A c tion Dated S e ptember 25. 2006 ohmic contact layer; a second gate metal covering a portion of ove r the opposing ends of the active layer to form material positioned at opposing ends of the active the first channel r egion; and metal positioned input/output pads.
Layer stacks claimed or described, ordered top of device to substrate.
high value resistor with two gate metals on first channel region
Materials described outside the worked examples.
semi-insulating substrate
epitaxial active layer for enhancement mode operation
gate metal
Measurements and analyses referenced in the patent, with their drawing references.
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,546,884Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 illustrates a prior art GaAs field effect transistor.
Figure 2 illustrates a plan view of a prior art GaAs resistor.
Figure 3 illustrates a space charge region for a GaAs FET.
Figure 4 illustrates a plan view of the resistor of the present invention.
Figure 5 illustrates a cross-sectional view of the resistor shown in
Figure 6 illustrates another embodiment of the resistor of the present invention.
Figure 7 illustrates another embodiment of the resistor of the present invention. DETAILS OF THE INVENTION [0013] When metal is patterned onto a semiconductor, a space charge region is formed. In a GaAs FET, this space charge region reduces the conductivity of the channel. In a depletion mode …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
Amendments to the Claims: A listing of the entire set of pending claims (including amendments to the claims, if any) is submitted herewith per 37 C FR 1.121. This listing of claims will replace all prior versions, and listings, of claims in the application.
2.
A device comprising: a resistor including: a semi-insulating substrate; an active layer, positioned over the semi-insulating substrate, including an epitaxial layer des i gned for enhancement mode operation; a first channel region positioned over the active layer; a first gate metal covering a portion of the first channel region; ohmic contact material positioned at opposing ends of the active layer; a second gate metal covering a portion of the first channel region; and metal positioned over the opposing ends of the active layer to form input/output pads.
A device comprising: a resistor including: a semi-insulating substrate; an active layer, positioned over the semi- insulating substrate, including an epitaxial layer designed for enhancement mode operation; a first channel region positioned over the active layer;-a first gate metal covering a portion of the first channel region; ohmic contact material positioned at opposing ends of the active layer; a second channel region covering a portion of the active layer; a second gate metal covering a portion of the second channel region; and metal positioned over the opposing ends of the active layer to form input/output pads.
. A device comprising: a resistor including: a semi-insulating substrate; an active layer, positioned over the semi- insulating substrate, including an epitaxial laye r designed for enhancement mode operation; a first channel region having a serpentine shape, positioned over the active l ayer; a first gate metal covering a portion of the first channel region; 4 PAGE 4111 2 RCVD AT 1 17112006 7:0 0:42 PM [Easte rn Standard Time]* SVR:USPT₀EFXRF-628' DNIS:27383 00'* CSID:610 375 8 380 DURAT IO N (mm ~ ss): 01.46 11/27/2006 N ON 19:01 FAx 610 3758380 I 005/0 11 Appl i cat i on Serial Number 10/283,971 Response to Of fi ce A c tion Dated S e ptember 25. 2006 ohmic contact layer; a second gate metal covering a portion of ove r the opposing ends of the active layer to form material positioned at opposing ends of the active the first channel r egion; and metal positioned input/output pads.
Layer stacks claimed or described, ordered top of device to substrate.
high value resistor with two gate metals on first channel region
Materials described outside the worked examples.
semi-insulating substrate
epitaxial active layer for enhancement mode operation
gate metal
Measurements and analyses referenced in the patent, with their drawing references.
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,546,884Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 illustrates a prior art GaAs field effect transistor.
Figure 2 illustrates a plan view of a prior art GaAs resistor.
Figure 3 illustrates a space charge region for a GaAs FET.
Figure 4 illustrates a plan view of the resistor of the present invention.
Figure 5 illustrates a cross-sectional view of the resistor shown in
Figure 6 illustrates another embodiment of the resistor of the present invention.
Figure 7 illustrates another embodiment of the resistor of the present invention. DETAILS OF THE INVENTION [0013] When metal is patterned onto a semiconductor, a space charge region is formed. In a GaAs FET, this space charge region reduces the conductivity of the channel. In a depletion mode …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
Amendments to the Claims: A listing of the entire set of pending claims (including amendments to the claims, if any) is submitted herewith per 37 C FR 1.121. This listing of claims will replace all prior versions, and listings, of claims in the application.
2.
A device comprising: a resistor including: a semi-insulating substrate; an active layer, positioned over the semi-insulating substrate, including an epitaxial layer des i gned for enhancement mode operation; a first channel region positioned over the active layer; a first gate metal covering a portion of the first channel region; ohmic contact material positioned at opposing ends of the active layer; a second gate metal covering a portion of the first channel region; and metal positioned over the opposing ends of the active layer to form input/output pads.
A device comprising: a resistor including: a semi-insulating substrate; an active layer, positioned over the semi- insulating substrate, including an epitaxial layer designed for enhancement mode operation; a first channel region positioned over the active layer;-a first gate metal covering a portion of the first channel region; ohmic contact material positioned at opposing ends of the active layer; a second channel region covering a portion of the active layer; a second gate metal covering a portion of the second channel region; and metal positioned over the opposing ends of the active layer to form input/output pads.
. A device comprising: a resistor including: a semi-insulating substrate; an active layer, positioned over the semi- insulating substrate, including an epitaxial laye r designed for enhancement mode operation; a first channel region having a serpentine shape, positioned over the active l ayer; a first gate metal covering a portion of the first channel region; 4 PAGE 4111 2 RCVD AT 1 17112006 7:0 0:42 PM [Easte rn Standard Time]* SVR:USPT₀EFXRF-628' DNIS:27383 00'* CSID:610 375 8 380 DURAT IO N (mm ~ ss): 01.46 11/27/2006 N ON 19:01 FAx 610 3758380 I 005/0 11 Appl i cat i on Serial Number 10/283,971 Response to Of fi ce A c tion Dated S e ptember 25. 2006 ohmic contact layer; a second gate metal covering a portion of ove r the opposing ends of the active layer to form material positioned at opposing ends of the active the first channel r egion; and metal positioned input/output pads.
Layer stacks claimed or described, ordered top of device to substrate.
high value resistor with two gate metals on first channel region
Materials described outside the worked examples.
semi-insulating substrate
epitaxial active layer for enhancement mode operation
gate metal
Measurements and analyses referenced in the patent, with their drawing references.
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,546,884Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 illustrates a prior art GaAs field effect transistor.
Figure 2 illustrates a plan view of a prior art GaAs resistor.
Figure 3 illustrates a space charge region for a GaAs FET.
Figure 4 illustrates a plan view of the resistor of the present invention.
Figure 5 illustrates a cross-sectional view of the resistor shown in
Figure 6 illustrates another embodiment of the resistor of the present invention.
Figure 7 illustrates another embodiment of the resistor of the present invention. DETAILS OF THE INVENTION [0013] When metal is patterned onto a semiconductor, a space charge region is formed. In a GaAs FET, this space charge region reduces the conductivity of the channel. In a depletion mode …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
Amendments to the Claims: A listing of the entire set of pending claims (including amendments to the claims, if any) is submitted herewith per 37 C FR 1.121. This listing of claims will replace all prior versions, and listings, of claims in the application.
2.
A device comprising: a resistor including: a semi-insulating substrate; an active layer, positioned over the semi-insulating substrate, including an epitaxial layer des i gned for enhancement mode operation; a first channel region positioned over the active layer; a first gate metal covering a portion of the first channel region; ohmic contact material positioned at opposing ends of the active layer; a second gate metal covering a portion of the first channel region; and metal positioned over the opposing ends of the active layer to form input/output pads.
A device comprising: a resistor including: a semi-insulating substrate; an active layer, positioned over the semi- insulating substrate, including an epitaxial layer designed for enhancement mode operation; a first channel region positioned over the active layer;-a first gate metal covering a portion of the first channel region; ohmic contact material positioned at opposing ends of the active layer; a second channel region covering a portion of the active layer; a second gate metal covering a portion of the second channel region; and metal positioned over the opposing ends of the active layer to form input/output pads.
. A device comprising: a resistor including: a semi-insulating substrate; an active layer, positioned over the semi- insulating substrate, including an epitaxial laye r designed for enhancement mode operation; a first channel region having a serpentine shape, positioned over the active l ayer; a first gate metal covering a portion of the first channel region; 4 PAGE 4111 2 RCVD AT 1 17112006 7:0 0:42 PM [Easte rn Standard Time]* SVR:USPT₀EFXRF-628' DNIS:27383 00'* CSID:610 375 8 380 DURAT IO N (mm ~ ss): 01.46 11/27/2006 N ON 19:01 FAx 610 3758380 I 005/0 11 Appl i cat i on Serial Number 10/283,971 Response to Of fi ce A c tion Dated S e ptember 25. 2006 ohmic contact layer; a second gate metal covering a portion of ove r the opposing ends of the active layer to form material positioned at opposing ends of the active the first channel r egion; and metal positioned input/output pads.
Layer stacks claimed or described, ordered top of device to substrate.
high value resistor with two gate metals on first channel region
Materials described outside the worked examples.
semi-insulating substrate
epitaxial active layer for enhancement mode operation
gate metal
Measurements and analyses referenced in the patent, with their drawing references.
Related documents with shared materials, methods, properties, or citations.
high value resistor with first and second channel regions and two gate metals
high value resistor with serpentine first channel region
ohmic contact material
second metal
gallium arsenide (GaAs)
GaAs
Figure 7 illustrates another embodiment of the resistor of the present invention. DETAILS OF THE INVENTION [0013] When metal is patterned onto a semiconductor, a space charge region is formed. In a GaAs FET, this space charge region reduces the conductivity of the channel. In a depletion mode …
high value resistor with first and second channel regions and two gate metals
high value resistor with serpentine first channel region
ohmic contact material
second metal
gallium arsenide (GaAs)
GaAs
Figure 7 illustrates another embodiment of the resistor of the present invention. DETAILS OF THE INVENTION [0013] When metal is patterned onto a semiconductor, a space charge region is formed. In a GaAs FET, this space charge region reduces the conductivity of the channel. In a depletion mode …
high value resistor with first and second channel regions and two gate metals
high value resistor with serpentine first channel region
ohmic contact material
second metal
gallium arsenide (GaAs)
GaAs
Figure 7 illustrates another embodiment of the resistor of the present invention. DETAILS OF THE INVENTION [0013] When metal is patterned onto a semiconductor, a space charge region is formed. In a GaAs FET, this space charge region reduces the conductivity of the channel. In a depletion mode …
high value resistor with first and second channel regions and two gate metals
high value resistor with serpentine first channel region
ohmic contact material
second metal
gallium arsenide (GaAs)
GaAs
Figure 7 illustrates another embodiment of the resistor of the present invention. DETAILS OF THE INVENTION [0013] When metal is patterned onto a semiconductor, a space charge region is formed. In a GaAs FET, this space charge region reduces the conductivity of the channel. In a depletion mode …