Patent
US 9,294,055CIRCUIT AND METHOD FOR BIASING A GALLIUM ARSENIDE (GaAs) POWER AMPLIFIER
Ziv Alon
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
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US 9,294,055Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a block diagram illustrating a simplified portable transceiver including an embodiment of a circuit and method for biasing a gallium arsenide (GaAs) …
FIG. 2 is a schematic diagram illustrating an embodiment of the gallium arsenide (GaAs) bias circuit of
FIG. 3 is a schematic diagram illustrating of the Vref generator of
FIG. 4 is a schematic diagram showing a refresh circuit. [0013]
FIG. 5 is a flow chart describing the operation of an embodiment of the gallium arsenide (GaAs) bias circuit of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
canceled
(Cu rr ently Amended) A semiconductor die comprising: a power amplifier configured to amplify a radio frequency input signal to generate a radio frequency output signal; a reference voltage generator configured to receive a control voltage that controls a bias current of the power amplifier and to generate a reference voltage by translating a voltage level of the control voltage, the reference voltage having a voltage level greater than the voltage level of the control voltage, the reference voltage generator including a first field effect transistor (FET) having a source configured to generate the reference voltage and a drain configured to receive a switch bias voltage, the reference voltage generator further including a first bipolar transistor and a first resistor, the first bipolar transistor having an emitter configured to receive the control voltage and a collector electrically connected to the switch bias voltage through the first resistor; and a bias circuit configured to receive the reference voltage and to convert the reference voltage to a reference current, the bias circuit further configured mi rr or the reference cu rr ent to control [[a]] the bias cu rr ent of the power amplifier.
The semiconductor die of claim 2 further comprising an enable circuit configured to receive an enable signal, the enable circuit configured to turn off the reference voltage generator when the enable signal is disabled by disconnecting a ground supply of the reference voltage generator.
The semiconductor die of claim 2 wherein the bias circuit includes a second bipolar transistor having a collector configured to receive the reference current, the first bipolar transistor configured to compensate for a process and temperature variation of the second bipolar transistor.
The semiconductor die of claim 2 wherein the power amplifier, the reference voltage generator, and the bias circuit are implemented in a gallium arsenide (GaAs) material system.
(Cu rr ently Amended) A radio frequency system comprising: a transmitter configured to generate a power amplifier input signal; a power amplifier configured to amplify the power amplifier input signal to generate a power amplifier output signal; a reference voltage generator configured to receive a control voltage that controls a bias current of the power amplifier and to generate a reference voltage by translating a voltage level of the control voltage, the reference voltage having a voltage level greater than the voltage level of the control voltage, the reference voltage generator including a first field effect transistor (FET) having a source configured to generate the reference voltage and a drain configured to receive a switch bias voltage, the reference voltage generator further including a first bipolar transistor and a first resistor, the first bipolar transistor having an emitter configured to receive the control voltage and a collector electrically connected to the switch bias voltage through the first resistor; and a bias circuit configured to receive the reference voltage and to convert the reference voltage to a reference current, the bias circuit further configured mi rr or the reference cu rr ent to control [[a]] the bias cu rr ent of the power amplifier.
The radio frequency system of claim 10 further comprising an enable circuit configured to receive an enable signal, the enable circuit configured to turn off the reference voltage generator when the enable signal is disabled by disconnecting a ground supply of the reference voltage generator.
The radio frequency system of claim 10 wherein the bias circuit includes a second bipolar transistor having a collector configured to receive the reference -4- Application No.: 14/040,523 Filing Date: curr ent, the first bipolar transistor configured to compensate for a process and temperature variation of the second bipolar transistor.
The radio frequency system of claim 10 wherein the reference voltage generator further includes a second FET having a drain electrically connected to the switch bias voltage and a gate electrically connected to a collector of the first bipolar transistor, the second FET configured to compensate for a process and temperature variation of the first FET.
The radio frequency system of claim 10 further comprising a gallium arsenide (GaAs) die including the power amplifier, the reference voltage generator, and the bias circuit fabricated thereon.
The radio frequency system of claim 10 wherein the transmitter includes a modulator and an upconverter, the modulator configured to generate a modulated signal by modulating an in-phase signal and a quadrature-phase signal, the upconverter configured to upconvert the modulated signal to generate the power amplifier input signal.
(Cu rr ently Amended) A method of power amplification in a radio frequency system, the method comprising: generating a power amplifier input signal using a transmitter; amplifying the power amplifier input signal using a power amplifier; receiving a control voltage for controlling a bias current of the power amplifier as an input to a reference voltage generator; generating a reference voltage by translating a voltage level of [[a]] the control voltage using [[a]] the reference voltage generator, the reference voltage having a voltage level greater than the voltage level of the control voltage, the reference voltage generator including a first field effect transistor (FET) having a source configured to generate the reference voltage and a drain configured to receive a switch bias voltage, the reference voltage generator further including a first bipolar transistor and a first resistor, the first bipolar transistor having an emitter configured to receive the control voltage and a collector electrically connected to the switch bias voltage through the first resistor; and controlling [[a]] the bias current of the power amplifier using a bias circuit, the bias circuit configured to receive the reference voltage and to convert the reference voltage to a reference cu rr ent, the bias circuit further configured mi rr or the reference curr ent to control the bias current of the power amplifier.
The method of claim 18 further comprising receiving an enable signal into an enable circuit, and turning off the reference voltage generator when the enable signal is disabled by disconnecting a ground supply of the reference voltage generator using the enable circuit.
The method of claim 18 wherein the bias circuit includes a second bipolar transistor having a collector configured to receive the reference cu rr ent, the method further comprising compensating for a process and temperature variation of the second bipolar transistor using the first bipolar transistor.
The method of claim 18 wherein the reference voltage generator further includes a second FET having a drain electrically connected to the switch bias voltage and a gate electrically connected to a collector of the first bipolar transistor, the method further comprising compensating for a process and temperature variation of the first FET using the second FET. -7-
Layer stacks claimed or described, ordered top of device to substrate.
GaAs power amplifier semiconductor die with bias circuit
No layer stack recorded.
radio frequency system with GaAs power amplifier and bias circuit
No layer stack recorded.
Materials described outside the worked examples.
gallium arsenide
GaAs
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 is a schematic diagram illustrating an embodiment of the gallium arsenide (GaAs) bias circuit of
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | 0–1.2 V | — |
Voltage |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,294,055Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a block diagram illustrating a simplified portable transceiver including an embodiment of a circuit and method for biasing a gallium arsenide (GaAs) …
FIG. 2 is a schematic diagram illustrating an embodiment of the gallium arsenide (GaAs) bias circuit of
FIG. 3 is a schematic diagram illustrating of the Vref generator of
FIG. 4 is a schematic diagram showing a refresh circuit. [0013]
FIG. 5 is a flow chart describing the operation of an embodiment of the gallium arsenide (GaAs) bias circuit of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
canceled
(Cu rr ently Amended) A semiconductor die comprising: a power amplifier configured to amplify a radio frequency input signal to generate a radio frequency output signal; a reference voltage generator configured to receive a control voltage that controls a bias current of the power amplifier and to generate a reference voltage by translating a voltage level of the control voltage, the reference voltage having a voltage level greater than the voltage level of the control voltage, the reference voltage generator including a first field effect transistor (FET) having a source configured to generate the reference voltage and a drain configured to receive a switch bias voltage, the reference voltage generator further including a first bipolar transistor and a first resistor, the first bipolar transistor having an emitter configured to receive the control voltage and a collector electrically connected to the switch bias voltage through the first resistor; and a bias circuit configured to receive the reference voltage and to convert the reference voltage to a reference current, the bias circuit further configured mi rr or the reference cu rr ent to control [[a]] the bias cu rr ent of the power amplifier.
The semiconductor die of claim 2 further comprising an enable circuit configured to receive an enable signal, the enable circuit configured to turn off the reference voltage generator when the enable signal is disabled by disconnecting a ground supply of the reference voltage generator.
The semiconductor die of claim 2 wherein the bias circuit includes a second bipolar transistor having a collector configured to receive the reference current, the first bipolar transistor configured to compensate for a process and temperature variation of the second bipolar transistor.
The semiconductor die of claim 2 wherein the power amplifier, the reference voltage generator, and the bias circuit are implemented in a gallium arsenide (GaAs) material system.
(Cu rr ently Amended) A radio frequency system comprising: a transmitter configured to generate a power amplifier input signal; a power amplifier configured to amplify the power amplifier input signal to generate a power amplifier output signal; a reference voltage generator configured to receive a control voltage that controls a bias current of the power amplifier and to generate a reference voltage by translating a voltage level of the control voltage, the reference voltage having a voltage level greater than the voltage level of the control voltage, the reference voltage generator including a first field effect transistor (FET) having a source configured to generate the reference voltage and a drain configured to receive a switch bias voltage, the reference voltage generator further including a first bipolar transistor and a first resistor, the first bipolar transistor having an emitter configured to receive the control voltage and a collector electrically connected to the switch bias voltage through the first resistor; and a bias circuit configured to receive the reference voltage and to convert the reference voltage to a reference current, the bias circuit further configured mi rr or the reference cu rr ent to control [[a]] the bias cu rr ent of the power amplifier.
The radio frequency system of claim 10 further comprising an enable circuit configured to receive an enable signal, the enable circuit configured to turn off the reference voltage generator when the enable signal is disabled by disconnecting a ground supply of the reference voltage generator.
The radio frequency system of claim 10 wherein the bias circuit includes a second bipolar transistor having a collector configured to receive the reference -4- Application No.: 14/040,523 Filing Date: curr ent, the first bipolar transistor configured to compensate for a process and temperature variation of the second bipolar transistor.
The radio frequency system of claim 10 wherein the reference voltage generator further includes a second FET having a drain electrically connected to the switch bias voltage and a gate electrically connected to a collector of the first bipolar transistor, the second FET configured to compensate for a process and temperature variation of the first FET.
The radio frequency system of claim 10 further comprising a gallium arsenide (GaAs) die including the power amplifier, the reference voltage generator, and the bias circuit fabricated thereon.
The radio frequency system of claim 10 wherein the transmitter includes a modulator and an upconverter, the modulator configured to generate a modulated signal by modulating an in-phase signal and a quadrature-phase signal, the upconverter configured to upconvert the modulated signal to generate the power amplifier input signal.
(Cu rr ently Amended) A method of power amplification in a radio frequency system, the method comprising: generating a power amplifier input signal using a transmitter; amplifying the power amplifier input signal using a power amplifier; receiving a control voltage for controlling a bias current of the power amplifier as an input to a reference voltage generator; generating a reference voltage by translating a voltage level of [[a]] the control voltage using [[a]] the reference voltage generator, the reference voltage having a voltage level greater than the voltage level of the control voltage, the reference voltage generator including a first field effect transistor (FET) having a source configured to generate the reference voltage and a drain configured to receive a switch bias voltage, the reference voltage generator further including a first bipolar transistor and a first resistor, the first bipolar transistor having an emitter configured to receive the control voltage and a collector electrically connected to the switch bias voltage through the first resistor; and controlling [[a]] the bias current of the power amplifier using a bias circuit, the bias circuit configured to receive the reference voltage and to convert the reference voltage to a reference cu rr ent, the bias circuit further configured mi rr or the reference curr ent to control the bias current of the power amplifier.
The method of claim 18 further comprising receiving an enable signal into an enable circuit, and turning off the reference voltage generator when the enable signal is disabled by disconnecting a ground supply of the reference voltage generator using the enable circuit.
The method of claim 18 wherein the bias circuit includes a second bipolar transistor having a collector configured to receive the reference cu rr ent, the method further comprising compensating for a process and temperature variation of the second bipolar transistor using the first bipolar transistor.
The method of claim 18 wherein the reference voltage generator further includes a second FET having a drain electrically connected to the switch bias voltage and a gate electrically connected to a collector of the first bipolar transistor, the method further comprising compensating for a process and temperature variation of the first FET using the second FET. -7-
Layer stacks claimed or described, ordered top of device to substrate.
GaAs power amplifier semiconductor die with bias circuit
No layer stack recorded.
radio frequency system with GaAs power amplifier and bias circuit
No layer stack recorded.
Materials described outside the worked examples.
gallium arsenide
GaAs
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 is a schematic diagram illustrating an embodiment of the gallium arsenide (GaAs) bias circuit of
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | 0–1.2 V | — |
Voltage |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,294,055Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a block diagram illustrating a simplified portable transceiver including an embodiment of a circuit and method for biasing a gallium arsenide (GaAs) …
FIG. 2 is a schematic diagram illustrating an embodiment of the gallium arsenide (GaAs) bias circuit of
FIG. 3 is a schematic diagram illustrating of the Vref generator of
FIG. 4 is a schematic diagram showing a refresh circuit. [0013]
FIG. 5 is a flow chart describing the operation of an embodiment of the gallium arsenide (GaAs) bias circuit of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
canceled
(Cu rr ently Amended) A semiconductor die comprising: a power amplifier configured to amplify a radio frequency input signal to generate a radio frequency output signal; a reference voltage generator configured to receive a control voltage that controls a bias current of the power amplifier and to generate a reference voltage by translating a voltage level of the control voltage, the reference voltage having a voltage level greater than the voltage level of the control voltage, the reference voltage generator including a first field effect transistor (FET) having a source configured to generate the reference voltage and a drain configured to receive a switch bias voltage, the reference voltage generator further including a first bipolar transistor and a first resistor, the first bipolar transistor having an emitter configured to receive the control voltage and a collector electrically connected to the switch bias voltage through the first resistor; and a bias circuit configured to receive the reference voltage and to convert the reference voltage to a reference current, the bias circuit further configured mi rr or the reference cu rr ent to control [[a]] the bias cu rr ent of the power amplifier.
The semiconductor die of claim 2 further comprising an enable circuit configured to receive an enable signal, the enable circuit configured to turn off the reference voltage generator when the enable signal is disabled by disconnecting a ground supply of the reference voltage generator.
The semiconductor die of claim 2 wherein the bias circuit includes a second bipolar transistor having a collector configured to receive the reference current, the first bipolar transistor configured to compensate for a process and temperature variation of the second bipolar transistor.
The semiconductor die of claim 2 wherein the power amplifier, the reference voltage generator, and the bias circuit are implemented in a gallium arsenide (GaAs) material system.
(Cu rr ently Amended) A radio frequency system comprising: a transmitter configured to generate a power amplifier input signal; a power amplifier configured to amplify the power amplifier input signal to generate a power amplifier output signal; a reference voltage generator configured to receive a control voltage that controls a bias current of the power amplifier and to generate a reference voltage by translating a voltage level of the control voltage, the reference voltage having a voltage level greater than the voltage level of the control voltage, the reference voltage generator including a first field effect transistor (FET) having a source configured to generate the reference voltage and a drain configured to receive a switch bias voltage, the reference voltage generator further including a first bipolar transistor and a first resistor, the first bipolar transistor having an emitter configured to receive the control voltage and a collector electrically connected to the switch bias voltage through the first resistor; and a bias circuit configured to receive the reference voltage and to convert the reference voltage to a reference current, the bias circuit further configured mi rr or the reference cu rr ent to control [[a]] the bias cu rr ent of the power amplifier.
The radio frequency system of claim 10 further comprising an enable circuit configured to receive an enable signal, the enable circuit configured to turn off the reference voltage generator when the enable signal is disabled by disconnecting a ground supply of the reference voltage generator.
The radio frequency system of claim 10 wherein the bias circuit includes a second bipolar transistor having a collector configured to receive the reference -4- Application No.: 14/040,523 Filing Date: curr ent, the first bipolar transistor configured to compensate for a process and temperature variation of the second bipolar transistor.
The radio frequency system of claim 10 wherein the reference voltage generator further includes a second FET having a drain electrically connected to the switch bias voltage and a gate electrically connected to a collector of the first bipolar transistor, the second FET configured to compensate for a process and temperature variation of the first FET.
The radio frequency system of claim 10 further comprising a gallium arsenide (GaAs) die including the power amplifier, the reference voltage generator, and the bias circuit fabricated thereon.
The radio frequency system of claim 10 wherein the transmitter includes a modulator and an upconverter, the modulator configured to generate a modulated signal by modulating an in-phase signal and a quadrature-phase signal, the upconverter configured to upconvert the modulated signal to generate the power amplifier input signal.
(Cu rr ently Amended) A method of power amplification in a radio frequency system, the method comprising: generating a power amplifier input signal using a transmitter; amplifying the power amplifier input signal using a power amplifier; receiving a control voltage for controlling a bias current of the power amplifier as an input to a reference voltage generator; generating a reference voltage by translating a voltage level of [[a]] the control voltage using [[a]] the reference voltage generator, the reference voltage having a voltage level greater than the voltage level of the control voltage, the reference voltage generator including a first field effect transistor (FET) having a source configured to generate the reference voltage and a drain configured to receive a switch bias voltage, the reference voltage generator further including a first bipolar transistor and a first resistor, the first bipolar transistor having an emitter configured to receive the control voltage and a collector electrically connected to the switch bias voltage through the first resistor; and controlling [[a]] the bias current of the power amplifier using a bias circuit, the bias circuit configured to receive the reference voltage and to convert the reference voltage to a reference cu rr ent, the bias circuit further configured mi rr or the reference curr ent to control the bias current of the power amplifier.
The method of claim 18 further comprising receiving an enable signal into an enable circuit, and turning off the reference voltage generator when the enable signal is disabled by disconnecting a ground supply of the reference voltage generator using the enable circuit.
The method of claim 18 wherein the bias circuit includes a second bipolar transistor having a collector configured to receive the reference cu rr ent, the method further comprising compensating for a process and temperature variation of the second bipolar transistor using the first bipolar transistor.
The method of claim 18 wherein the reference voltage generator further includes a second FET having a drain electrically connected to the switch bias voltage and a gate electrically connected to a collector of the first bipolar transistor, the method further comprising compensating for a process and temperature variation of the first FET using the second FET. -7-
Layer stacks claimed or described, ordered top of device to substrate.
GaAs power amplifier semiconductor die with bias circuit
No layer stack recorded.
radio frequency system with GaAs power amplifier and bias circuit
No layer stack recorded.
Materials described outside the worked examples.
gallium arsenide
GaAs
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 is a schematic diagram illustrating an embodiment of the gallium arsenide (GaAs) bias circuit of
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | 0–1.2 V | — |
Voltage |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,294,055Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a block diagram illustrating a simplified portable transceiver including an embodiment of a circuit and method for biasing a gallium arsenide (GaAs) …
FIG. 2 is a schematic diagram illustrating an embodiment of the gallium arsenide (GaAs) bias circuit of
FIG. 3 is a schematic diagram illustrating of the Vref generator of
FIG. 4 is a schematic diagram showing a refresh circuit. [0013]
FIG. 5 is a flow chart describing the operation of an embodiment of the gallium arsenide (GaAs) bias circuit of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
canceled
(Cu rr ently Amended) A semiconductor die comprising: a power amplifier configured to amplify a radio frequency input signal to generate a radio frequency output signal; a reference voltage generator configured to receive a control voltage that controls a bias current of the power amplifier and to generate a reference voltage by translating a voltage level of the control voltage, the reference voltage having a voltage level greater than the voltage level of the control voltage, the reference voltage generator including a first field effect transistor (FET) having a source configured to generate the reference voltage and a drain configured to receive a switch bias voltage, the reference voltage generator further including a first bipolar transistor and a first resistor, the first bipolar transistor having an emitter configured to receive the control voltage and a collector electrically connected to the switch bias voltage through the first resistor; and a bias circuit configured to receive the reference voltage and to convert the reference voltage to a reference current, the bias circuit further configured mi rr or the reference cu rr ent to control [[a]] the bias cu rr ent of the power amplifier.
The semiconductor die of claim 2 further comprising an enable circuit configured to receive an enable signal, the enable circuit configured to turn off the reference voltage generator when the enable signal is disabled by disconnecting a ground supply of the reference voltage generator.
The semiconductor die of claim 2 wherein the bias circuit includes a second bipolar transistor having a collector configured to receive the reference current, the first bipolar transistor configured to compensate for a process and temperature variation of the second bipolar transistor.
The semiconductor die of claim 2 wherein the power amplifier, the reference voltage generator, and the bias circuit are implemented in a gallium arsenide (GaAs) material system.
(Cu rr ently Amended) A radio frequency system comprising: a transmitter configured to generate a power amplifier input signal; a power amplifier configured to amplify the power amplifier input signal to generate a power amplifier output signal; a reference voltage generator configured to receive a control voltage that controls a bias current of the power amplifier and to generate a reference voltage by translating a voltage level of the control voltage, the reference voltage having a voltage level greater than the voltage level of the control voltage, the reference voltage generator including a first field effect transistor (FET) having a source configured to generate the reference voltage and a drain configured to receive a switch bias voltage, the reference voltage generator further including a first bipolar transistor and a first resistor, the first bipolar transistor having an emitter configured to receive the control voltage and a collector electrically connected to the switch bias voltage through the first resistor; and a bias circuit configured to receive the reference voltage and to convert the reference voltage to a reference current, the bias circuit further configured mi rr or the reference cu rr ent to control [[a]] the bias cu rr ent of the power amplifier.
The radio frequency system of claim 10 further comprising an enable circuit configured to receive an enable signal, the enable circuit configured to turn off the reference voltage generator when the enable signal is disabled by disconnecting a ground supply of the reference voltage generator.
The radio frequency system of claim 10 wherein the bias circuit includes a second bipolar transistor having a collector configured to receive the reference -4- Application No.: 14/040,523 Filing Date: curr ent, the first bipolar transistor configured to compensate for a process and temperature variation of the second bipolar transistor.
The radio frequency system of claim 10 wherein the reference voltage generator further includes a second FET having a drain electrically connected to the switch bias voltage and a gate electrically connected to a collector of the first bipolar transistor, the second FET configured to compensate for a process and temperature variation of the first FET.
The radio frequency system of claim 10 further comprising a gallium arsenide (GaAs) die including the power amplifier, the reference voltage generator, and the bias circuit fabricated thereon.
The radio frequency system of claim 10 wherein the transmitter includes a modulator and an upconverter, the modulator configured to generate a modulated signal by modulating an in-phase signal and a quadrature-phase signal, the upconverter configured to upconvert the modulated signal to generate the power amplifier input signal.
(Cu rr ently Amended) A method of power amplification in a radio frequency system, the method comprising: generating a power amplifier input signal using a transmitter; amplifying the power amplifier input signal using a power amplifier; receiving a control voltage for controlling a bias current of the power amplifier as an input to a reference voltage generator; generating a reference voltage by translating a voltage level of [[a]] the control voltage using [[a]] the reference voltage generator, the reference voltage having a voltage level greater than the voltage level of the control voltage, the reference voltage generator including a first field effect transistor (FET) having a source configured to generate the reference voltage and a drain configured to receive a switch bias voltage, the reference voltage generator further including a first bipolar transistor and a first resistor, the first bipolar transistor having an emitter configured to receive the control voltage and a collector electrically connected to the switch bias voltage through the first resistor; and controlling [[a]] the bias current of the power amplifier using a bias circuit, the bias circuit configured to receive the reference voltage and to convert the reference voltage to a reference cu rr ent, the bias circuit further configured mi rr or the reference curr ent to control the bias current of the power amplifier.
The method of claim 18 further comprising receiving an enable signal into an enable circuit, and turning off the reference voltage generator when the enable signal is disabled by disconnecting a ground supply of the reference voltage generator using the enable circuit.
The method of claim 18 wherein the bias circuit includes a second bipolar transistor having a collector configured to receive the reference cu rr ent, the method further comprising compensating for a process and temperature variation of the second bipolar transistor using the first bipolar transistor.
The method of claim 18 wherein the reference voltage generator further includes a second FET having a drain electrically connected to the switch bias voltage and a gate electrically connected to a collector of the first bipolar transistor, the method further comprising compensating for a process and temperature variation of the first FET using the second FET. -7-
Layer stacks claimed or described, ordered top of device to substrate.
GaAs power amplifier semiconductor die with bias circuit
No layer stack recorded.
radio frequency system with GaAs power amplifier and bias circuit
No layer stack recorded.
Materials described outside the worked examples.
gallium arsenide
GaAs
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 is a schematic diagram illustrating an embodiment of the gallium arsenide (GaAs) bias circuit of
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | 0–1.2 V | — |
Voltage |
Related documents with shared materials, methods, properties, or citations.
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