Patent
US 8,697,532InP BASED HETEROJUNCTION BIPOLAR TRANSISTORS WITH EMITTER-UP AND EMITTER-DOWN PROFILES ON A COMMON WAFER
Mary Chen
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 8,697,532Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 depicts a side view of an emitter-up HBT; [0010]
FIG. 2 depicts a side view of an emitter-down HBT; [0011]
FIG. 3 depicts a wafer with HBTs on the wafer; [0012]
FIGS. 4-23 depict a process of forming HBTs based on an exemplary embodiment; [0013]
FIG. 5, layer 70 may be formed, for example, by epitaxial growth, on top of the layer 60. The layer 70 may comprise, for example, N-type I nP (N-) undoped …
FIG. 6; 2) performing ion implantation until region 75 is formed, as shown in
FIG. 7; 3) removing implant mask 71 and annealing the structure in
FIG. 8 for implant activation and damage removal wherein N region 75 is formed. [0022] This disclosure is not limited to a shape of implant region 75 as …
FIG. 9; 2) performing ion implantation until regions 78 are formed, as shown in
FIG. 10; 3) removing implant mask 72, as shown in
FIG. 11. This disclosure is not limited to shape of implant isolation regions 78 as depicted in
FIG. 12, a base layer 80 may be formed, for example, by epitaxial growth, on top of the layer 70 or on top of the optional layer referred to above. The base …
FIG. 13, a layer 90 may be formed, for example by epitaxial growth, on top of the base layer 80. The layer 90 may comprise, for example, N- type I nP (N) …
FIG. 14, a layer 100 may be formed, for example by epitaxial growth. The emitter cap layer 9 may comprise, for example, N-type I nGaAs (N +) material that is …
FIG. 15; 2) performing ion implantation until region 95 may be formed, as shown in
FIG. 16; 3) removing implant mask 91 and performing rapid thermal annealing of the structure in
FIG. 17 for implant activation and damage removal wherein N + region 95 may be formed. [0032] I on implantation of region 95 may be performed on layer 90 prior …
FIG. 18; etching emitter mesas 150 for emitter-up HBT 10 and collector mesas 160 for emitter-down HBT 11, as shown in
FIG. 19; providing base metal contacts 120 through lithography and metal deposition, as shown in
FIG. 20; etching base mesas 170, as shown in
FIG. 21; providing metal contacts 130 through lithography and metal deposition, as shown in
FIG. 22; and etching isolation mesas 180, as shown in
FIG. 23. As shown in FIGs. 18-23, the substrate 50 has the same thickness at locations under the emitter-up HBT 10 and the emitter-down HBT 11. The substrate …
FIGS. 24-29 depict a process of forming HBTs based on another exemplary embodiment.
FIG. 25, emitter mesas 210 for emitter-up HBT 10 and collector mesas 220 for emitter-down HBT 11 may be etched. Using metal contacts 110 as a mask, etching of …
FIG. 26, layer 200 may be formed to at least partially cover metal contacts 110. Layer 200 may comprise, for example, positive tone photo definable polyimide …
FIG. 27, layer 200 may be soft baked, may be flood exposed (maskless) and may be developed so as to remove most of the exposed layer 200 material except for the …
FIGS. 28-29, formation of self-aligned metal contacts 120 may be performed by: providing a photoresist layer 205 (patterned for base contact metal) so as to …
FIG. 29; removing any metal flaxes that may be deposited on portions 201, 202, 203, 204 by performing slight Argon (Ar) ion milling etch process. [0040] The …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A wafer comprising: an InP based semiconductor substrate; at least one emitter-up Heterojunction Bipolar Transistor (HBT), wherein a collector layer is disposed between a base layer and a substrate; and at least one emitter-down HBT, wherein an emitter layer is disposed between a base layer and a substrate. withdrawn
The wafer as claimed in Claim 1 wherein said at least one emitter-down HBT comprises a plurality of ion implanted regions in said emitter layer. withdrawn
The wafer as claimed in Claim 1 wherein said at least one emitter-up HBT comprises an ion implanted region in said emitter layer. withdrawn
An Integrated Circuit (IC) comprising: an InP based semiconductor substrate; at least one emitter-up Heterojunction Bipolar Transistor (HBT), wherein a collector layer is disposed between a base layer and a substrate; and Application No: 12/616,374 Page 3 at least one emitter-down HBT, wherein an emitter layer is disposed between a base layer and a substrate. withdrawn
The IC as claimed in Claim 7 wherein said at least one emitter-down HBT comprises a plurality of ion implanted region in said emitter layer. withdrawn
The IC as claimed in Claim 7 wherein said at least one emitter-up HBT comprises an ion implanted region in said emitter layer. withdrawn
A wafer comprising: at least one emitter-up Heterojunction Bipolar Transistor (HBT) comprising: an InP based semiconductor substrate; a sub-collector layer formed on said substrate; a collector layer formed on said sub-collector layer; a base layer formed on said collector layer; an emitter layer formed on said base layer; an emitter cap layer formed on said emitter layer; an electrically conducting emitter contact formed on said emitter cap layer; an electrically conducting base contact formed on said base layer; and an electrically conducting collector contact formed on said sub-collector layer; at least one emitter-down HBT comprising an InP based semiconductor substrate; Application No: 12/616,374 Page 4 a sub-emitter layer formed on said substrate; an emitter layer formed on said sub-emitter layer; a plurality of implant regions within said emitter layer; a base layer formed on said emitter layer; a collector layer formed on said base layer; a collector cap formed on said collector layer; an electrically conducting collector contact formed on said collector cap; an electrically conducting base contact formed on said base layer; and an electrically conducting emitter contact formed on said sub-emitter layer. withdrawn
The wafer as claimed in Claim 13 wherein at least one of said plurality of ion implanted regions is annealed for doping activation. withdrawn
The wafer as claimed in Claim 13 wherein said at least one emitter-up HBT comprises an ion implanted region in said emitter layer. withdrawn
An integrated circuit comprising: an emitter-up Hetero-junction Bipolar Transistor (HBT) on a first location on a substrate comprising: an undoped collector layer over the substrate; a base layer over the undoped collector layer; and an emitter layer over the first portion of the base layer; and an emitter-down HBT on a second location on the substrate, wherein the substrate is of equal thickness at the first location and the second location, the emitter-down HBT comprising: a first ion implant in the undoped collector layer to provide an intrinsic emitter; Application No: 12/616,374 Page 5 a second ion implant in the undoped collector layer adjacent to the first ion implant to prevent parasitic current injection through an extrinsic base emitter junction area under forward bias; the base layer over the first and second ion implants; and the emitter layer over the base layer to provide a collector for the emitter-down HBT. withdrawn
The integrated circuit of claim 18 wherein the substrate comprises a semi- insulating InP wafer. withdrawn
The integrated circuit of claim 18 wherein the undoped collector layer comprises N-type InP (N) undoped material. withdrawn
The integrated circuit of claim 18 wherein a thickness of the undoped collector layer is selected to obtain a desired BVceo. withdrawn
The integrated circuit of claim 18 wherein the base layer comprises P-type GaAsSb (P+) material. withdrawn
The integrated circuit of claim 18 wherein the emitter layer comprises N-type InP (N) material. withdrawn
The integrated circuit of claim 18 wherein the emitter-up HBT f u rther comprises a third ion implant in the emitter layer. withdrawn
The integrated circuit of claim 18 wherein: the emitter-up HBT f u rther comprises: an emitter mesa; a first base mesa; and a first isolation mesa; and forming the emitter-down HBT f u rther comprises: Application No: 12/616,374 Page 6 a collector mesa; a second base mesa; and a second isolation mesa. withdrawn
The integrated circuit of claim 18 wherein: the emitter-up HBT f u rther comprises: an emitter mesa; an emitter metal contact overhanging the emitter mesa; and a self aligned base metal contact. withdrawn
The integrated circuit of claim 18 wherein: the substrate comprises a semi-insulating InP wafer; the undoped collector layer comprises N-type InP (N) undoped material; the base layer comprises P-type GaAsSb (P+) material; and the emitter layer comprises N-type InP (N) material. withdrawn
The integrated circuit of claim 18 wherein: the emitter-up HBT has a high BV c eo; and the emitter-down HBT has a high Ft. withdrawn
A method of forming an emitter-up Heterojunction Bipolar Transistor (HBT) and an emitter-down HBT on a single wafer, said method comprising: providing a semiconductor substrate; forming a sub-layer over the substrate that f u nctions as a sub-collector layer for the emitter up HBT and that f u nctions as a sub-emitter for the emitter down HBT; forming a collector layer disposed over the sub-layer; implanting ions into a portion of the collector layer to form a first implant region for forming an emitter for the emitter-down HBT; annealing the first implant region; implanting ions into second regions in the collector layer, the second implant regions on either side of and directly adjacent to the first implant region, and the second implant regions Application No: 12/616,374 Page 7 forming isolation regions for preventing parasitic current injection through an extrinsic base emitter junction area under forward bias, wherein the second implant regions do not extend into h-eu gh the sub-layer int- the substrae; forming a base layer disposed over the collector layer and over the first and second implant regions; and forming an emitter layer above the base layer that functions as an emitter layer for the emitter-up HBT, and that functions as a collector layer for the emitter-down HBT.
The method of Claim 29 wherein implanting ions into the portion of the collector layer comprises: applying and forming an implant mask to said collector layer to expose only said portion of said collector layer; implanting the first implant region in said collector layer.
The method of Claim 29 wherein forming the emitter layer above the base layer further comprises: implanting ions in a portion of said emitter layer to form a third implant region in said emitter layer for the emitter-up HBT
The method of Claim 29 further comprising: forming a first metal contact on at least one of the HBTs; forming a first mesa for the at least one of the HBTs so that said first metal contact overhangs said first mesa; Application No: 12/616,374 Page 8 forming a photo sensitive dielectric layer to at least partially cover said first metal contact; flood exposing said photo sensitive dielectric layer; developing said photo sensitive dielectric layer to remove most of said photo sensitive layer, wherein portions of said photo sensitive dielectric layer remain under said overhang of said first metal contact; forming self-aligned metal contacts. withdrawn
The method of Claim 29, wherein annealing the first implant region is done before forming the second implant regions.
The method of Claim 29, wherein annealing the first implant region is done after forming the first implant region and the second implant regions.
The method of Claim 29, wherein the first implant region is between the second implant regions.
The method of Claim 29, wherein the first implant region is physically contacting at least one of the second implant regions.
The method of Claim 29, wherein the second implant regions are at least partially covered by the base layer.
The method of Claim 29, wherein the first implant region and the second implant regions are associated with the emitter-down HBT.
The method of Claim 29, wherein the first implant region is an N- doped region.
The method of claim 29 wherein: the substrate comprises a semi-insulating InP wafer; the collector layer comprises N-type InP (N-) undoped material; Application No: 12/616,374 Page the base layer comprises P-type GaAsSb (P+) material; and the emitter layer comprises N-type InP (N) material.
The method of claim 29 further comprising forming the collector layer to have a thickness to obtain a BVceo for the emitter-up HBT.
The method of claim 29 wherein ions are implanted into the first implant region before implanting ions to form the second implant regions.
The method of claim 29 wherein ions are implanted into the second implant regions before implanting ions to form the first implant region.
The method of claim 29 wherein the sub-layer heavily doped with silicon or N-type InP (N+)
The method of claim 29 wherein the sub-layer angstroms.
The method of claim 29 wherein the sub-layer the emitter-down HBT. comprises N-type InGasAs (N+) material material heavily doped with silicon. has a thickness from 100 angstroms to 5000 is contiguous between the emitter-up HBT and
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A method of forming an emitter-up Heterojunction Bipolar Transistor (HBT) and an emitter-down HBT on a wafer, said method comprising: providing an InP based semiconductor substrate; forming a plurality of layers on said substrate; forming a first metal contact on a top layer of said plurality of layers for at least one HBT on said substrate; forming a first mesa so that said first metal contact overhangs said mesa for said at least one HBT on said substrate; forming a photo sensitive dielectric layer so as to at least partially cover said first metal contact on said substrate; flood exposing said photo sensitive dielectric layer; developing said photo sensitive dielectric layer so as to remove most of said photo sensitive dielectric layer, wherein portions of said photo sensitive dielectric layer remain under said overhang of said first metal contact; forming self-aligned metal contacts. withdrawn
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Layer stacks claimed or described, ordered top of device to substrate.
emitter-up Heterojunction Bipolar Transistor (HBT)
Materials described outside the worked examples.
semi-insulating InP substrate
InP
P-type GaAsSb base layer
GaAsSb
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 23. As shown in FIGs. 18-23, the substrate 50 has the same thickness at locations under the emitter-up HBT 10 and the emitter-down HBT 11. The substrate …
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,697,532Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 depicts a side view of an emitter-up HBT; [0010]
FIG. 2 depicts a side view of an emitter-down HBT; [0011]
FIG. 3 depicts a wafer with HBTs on the wafer; [0012]
FIGS. 4-23 depict a process of forming HBTs based on an exemplary embodiment; [0013]
FIG. 5, layer 70 may be formed, for example, by epitaxial growth, on top of the layer 60. The layer 70 may comprise, for example, N-type I nP (N-) undoped …
FIG. 6; 2) performing ion implantation until region 75 is formed, as shown in
FIG. 7; 3) removing implant mask 71 and annealing the structure in
FIG. 8 for implant activation and damage removal wherein N region 75 is formed. [0022] This disclosure is not limited to a shape of implant region 75 as …
FIG. 9; 2) performing ion implantation until regions 78 are formed, as shown in
FIG. 10; 3) removing implant mask 72, as shown in
FIG. 11. This disclosure is not limited to shape of implant isolation regions 78 as depicted in
FIG. 12, a base layer 80 may be formed, for example, by epitaxial growth, on top of the layer 70 or on top of the optional layer referred to above. The base …
FIG. 13, a layer 90 may be formed, for example by epitaxial growth, on top of the base layer 80. The layer 90 may comprise, for example, N- type I nP (N) …
FIG. 14, a layer 100 may be formed, for example by epitaxial growth. The emitter cap layer 9 may comprise, for example, N-type I nGaAs (N +) material that is …
FIG. 15; 2) performing ion implantation until region 95 may be formed, as shown in
FIG. 16; 3) removing implant mask 91 and performing rapid thermal annealing of the structure in
FIG. 17 for implant activation and damage removal wherein N + region 95 may be formed. [0032] I on implantation of region 95 may be performed on layer 90 prior …
FIG. 18; etching emitter mesas 150 for emitter-up HBT 10 and collector mesas 160 for emitter-down HBT 11, as shown in
FIG. 19; providing base metal contacts 120 through lithography and metal deposition, as shown in
FIG. 20; etching base mesas 170, as shown in
FIG. 21; providing metal contacts 130 through lithography and metal deposition, as shown in
FIG. 22; and etching isolation mesas 180, as shown in
FIG. 23. As shown in FIGs. 18-23, the substrate 50 has the same thickness at locations under the emitter-up HBT 10 and the emitter-down HBT 11. The substrate …
FIGS. 24-29 depict a process of forming HBTs based on another exemplary embodiment.
FIG. 25, emitter mesas 210 for emitter-up HBT 10 and collector mesas 220 for emitter-down HBT 11 may be etched. Using metal contacts 110 as a mask, etching of …
FIG. 26, layer 200 may be formed to at least partially cover metal contacts 110. Layer 200 may comprise, for example, positive tone photo definable polyimide …
FIG. 27, layer 200 may be soft baked, may be flood exposed (maskless) and may be developed so as to remove most of the exposed layer 200 material except for the …
FIGS. 28-29, formation of self-aligned metal contacts 120 may be performed by: providing a photoresist layer 205 (patterned for base contact metal) so as to …
FIG. 29; removing any metal flaxes that may be deposited on portions 201, 202, 203, 204 by performing slight Argon (Ar) ion milling etch process. [0040] The …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A wafer comprising: an InP based semiconductor substrate; at least one emitter-up Heterojunction Bipolar Transistor (HBT), wherein a collector layer is disposed between a base layer and a substrate; and at least one emitter-down HBT, wherein an emitter layer is disposed between a base layer and a substrate. withdrawn
The wafer as claimed in Claim 1 wherein said at least one emitter-down HBT comprises a plurality of ion implanted regions in said emitter layer. withdrawn
The wafer as claimed in Claim 1 wherein said at least one emitter-up HBT comprises an ion implanted region in said emitter layer. withdrawn
An Integrated Circuit (IC) comprising: an InP based semiconductor substrate; at least one emitter-up Heterojunction Bipolar Transistor (HBT), wherein a collector layer is disposed between a base layer and a substrate; and Application No: 12/616,374 Page 3 at least one emitter-down HBT, wherein an emitter layer is disposed between a base layer and a substrate. withdrawn
The IC as claimed in Claim 7 wherein said at least one emitter-down HBT comprises a plurality of ion implanted region in said emitter layer. withdrawn
The IC as claimed in Claim 7 wherein said at least one emitter-up HBT comprises an ion implanted region in said emitter layer. withdrawn
A wafer comprising: at least one emitter-up Heterojunction Bipolar Transistor (HBT) comprising: an InP based semiconductor substrate; a sub-collector layer formed on said substrate; a collector layer formed on said sub-collector layer; a base layer formed on said collector layer; an emitter layer formed on said base layer; an emitter cap layer formed on said emitter layer; an electrically conducting emitter contact formed on said emitter cap layer; an electrically conducting base contact formed on said base layer; and an electrically conducting collector contact formed on said sub-collector layer; at least one emitter-down HBT comprising an InP based semiconductor substrate; Application No: 12/616,374 Page 4 a sub-emitter layer formed on said substrate; an emitter layer formed on said sub-emitter layer; a plurality of implant regions within said emitter layer; a base layer formed on said emitter layer; a collector layer formed on said base layer; a collector cap formed on said collector layer; an electrically conducting collector contact formed on said collector cap; an electrically conducting base contact formed on said base layer; and an electrically conducting emitter contact formed on said sub-emitter layer. withdrawn
The wafer as claimed in Claim 13 wherein at least one of said plurality of ion implanted regions is annealed for doping activation. withdrawn
The wafer as claimed in Claim 13 wherein said at least one emitter-up HBT comprises an ion implanted region in said emitter layer. withdrawn
An integrated circuit comprising: an emitter-up Hetero-junction Bipolar Transistor (HBT) on a first location on a substrate comprising: an undoped collector layer over the substrate; a base layer over the undoped collector layer; and an emitter layer over the first portion of the base layer; and an emitter-down HBT on a second location on the substrate, wherein the substrate is of equal thickness at the first location and the second location, the emitter-down HBT comprising: a first ion implant in the undoped collector layer to provide an intrinsic emitter; Application No: 12/616,374 Page 5 a second ion implant in the undoped collector layer adjacent to the first ion implant to prevent parasitic current injection through an extrinsic base emitter junction area under forward bias; the base layer over the first and second ion implants; and the emitter layer over the base layer to provide a collector for the emitter-down HBT. withdrawn
The integrated circuit of claim 18 wherein the substrate comprises a semi- insulating InP wafer. withdrawn
The integrated circuit of claim 18 wherein the undoped collector layer comprises N-type InP (N) undoped material. withdrawn
The integrated circuit of claim 18 wherein a thickness of the undoped collector layer is selected to obtain a desired BVceo. withdrawn
The integrated circuit of claim 18 wherein the base layer comprises P-type GaAsSb (P+) material. withdrawn
The integrated circuit of claim 18 wherein the emitter layer comprises N-type InP (N) material. withdrawn
The integrated circuit of claim 18 wherein the emitter-up HBT f u rther comprises a third ion implant in the emitter layer. withdrawn
The integrated circuit of claim 18 wherein: the emitter-up HBT f u rther comprises: an emitter mesa; a first base mesa; and a first isolation mesa; and forming the emitter-down HBT f u rther comprises: Application No: 12/616,374 Page 6 a collector mesa; a second base mesa; and a second isolation mesa. withdrawn
The integrated circuit of claim 18 wherein: the emitter-up HBT f u rther comprises: an emitter mesa; an emitter metal contact overhanging the emitter mesa; and a self aligned base metal contact. withdrawn
The integrated circuit of claim 18 wherein: the substrate comprises a semi-insulating InP wafer; the undoped collector layer comprises N-type InP (N) undoped material; the base layer comprises P-type GaAsSb (P+) material; and the emitter layer comprises N-type InP (N) material. withdrawn
The integrated circuit of claim 18 wherein: the emitter-up HBT has a high BV c eo; and the emitter-down HBT has a high Ft. withdrawn
A method of forming an emitter-up Heterojunction Bipolar Transistor (HBT) and an emitter-down HBT on a single wafer, said method comprising: providing a semiconductor substrate; forming a sub-layer over the substrate that f u nctions as a sub-collector layer for the emitter up HBT and that f u nctions as a sub-emitter for the emitter down HBT; forming a collector layer disposed over the sub-layer; implanting ions into a portion of the collector layer to form a first implant region for forming an emitter for the emitter-down HBT; annealing the first implant region; implanting ions into second regions in the collector layer, the second implant regions on either side of and directly adjacent to the first implant region, and the second implant regions Application No: 12/616,374 Page 7 forming isolation regions for preventing parasitic current injection through an extrinsic base emitter junction area under forward bias, wherein the second implant regions do not extend into h-eu gh the sub-layer int- the substrae; forming a base layer disposed over the collector layer and over the first and second implant regions; and forming an emitter layer above the base layer that functions as an emitter layer for the emitter-up HBT, and that functions as a collector layer for the emitter-down HBT.
The method of Claim 29 wherein implanting ions into the portion of the collector layer comprises: applying and forming an implant mask to said collector layer to expose only said portion of said collector layer; implanting the first implant region in said collector layer.
The method of Claim 29 wherein forming the emitter layer above the base layer further comprises: implanting ions in a portion of said emitter layer to form a third implant region in said emitter layer for the emitter-up HBT
The method of Claim 29 further comprising: forming a first metal contact on at least one of the HBTs; forming a first mesa for the at least one of the HBTs so that said first metal contact overhangs said first mesa; Application No: 12/616,374 Page 8 forming a photo sensitive dielectric layer to at least partially cover said first metal contact; flood exposing said photo sensitive dielectric layer; developing said photo sensitive dielectric layer to remove most of said photo sensitive layer, wherein portions of said photo sensitive dielectric layer remain under said overhang of said first metal contact; forming self-aligned metal contacts. withdrawn
The method of Claim 29, wherein annealing the first implant region is done before forming the second implant regions.
The method of Claim 29, wherein annealing the first implant region is done after forming the first implant region and the second implant regions.
The method of Claim 29, wherein the first implant region is between the second implant regions.
The method of Claim 29, wherein the first implant region is physically contacting at least one of the second implant regions.
The method of Claim 29, wherein the second implant regions are at least partially covered by the base layer.
The method of Claim 29, wherein the first implant region and the second implant regions are associated with the emitter-down HBT.
The method of Claim 29, wherein the first implant region is an N- doped region.
The method of claim 29 wherein: the substrate comprises a semi-insulating InP wafer; the collector layer comprises N-type InP (N-) undoped material; Application No: 12/616,374 Page the base layer comprises P-type GaAsSb (P+) material; and the emitter layer comprises N-type InP (N) material.
The method of claim 29 further comprising forming the collector layer to have a thickness to obtain a BVceo for the emitter-up HBT.
The method of claim 29 wherein ions are implanted into the first implant region before implanting ions to form the second implant regions.
The method of claim 29 wherein ions are implanted into the second implant regions before implanting ions to form the first implant region.
The method of claim 29 wherein the sub-layer heavily doped with silicon or N-type InP (N+)
The method of claim 29 wherein the sub-layer angstroms.
The method of claim 29 wherein the sub-layer the emitter-down HBT. comprises N-type InGasAs (N+) material material heavily doped with silicon. has a thickness from 100 angstroms to 5000 is contiguous between the emitter-up HBT and
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A method of forming an emitter-up Heterojunction Bipolar Transistor (HBT) and an emitter-down HBT on a wafer, said method comprising: providing an InP based semiconductor substrate; forming a plurality of layers on said substrate; forming a first metal contact on a top layer of said plurality of layers for at least one HBT on said substrate; forming a first mesa so that said first metal contact overhangs said mesa for said at least one HBT on said substrate; forming a photo sensitive dielectric layer so as to at least partially cover said first metal contact on said substrate; flood exposing said photo sensitive dielectric layer; developing said photo sensitive dielectric layer so as to remove most of said photo sensitive dielectric layer, wherein portions of said photo sensitive dielectric layer remain under said overhang of said first metal contact; forming self-aligned metal contacts. withdrawn
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Layer stacks claimed or described, ordered top of device to substrate.
emitter-up Heterojunction Bipolar Transistor (HBT)
Materials described outside the worked examples.
semi-insulating InP substrate
InP
P-type GaAsSb base layer
GaAsSb
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 23. As shown in FIGs. 18-23, the substrate 50 has the same thickness at locations under the emitter-up HBT 10 and the emitter-down HBT 11. The substrate …
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,697,532Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 depicts a side view of an emitter-up HBT; [0010]
FIG. 2 depicts a side view of an emitter-down HBT; [0011]
FIG. 3 depicts a wafer with HBTs on the wafer; [0012]
FIGS. 4-23 depict a process of forming HBTs based on an exemplary embodiment; [0013]
FIG. 5, layer 70 may be formed, for example, by epitaxial growth, on top of the layer 60. The layer 70 may comprise, for example, N-type I nP (N-) undoped …
FIG. 6; 2) performing ion implantation until region 75 is formed, as shown in
FIG. 7; 3) removing implant mask 71 and annealing the structure in
FIG. 8 for implant activation and damage removal wherein N region 75 is formed. [0022] This disclosure is not limited to a shape of implant region 75 as …
FIG. 9; 2) performing ion implantation until regions 78 are formed, as shown in
FIG. 10; 3) removing implant mask 72, as shown in
FIG. 11. This disclosure is not limited to shape of implant isolation regions 78 as depicted in
FIG. 12, a base layer 80 may be formed, for example, by epitaxial growth, on top of the layer 70 or on top of the optional layer referred to above. The base …
FIG. 13, a layer 90 may be formed, for example by epitaxial growth, on top of the base layer 80. The layer 90 may comprise, for example, N- type I nP (N) …
FIG. 14, a layer 100 may be formed, for example by epitaxial growth. The emitter cap layer 9 may comprise, for example, N-type I nGaAs (N +) material that is …
FIG. 15; 2) performing ion implantation until region 95 may be formed, as shown in
FIG. 16; 3) removing implant mask 91 and performing rapid thermal annealing of the structure in
FIG. 17 for implant activation and damage removal wherein N + region 95 may be formed. [0032] I on implantation of region 95 may be performed on layer 90 prior …
FIG. 18; etching emitter mesas 150 for emitter-up HBT 10 and collector mesas 160 for emitter-down HBT 11, as shown in
FIG. 19; providing base metal contacts 120 through lithography and metal deposition, as shown in
FIG. 20; etching base mesas 170, as shown in
FIG. 21; providing metal contacts 130 through lithography and metal deposition, as shown in
FIG. 22; and etching isolation mesas 180, as shown in
FIG. 23. As shown in FIGs. 18-23, the substrate 50 has the same thickness at locations under the emitter-up HBT 10 and the emitter-down HBT 11. The substrate …
FIGS. 24-29 depict a process of forming HBTs based on another exemplary embodiment.
FIG. 25, emitter mesas 210 for emitter-up HBT 10 and collector mesas 220 for emitter-down HBT 11 may be etched. Using metal contacts 110 as a mask, etching of …
FIG. 26, layer 200 may be formed to at least partially cover metal contacts 110. Layer 200 may comprise, for example, positive tone photo definable polyimide …
FIG. 27, layer 200 may be soft baked, may be flood exposed (maskless) and may be developed so as to remove most of the exposed layer 200 material except for the …
FIGS. 28-29, formation of self-aligned metal contacts 120 may be performed by: providing a photoresist layer 205 (patterned for base contact metal) so as to …
FIG. 29; removing any metal flaxes that may be deposited on portions 201, 202, 203, 204 by performing slight Argon (Ar) ion milling etch process. [0040] The …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A wafer comprising: an InP based semiconductor substrate; at least one emitter-up Heterojunction Bipolar Transistor (HBT), wherein a collector layer is disposed between a base layer and a substrate; and at least one emitter-down HBT, wherein an emitter layer is disposed between a base layer and a substrate. withdrawn
The wafer as claimed in Claim 1 wherein said at least one emitter-down HBT comprises a plurality of ion implanted regions in said emitter layer. withdrawn
The wafer as claimed in Claim 1 wherein said at least one emitter-up HBT comprises an ion implanted region in said emitter layer. withdrawn
An Integrated Circuit (IC) comprising: an InP based semiconductor substrate; at least one emitter-up Heterojunction Bipolar Transistor (HBT), wherein a collector layer is disposed between a base layer and a substrate; and Application No: 12/616,374 Page 3 at least one emitter-down HBT, wherein an emitter layer is disposed between a base layer and a substrate. withdrawn
The IC as claimed in Claim 7 wherein said at least one emitter-down HBT comprises a plurality of ion implanted region in said emitter layer. withdrawn
The IC as claimed in Claim 7 wherein said at least one emitter-up HBT comprises an ion implanted region in said emitter layer. withdrawn
A wafer comprising: at least one emitter-up Heterojunction Bipolar Transistor (HBT) comprising: an InP based semiconductor substrate; a sub-collector layer formed on said substrate; a collector layer formed on said sub-collector layer; a base layer formed on said collector layer; an emitter layer formed on said base layer; an emitter cap layer formed on said emitter layer; an electrically conducting emitter contact formed on said emitter cap layer; an electrically conducting base contact formed on said base layer; and an electrically conducting collector contact formed on said sub-collector layer; at least one emitter-down HBT comprising an InP based semiconductor substrate; Application No: 12/616,374 Page 4 a sub-emitter layer formed on said substrate; an emitter layer formed on said sub-emitter layer; a plurality of implant regions within said emitter layer; a base layer formed on said emitter layer; a collector layer formed on said base layer; a collector cap formed on said collector layer; an electrically conducting collector contact formed on said collector cap; an electrically conducting base contact formed on said base layer; and an electrically conducting emitter contact formed on said sub-emitter layer. withdrawn
The wafer as claimed in Claim 13 wherein at least one of said plurality of ion implanted regions is annealed for doping activation. withdrawn
The wafer as claimed in Claim 13 wherein said at least one emitter-up HBT comprises an ion implanted region in said emitter layer. withdrawn
An integrated circuit comprising: an emitter-up Hetero-junction Bipolar Transistor (HBT) on a first location on a substrate comprising: an undoped collector layer over the substrate; a base layer over the undoped collector layer; and an emitter layer over the first portion of the base layer; and an emitter-down HBT on a second location on the substrate, wherein the substrate is of equal thickness at the first location and the second location, the emitter-down HBT comprising: a first ion implant in the undoped collector layer to provide an intrinsic emitter; Application No: 12/616,374 Page 5 a second ion implant in the undoped collector layer adjacent to the first ion implant to prevent parasitic current injection through an extrinsic base emitter junction area under forward bias; the base layer over the first and second ion implants; and the emitter layer over the base layer to provide a collector for the emitter-down HBT. withdrawn
The integrated circuit of claim 18 wherein the substrate comprises a semi- insulating InP wafer. withdrawn
The integrated circuit of claim 18 wherein the undoped collector layer comprises N-type InP (N) undoped material. withdrawn
The integrated circuit of claim 18 wherein a thickness of the undoped collector layer is selected to obtain a desired BVceo. withdrawn
The integrated circuit of claim 18 wherein the base layer comprises P-type GaAsSb (P+) material. withdrawn
The integrated circuit of claim 18 wherein the emitter layer comprises N-type InP (N) material. withdrawn
The integrated circuit of claim 18 wherein the emitter-up HBT f u rther comprises a third ion implant in the emitter layer. withdrawn
The integrated circuit of claim 18 wherein: the emitter-up HBT f u rther comprises: an emitter mesa; a first base mesa; and a first isolation mesa; and forming the emitter-down HBT f u rther comprises: Application No: 12/616,374 Page 6 a collector mesa; a second base mesa; and a second isolation mesa. withdrawn
The integrated circuit of claim 18 wherein: the emitter-up HBT f u rther comprises: an emitter mesa; an emitter metal contact overhanging the emitter mesa; and a self aligned base metal contact. withdrawn
The integrated circuit of claim 18 wherein: the substrate comprises a semi-insulating InP wafer; the undoped collector layer comprises N-type InP (N) undoped material; the base layer comprises P-type GaAsSb (P+) material; and the emitter layer comprises N-type InP (N) material. withdrawn
The integrated circuit of claim 18 wherein: the emitter-up HBT has a high BV c eo; and the emitter-down HBT has a high Ft. withdrawn
A method of forming an emitter-up Heterojunction Bipolar Transistor (HBT) and an emitter-down HBT on a single wafer, said method comprising: providing a semiconductor substrate; forming a sub-layer over the substrate that f u nctions as a sub-collector layer for the emitter up HBT and that f u nctions as a sub-emitter for the emitter down HBT; forming a collector layer disposed over the sub-layer; implanting ions into a portion of the collector layer to form a first implant region for forming an emitter for the emitter-down HBT; annealing the first implant region; implanting ions into second regions in the collector layer, the second implant regions on either side of and directly adjacent to the first implant region, and the second implant regions Application No: 12/616,374 Page 7 forming isolation regions for preventing parasitic current injection through an extrinsic base emitter junction area under forward bias, wherein the second implant regions do not extend into h-eu gh the sub-layer int- the substrae; forming a base layer disposed over the collector layer and over the first and second implant regions; and forming an emitter layer above the base layer that functions as an emitter layer for the emitter-up HBT, and that functions as a collector layer for the emitter-down HBT.
The method of Claim 29 wherein implanting ions into the portion of the collector layer comprises: applying and forming an implant mask to said collector layer to expose only said portion of said collector layer; implanting the first implant region in said collector layer.
The method of Claim 29 wherein forming the emitter layer above the base layer further comprises: implanting ions in a portion of said emitter layer to form a third implant region in said emitter layer for the emitter-up HBT
The method of Claim 29 further comprising: forming a first metal contact on at least one of the HBTs; forming a first mesa for the at least one of the HBTs so that said first metal contact overhangs said first mesa; Application No: 12/616,374 Page 8 forming a photo sensitive dielectric layer to at least partially cover said first metal contact; flood exposing said photo sensitive dielectric layer; developing said photo sensitive dielectric layer to remove most of said photo sensitive layer, wherein portions of said photo sensitive dielectric layer remain under said overhang of said first metal contact; forming self-aligned metal contacts. withdrawn
The method of Claim 29, wherein annealing the first implant region is done before forming the second implant regions.
The method of Claim 29, wherein annealing the first implant region is done after forming the first implant region and the second implant regions.
The method of Claim 29, wherein the first implant region is between the second implant regions.
The method of Claim 29, wherein the first implant region is physically contacting at least one of the second implant regions.
The method of Claim 29, wherein the second implant regions are at least partially covered by the base layer.
The method of Claim 29, wherein the first implant region and the second implant regions are associated with the emitter-down HBT.
The method of Claim 29, wherein the first implant region is an N- doped region.
The method of claim 29 wherein: the substrate comprises a semi-insulating InP wafer; the collector layer comprises N-type InP (N-) undoped material; Application No: 12/616,374 Page the base layer comprises P-type GaAsSb (P+) material; and the emitter layer comprises N-type InP (N) material.
The method of claim 29 further comprising forming the collector layer to have a thickness to obtain a BVceo for the emitter-up HBT.
The method of claim 29 wherein ions are implanted into the first implant region before implanting ions to form the second implant regions.
The method of claim 29 wherein ions are implanted into the second implant regions before implanting ions to form the first implant region.
The method of claim 29 wherein the sub-layer heavily doped with silicon or N-type InP (N+)
The method of claim 29 wherein the sub-layer angstroms.
The method of claim 29 wherein the sub-layer the emitter-down HBT. comprises N-type InGasAs (N+) material material heavily doped with silicon. has a thickness from 100 angstroms to 5000 is contiguous between the emitter-up HBT and
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A method of forming an emitter-up Heterojunction Bipolar Transistor (HBT) and an emitter-down HBT on a wafer, said method comprising: providing an InP based semiconductor substrate; forming a plurality of layers on said substrate; forming a first metal contact on a top layer of said plurality of layers for at least one HBT on said substrate; forming a first mesa so that said first metal contact overhangs said mesa for said at least one HBT on said substrate; forming a photo sensitive dielectric layer so as to at least partially cover said first metal contact on said substrate; flood exposing said photo sensitive dielectric layer; developing said photo sensitive dielectric layer so as to remove most of said photo sensitive dielectric layer, wherein portions of said photo sensitive dielectric layer remain under said overhang of said first metal contact; forming self-aligned metal contacts. withdrawn
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Layer stacks claimed or described, ordered top of device to substrate.
emitter-up Heterojunction Bipolar Transistor (HBT)
Materials described outside the worked examples.
semi-insulating InP substrate
InP
P-type GaAsSb base layer
GaAsSb
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 23. As shown in FIGs. 18-23, the substrate 50 has the same thickness at locations under the emitter-up HBT 10 and the emitter-down HBT 11. The substrate …
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US 8,697,532Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 depicts a side view of an emitter-up HBT; [0010]
FIG. 2 depicts a side view of an emitter-down HBT; [0011]
FIG. 3 depicts a wafer with HBTs on the wafer; [0012]
FIGS. 4-23 depict a process of forming HBTs based on an exemplary embodiment; [0013]
FIG. 5, layer 70 may be formed, for example, by epitaxial growth, on top of the layer 60. The layer 70 may comprise, for example, N-type I nP (N-) undoped …
FIG. 6; 2) performing ion implantation until region 75 is formed, as shown in
FIG. 7; 3) removing implant mask 71 and annealing the structure in
FIG. 8 for implant activation and damage removal wherein N region 75 is formed. [0022] This disclosure is not limited to a shape of implant region 75 as …
FIG. 9; 2) performing ion implantation until regions 78 are formed, as shown in
FIG. 10; 3) removing implant mask 72, as shown in
FIG. 11. This disclosure is not limited to shape of implant isolation regions 78 as depicted in
FIG. 12, a base layer 80 may be formed, for example, by epitaxial growth, on top of the layer 70 or on top of the optional layer referred to above. The base …
FIG. 13, a layer 90 may be formed, for example by epitaxial growth, on top of the base layer 80. The layer 90 may comprise, for example, N- type I nP (N) …
FIG. 14, a layer 100 may be formed, for example by epitaxial growth. The emitter cap layer 9 may comprise, for example, N-type I nGaAs (N +) material that is …
FIG. 15; 2) performing ion implantation until region 95 may be formed, as shown in
FIG. 16; 3) removing implant mask 91 and performing rapid thermal annealing of the structure in
FIG. 17 for implant activation and damage removal wherein N + region 95 may be formed. [0032] I on implantation of region 95 may be performed on layer 90 prior …
FIG. 18; etching emitter mesas 150 for emitter-up HBT 10 and collector mesas 160 for emitter-down HBT 11, as shown in
FIG. 19; providing base metal contacts 120 through lithography and metal deposition, as shown in
FIG. 20; etching base mesas 170, as shown in
FIG. 21; providing metal contacts 130 through lithography and metal deposition, as shown in
FIG. 22; and etching isolation mesas 180, as shown in
FIG. 23. As shown in FIGs. 18-23, the substrate 50 has the same thickness at locations under the emitter-up HBT 10 and the emitter-down HBT 11. The substrate …
FIGS. 24-29 depict a process of forming HBTs based on another exemplary embodiment.
FIG. 25, emitter mesas 210 for emitter-up HBT 10 and collector mesas 220 for emitter-down HBT 11 may be etched. Using metal contacts 110 as a mask, etching of …
FIG. 26, layer 200 may be formed to at least partially cover metal contacts 110. Layer 200 may comprise, for example, positive tone photo definable polyimide …
FIG. 27, layer 200 may be soft baked, may be flood exposed (maskless) and may be developed so as to remove most of the exposed layer 200 material except for the …
FIGS. 28-29, formation of self-aligned metal contacts 120 may be performed by: providing a photoresist layer 205 (patterned for base contact metal) so as to …
FIG. 29; removing any metal flaxes that may be deposited on portions 201, 202, 203, 204 by performing slight Argon (Ar) ion milling etch process. [0040] The …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A wafer comprising: an InP based semiconductor substrate; at least one emitter-up Heterojunction Bipolar Transistor (HBT), wherein a collector layer is disposed between a base layer and a substrate; and at least one emitter-down HBT, wherein an emitter layer is disposed between a base layer and a substrate. withdrawn
The wafer as claimed in Claim 1 wherein said at least one emitter-down HBT comprises a plurality of ion implanted regions in said emitter layer. withdrawn
The wafer as claimed in Claim 1 wherein said at least one emitter-up HBT comprises an ion implanted region in said emitter layer. withdrawn
An Integrated Circuit (IC) comprising: an InP based semiconductor substrate; at least one emitter-up Heterojunction Bipolar Transistor (HBT), wherein a collector layer is disposed between a base layer and a substrate; and Application No: 12/616,374 Page 3 at least one emitter-down HBT, wherein an emitter layer is disposed between a base layer and a substrate. withdrawn
The IC as claimed in Claim 7 wherein said at least one emitter-down HBT comprises a plurality of ion implanted region in said emitter layer. withdrawn
The IC as claimed in Claim 7 wherein said at least one emitter-up HBT comprises an ion implanted region in said emitter layer. withdrawn
A wafer comprising: at least one emitter-up Heterojunction Bipolar Transistor (HBT) comprising: an InP based semiconductor substrate; a sub-collector layer formed on said substrate; a collector layer formed on said sub-collector layer; a base layer formed on said collector layer; an emitter layer formed on said base layer; an emitter cap layer formed on said emitter layer; an electrically conducting emitter contact formed on said emitter cap layer; an electrically conducting base contact formed on said base layer; and an electrically conducting collector contact formed on said sub-collector layer; at least one emitter-down HBT comprising an InP based semiconductor substrate; Application No: 12/616,374 Page 4 a sub-emitter layer formed on said substrate; an emitter layer formed on said sub-emitter layer; a plurality of implant regions within said emitter layer; a base layer formed on said emitter layer; a collector layer formed on said base layer; a collector cap formed on said collector layer; an electrically conducting collector contact formed on said collector cap; an electrically conducting base contact formed on said base layer; and an electrically conducting emitter contact formed on said sub-emitter layer. withdrawn
The wafer as claimed in Claim 13 wherein at least one of said plurality of ion implanted regions is annealed for doping activation. withdrawn
The wafer as claimed in Claim 13 wherein said at least one emitter-up HBT comprises an ion implanted region in said emitter layer. withdrawn
An integrated circuit comprising: an emitter-up Hetero-junction Bipolar Transistor (HBT) on a first location on a substrate comprising: an undoped collector layer over the substrate; a base layer over the undoped collector layer; and an emitter layer over the first portion of the base layer; and an emitter-down HBT on a second location on the substrate, wherein the substrate is of equal thickness at the first location and the second location, the emitter-down HBT comprising: a first ion implant in the undoped collector layer to provide an intrinsic emitter; Application No: 12/616,374 Page 5 a second ion implant in the undoped collector layer adjacent to the first ion implant to prevent parasitic current injection through an extrinsic base emitter junction area under forward bias; the base layer over the first and second ion implants; and the emitter layer over the base layer to provide a collector for the emitter-down HBT. withdrawn
The integrated circuit of claim 18 wherein the substrate comprises a semi- insulating InP wafer. withdrawn
The integrated circuit of claim 18 wherein the undoped collector layer comprises N-type InP (N) undoped material. withdrawn
The integrated circuit of claim 18 wherein a thickness of the undoped collector layer is selected to obtain a desired BVceo. withdrawn
The integrated circuit of claim 18 wherein the base layer comprises P-type GaAsSb (P+) material. withdrawn
The integrated circuit of claim 18 wherein the emitter layer comprises N-type InP (N) material. withdrawn
The integrated circuit of claim 18 wherein the emitter-up HBT f u rther comprises a third ion implant in the emitter layer. withdrawn
The integrated circuit of claim 18 wherein: the emitter-up HBT f u rther comprises: an emitter mesa; a first base mesa; and a first isolation mesa; and forming the emitter-down HBT f u rther comprises: Application No: 12/616,374 Page 6 a collector mesa; a second base mesa; and a second isolation mesa. withdrawn
The integrated circuit of claim 18 wherein: the emitter-up HBT f u rther comprises: an emitter mesa; an emitter metal contact overhanging the emitter mesa; and a self aligned base metal contact. withdrawn
The integrated circuit of claim 18 wherein: the substrate comprises a semi-insulating InP wafer; the undoped collector layer comprises N-type InP (N) undoped material; the base layer comprises P-type GaAsSb (P+) material; and the emitter layer comprises N-type InP (N) material. withdrawn
The integrated circuit of claim 18 wherein: the emitter-up HBT has a high BV c eo; and the emitter-down HBT has a high Ft. withdrawn
A method of forming an emitter-up Heterojunction Bipolar Transistor (HBT) and an emitter-down HBT on a single wafer, said method comprising: providing a semiconductor substrate; forming a sub-layer over the substrate that f u nctions as a sub-collector layer for the emitter up HBT and that f u nctions as a sub-emitter for the emitter down HBT; forming a collector layer disposed over the sub-layer; implanting ions into a portion of the collector layer to form a first implant region for forming an emitter for the emitter-down HBT; annealing the first implant region; implanting ions into second regions in the collector layer, the second implant regions on either side of and directly adjacent to the first implant region, and the second implant regions Application No: 12/616,374 Page 7 forming isolation regions for preventing parasitic current injection through an extrinsic base emitter junction area under forward bias, wherein the second implant regions do not extend into h-eu gh the sub-layer int- the substrae; forming a base layer disposed over the collector layer and over the first and second implant regions; and forming an emitter layer above the base layer that functions as an emitter layer for the emitter-up HBT, and that functions as a collector layer for the emitter-down HBT.
The method of Claim 29 wherein implanting ions into the portion of the collector layer comprises: applying and forming an implant mask to said collector layer to expose only said portion of said collector layer; implanting the first implant region in said collector layer.
The method of Claim 29 wherein forming the emitter layer above the base layer further comprises: implanting ions in a portion of said emitter layer to form a third implant region in said emitter layer for the emitter-up HBT
The method of Claim 29 further comprising: forming a first metal contact on at least one of the HBTs; forming a first mesa for the at least one of the HBTs so that said first metal contact overhangs said first mesa; Application No: 12/616,374 Page 8 forming a photo sensitive dielectric layer to at least partially cover said first metal contact; flood exposing said photo sensitive dielectric layer; developing said photo sensitive dielectric layer to remove most of said photo sensitive layer, wherein portions of said photo sensitive dielectric layer remain under said overhang of said first metal contact; forming self-aligned metal contacts. withdrawn
The method of Claim 29, wherein annealing the first implant region is done before forming the second implant regions.
The method of Claim 29, wherein annealing the first implant region is done after forming the first implant region and the second implant regions.
The method of Claim 29, wherein the first implant region is between the second implant regions.
The method of Claim 29, wherein the first implant region is physically contacting at least one of the second implant regions.
The method of Claim 29, wherein the second implant regions are at least partially covered by the base layer.
The method of Claim 29, wherein the first implant region and the second implant regions are associated with the emitter-down HBT.
The method of Claim 29, wherein the first implant region is an N- doped region.
The method of claim 29 wherein: the substrate comprises a semi-insulating InP wafer; the collector layer comprises N-type InP (N-) undoped material; Application No: 12/616,374 Page the base layer comprises P-type GaAsSb (P+) material; and the emitter layer comprises N-type InP (N) material.
The method of claim 29 further comprising forming the collector layer to have a thickness to obtain a BVceo for the emitter-up HBT.
The method of claim 29 wherein ions are implanted into the first implant region before implanting ions to form the second implant regions.
The method of claim 29 wherein ions are implanted into the second implant regions before implanting ions to form the first implant region.
The method of claim 29 wherein the sub-layer heavily doped with silicon or N-type InP (N+)
The method of claim 29 wherein the sub-layer angstroms.
The method of claim 29 wherein the sub-layer the emitter-down HBT. comprises N-type InGasAs (N+) material material heavily doped with silicon. has a thickness from 100 angstroms to 5000 is contiguous between the emitter-up HBT and
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A method of forming an emitter-up Heterojunction Bipolar Transistor (HBT) and an emitter-down HBT on a wafer, said method comprising: providing an InP based semiconductor substrate; forming a plurality of layers on said substrate; forming a first metal contact on a top layer of said plurality of layers for at least one HBT on said substrate; forming a first mesa so that said first metal contact overhangs said mesa for said at least one HBT on said substrate; forming a photo sensitive dielectric layer so as to at least partially cover said first metal contact on said substrate; flood exposing said photo sensitive dielectric layer; developing said photo sensitive dielectric layer so as to remove most of said photo sensitive dielectric layer, wherein portions of said photo sensitive dielectric layer remain under said overhang of said first metal contact; forming self-aligned metal contacts. withdrawn
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Layer stacks claimed or described, ordered top of device to substrate.
emitter-up Heterojunction Bipolar Transistor (HBT)
Materials described outside the worked examples.
semi-insulating InP substrate
InP
P-type GaAsSb base layer
GaAsSb
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 23. As shown in FIGs. 18-23, the substrate 50 has the same thickness at locations under the emitter-up HBT 10 and the emitter-down HBT 11. The substrate …
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