Patent
US 11,276,694TRANSISTOR STRUCTURE WITH INDIUM PHOSPHIDE CHANNEL
Willy Rachmady
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 11,276,694Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 1. In these example embodiments, the transistor structure 100 has a nanowire or nanoribbon configuration. The transistor structure 100 is formed on a …
FIG. 2 shows a section taken through the gate structure 140 and perpendicular to the channel regions 130 of two devices. The gate structure 140 includes a gate …
FIG. 3, the buffer 112 includes a plurality of layers of buffer material. For example, the buffer 112 includes a first layer 11 4a of buffer material of GaP. This …
FIG. 4, a flowchart illustrates a process flow for a method 400 of forming an integrated circuit that includes one or more nanowire or nanoribbon transistor, in …
FIG. 5 after processing the superlattice into fins, in accordance with an embodiment of the present disclosure. [0009] FIGURE 7 illustrates a perspective view …
FIG. 6 after forming a dummy gate structure on the fins, in accordance with an embodiment of the present disclosure. [0010] FIGURE 8 illustrates a perspective …
FIG. 7 after recessing the fins adjacent the gate structure, in accordance with an embodiment of the present disclosure. [0011] FIGURE 9 illustrates a …
FIG. 8 after epitaxial growth of replacement source and drains from the exposed channel material, in accordance with an embodiment of the present disclosure. …
FIG. 9 after removing the dummy gate electrode and releasing nanowires in the channel region, in accordance with an embodiment of the present disclosure. …
FIG. 10 after replacement gate processing, in accordance with an embodiment of the present disclosure. [0014] FIGURE 12 illustrates a perspective view of a …
FIG. 11 after processing the source and drain contacts, in accordance with an embodiment of the present disclosure. [0015] FIGURE 13 illustrates an example …
FIG. 12 illustrates a perspective view of an example transistor structure 100 with S/D contacts 126 formed on the S/D 120, in accordance with some embodiments. …
FIG. 13 illustrates a computing system 1000 implemented with integrated circuit structures and/or transistor devices formed using the techniques disclosed …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit with at least one transistor, the integrated circuit comprising: a substrate comprising silicon; a buffer structure on the substrate, the buffer structure including one or more layers of buffer material comprising indium, gallium, and phosphorous, wherein a ratio of indium to gallium in the one or more layers of buffer material increases from a first value of 0.35 or less to a second value of at least 2; a source and a drain on top of the buffer structure; a body of Group I II -V semiconductor material extending between and connecting the source and the drain; and a gate structure in contact with the body, the gate structure including a gate electrode and a gate dielectric, wherein the gate dielectric is between the body and the gate electrode.
The integrated circuit of claim 1, wherein the Group I II -V semiconductor material comprises indium and phosphorous.
The integrated circuit of claim 1, wherein the Group I II -V semiconductor material comprises indium, gallium, and arsenic.
The integrated circuit of claim 1, wherein the body has fewer than 1E₆ defects per cm 2.
The integrated circuit of claim 1, wherein the one or more layers of buffer material include a layer with a graded ratio of indium to gallium from the first value to the second value.
The integrated circuit of claim 1, wherein the first value is 0.25 or less.
The integrated circuit of claim 1, wherein the buffer layer comprises a first layer with a mismatch no greater than 2.5% with respect to the substrate, a second layer with a lattice mismatch no greater than 2.5% with respect to the first layer, and a third layer with a lattice mismatch no greater than 2.5% with respect to the second layer.
The integrated circuit of claim 1, wherein the body is a nanowire, nanoribbon, or nanosheet and the gate structure wraps around the body.
A nanowire transistor structure comprising: a substrate comprising silicon; a buffer structure on the substrate, the buffer structure including n layers of buffer material and comprising indium, gallium, and phosphorous, wherein a ratio of indium to gallium in a first layer of the n layers is 0.35 or less and the ratio in an nth layer of the n layers is at least 2; a source and a drain on top of the buffer structure; at least one body extending between and connecting the source and the drain, the body comprising a Group I II -V semiconductor material; and a gate structure wrapped around each of the at least one body, the gate structure including a gate electrode and a gate dielectric, wherein the gate dielectric is between each of the at least one body and the gate electrode.
The nanowire transistor structure of claim 12, wherein the body comprises indium and phosphorous.
The nanowire transistor structure of claim 12, wherein the body comprises indium, gallium, and arsenic.
The nanowire transistor structure of claim 12, wherein the n layers of buffer material include a layer with a graded concentration of indium, wherein the ratio increases from a first value of 0.35 or less to a second value of at least 2.
The nanowire transistor structure of claim 12, wherein the n layers of buffer material include a first layer with the ratio of indium to gallium of 0, a second layer with the ratio of 1:3, a third layer with the ratio of 1:1, and a fourth layer with the ratio of 3:1.
The nanowire transistor structure of claim 12, wherein each of the at least one body is selected from a nanowire, a nanoribbon, and a nanosheet.
The nanowire transistor structure of claim 12, wherein the n layers of buffer material have a relaxed lattice constant.
The nanowire transistor structure of claim 12, wherein the nanowire transistor structure is an n-channel transistor.
The nanowire transistor structure of claim 12, wherein the nanowire transistor structure is a p-channel transistor.
Layer stacks claimed or described, ordered top of device to substrate.
integrated circuit transistor (FET)
Materials described outside the worked examples.
gallium phosphide
GaP
indium gallium phosphide
InGaP
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 1. In these example embodiments, the transistor structure 100 has a nanowire or nanoribbon configuration. The transistor structure 100 is formed on a …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
stacking fault/defect density in channel body (InP) | ≤ 1000000 cm⁻² | InP |
layer-to-layer lattice mismatch in buffer structure | ≤ 2.5 % |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,276,694Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 1. In these example embodiments, the transistor structure 100 has a nanowire or nanoribbon configuration. The transistor structure 100 is formed on a …
FIG. 2 shows a section taken through the gate structure 140 and perpendicular to the channel regions 130 of two devices. The gate structure 140 includes a gate …
FIG. 3, the buffer 112 includes a plurality of layers of buffer material. For example, the buffer 112 includes a first layer 11 4a of buffer material of GaP. This …
FIG. 4, a flowchart illustrates a process flow for a method 400 of forming an integrated circuit that includes one or more nanowire or nanoribbon transistor, in …
FIG. 5 after processing the superlattice into fins, in accordance with an embodiment of the present disclosure. [0009] FIGURE 7 illustrates a perspective view …
FIG. 6 after forming a dummy gate structure on the fins, in accordance with an embodiment of the present disclosure. [0010] FIGURE 8 illustrates a perspective …
FIG. 7 after recessing the fins adjacent the gate structure, in accordance with an embodiment of the present disclosure. [0011] FIGURE 9 illustrates a …
FIG. 8 after epitaxial growth of replacement source and drains from the exposed channel material, in accordance with an embodiment of the present disclosure. …
FIG. 9 after removing the dummy gate electrode and releasing nanowires in the channel region, in accordance with an embodiment of the present disclosure. …
FIG. 10 after replacement gate processing, in accordance with an embodiment of the present disclosure. [0014] FIGURE 12 illustrates a perspective view of a …
FIG. 11 after processing the source and drain contacts, in accordance with an embodiment of the present disclosure. [0015] FIGURE 13 illustrates an example …
FIG. 12 illustrates a perspective view of an example transistor structure 100 with S/D contacts 126 formed on the S/D 120, in accordance with some embodiments. …
FIG. 13 illustrates a computing system 1000 implemented with integrated circuit structures and/or transistor devices formed using the techniques disclosed …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit with at least one transistor, the integrated circuit comprising: a substrate comprising silicon; a buffer structure on the substrate, the buffer structure including one or more layers of buffer material comprising indium, gallium, and phosphorous, wherein a ratio of indium to gallium in the one or more layers of buffer material increases from a first value of 0.35 or less to a second value of at least 2; a source and a drain on top of the buffer structure; a body of Group I II -V semiconductor material extending between and connecting the source and the drain; and a gate structure in contact with the body, the gate structure including a gate electrode and a gate dielectric, wherein the gate dielectric is between the body and the gate electrode.
The integrated circuit of claim 1, wherein the Group I II -V semiconductor material comprises indium and phosphorous.
The integrated circuit of claim 1, wherein the Group I II -V semiconductor material comprises indium, gallium, and arsenic.
The integrated circuit of claim 1, wherein the body has fewer than 1E₆ defects per cm 2.
The integrated circuit of claim 1, wherein the one or more layers of buffer material include a layer with a graded ratio of indium to gallium from the first value to the second value.
The integrated circuit of claim 1, wherein the first value is 0.25 or less.
The integrated circuit of claim 1, wherein the buffer layer comprises a first layer with a mismatch no greater than 2.5% with respect to the substrate, a second layer with a lattice mismatch no greater than 2.5% with respect to the first layer, and a third layer with a lattice mismatch no greater than 2.5% with respect to the second layer.
The integrated circuit of claim 1, wherein the body is a nanowire, nanoribbon, or nanosheet and the gate structure wraps around the body.
A nanowire transistor structure comprising: a substrate comprising silicon; a buffer structure on the substrate, the buffer structure including n layers of buffer material and comprising indium, gallium, and phosphorous, wherein a ratio of indium to gallium in a first layer of the n layers is 0.35 or less and the ratio in an nth layer of the n layers is at least 2; a source and a drain on top of the buffer structure; at least one body extending between and connecting the source and the drain, the body comprising a Group I II -V semiconductor material; and a gate structure wrapped around each of the at least one body, the gate structure including a gate electrode and a gate dielectric, wherein the gate dielectric is between each of the at least one body and the gate electrode.
The nanowire transistor structure of claim 12, wherein the body comprises indium and phosphorous.
The nanowire transistor structure of claim 12, wherein the body comprises indium, gallium, and arsenic.
The nanowire transistor structure of claim 12, wherein the n layers of buffer material include a layer with a graded concentration of indium, wherein the ratio increases from a first value of 0.35 or less to a second value of at least 2.
The nanowire transistor structure of claim 12, wherein the n layers of buffer material include a first layer with the ratio of indium to gallium of 0, a second layer with the ratio of 1:3, a third layer with the ratio of 1:1, and a fourth layer with the ratio of 3:1.
The nanowire transistor structure of claim 12, wherein each of the at least one body is selected from a nanowire, a nanoribbon, and a nanosheet.
The nanowire transistor structure of claim 12, wherein the n layers of buffer material have a relaxed lattice constant.
The nanowire transistor structure of claim 12, wherein the nanowire transistor structure is an n-channel transistor.
The nanowire transistor structure of claim 12, wherein the nanowire transistor structure is a p-channel transistor.
Layer stacks claimed or described, ordered top of device to substrate.
integrated circuit transistor (FET)
Materials described outside the worked examples.
gallium phosphide
GaP
indium gallium phosphide
InGaP
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 1. In these example embodiments, the transistor structure 100 has a nanowire or nanoribbon configuration. The transistor structure 100 is formed on a …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
stacking fault/defect density in channel body (InP) | ≤ 1000000 cm⁻² | InP |
layer-to-layer lattice mismatch in buffer structure | ≤ 2.5 % |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,276,694Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 1. In these example embodiments, the transistor structure 100 has a nanowire or nanoribbon configuration. The transistor structure 100 is formed on a …
FIG. 2 shows a section taken through the gate structure 140 and perpendicular to the channel regions 130 of two devices. The gate structure 140 includes a gate …
FIG. 3, the buffer 112 includes a plurality of layers of buffer material. For example, the buffer 112 includes a first layer 11 4a of buffer material of GaP. This …
FIG. 4, a flowchart illustrates a process flow for a method 400 of forming an integrated circuit that includes one or more nanowire or nanoribbon transistor, in …
FIG. 5 after processing the superlattice into fins, in accordance with an embodiment of the present disclosure. [0009] FIGURE 7 illustrates a perspective view …
FIG. 6 after forming a dummy gate structure on the fins, in accordance with an embodiment of the present disclosure. [0010] FIGURE 8 illustrates a perspective …
FIG. 7 after recessing the fins adjacent the gate structure, in accordance with an embodiment of the present disclosure. [0011] FIGURE 9 illustrates a …
FIG. 8 after epitaxial growth of replacement source and drains from the exposed channel material, in accordance with an embodiment of the present disclosure. …
FIG. 9 after removing the dummy gate electrode and releasing nanowires in the channel region, in accordance with an embodiment of the present disclosure. …
FIG. 10 after replacement gate processing, in accordance with an embodiment of the present disclosure. [0014] FIGURE 12 illustrates a perspective view of a …
FIG. 11 after processing the source and drain contacts, in accordance with an embodiment of the present disclosure. [0015] FIGURE 13 illustrates an example …
FIG. 12 illustrates a perspective view of an example transistor structure 100 with S/D contacts 126 formed on the S/D 120, in accordance with some embodiments. …
FIG. 13 illustrates a computing system 1000 implemented with integrated circuit structures and/or transistor devices formed using the techniques disclosed …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit with at least one transistor, the integrated circuit comprising: a substrate comprising silicon; a buffer structure on the substrate, the buffer structure including one or more layers of buffer material comprising indium, gallium, and phosphorous, wherein a ratio of indium to gallium in the one or more layers of buffer material increases from a first value of 0.35 or less to a second value of at least 2; a source and a drain on top of the buffer structure; a body of Group I II -V semiconductor material extending between and connecting the source and the drain; and a gate structure in contact with the body, the gate structure including a gate electrode and a gate dielectric, wherein the gate dielectric is between the body and the gate electrode.
The integrated circuit of claim 1, wherein the Group I II -V semiconductor material comprises indium and phosphorous.
The integrated circuit of claim 1, wherein the Group I II -V semiconductor material comprises indium, gallium, and arsenic.
The integrated circuit of claim 1, wherein the body has fewer than 1E₆ defects per cm 2.
The integrated circuit of claim 1, wherein the one or more layers of buffer material include a layer with a graded ratio of indium to gallium from the first value to the second value.
The integrated circuit of claim 1, wherein the first value is 0.25 or less.
The integrated circuit of claim 1, wherein the buffer layer comprises a first layer with a mismatch no greater than 2.5% with respect to the substrate, a second layer with a lattice mismatch no greater than 2.5% with respect to the first layer, and a third layer with a lattice mismatch no greater than 2.5% with respect to the second layer.
The integrated circuit of claim 1, wherein the body is a nanowire, nanoribbon, or nanosheet and the gate structure wraps around the body.
A nanowire transistor structure comprising: a substrate comprising silicon; a buffer structure on the substrate, the buffer structure including n layers of buffer material and comprising indium, gallium, and phosphorous, wherein a ratio of indium to gallium in a first layer of the n layers is 0.35 or less and the ratio in an nth layer of the n layers is at least 2; a source and a drain on top of the buffer structure; at least one body extending between and connecting the source and the drain, the body comprising a Group I II -V semiconductor material; and a gate structure wrapped around each of the at least one body, the gate structure including a gate electrode and a gate dielectric, wherein the gate dielectric is between each of the at least one body and the gate electrode.
The nanowire transistor structure of claim 12, wherein the body comprises indium and phosphorous.
The nanowire transistor structure of claim 12, wherein the body comprises indium, gallium, and arsenic.
The nanowire transistor structure of claim 12, wherein the n layers of buffer material include a layer with a graded concentration of indium, wherein the ratio increases from a first value of 0.35 or less to a second value of at least 2.
The nanowire transistor structure of claim 12, wherein the n layers of buffer material include a first layer with the ratio of indium to gallium of 0, a second layer with the ratio of 1:3, a third layer with the ratio of 1:1, and a fourth layer with the ratio of 3:1.
The nanowire transistor structure of claim 12, wherein each of the at least one body is selected from a nanowire, a nanoribbon, and a nanosheet.
The nanowire transistor structure of claim 12, wherein the n layers of buffer material have a relaxed lattice constant.
The nanowire transistor structure of claim 12, wherein the nanowire transistor structure is an n-channel transistor.
The nanowire transistor structure of claim 12, wherein the nanowire transistor structure is a p-channel transistor.
Layer stacks claimed or described, ordered top of device to substrate.
integrated circuit transistor (FET)
Materials described outside the worked examples.
gallium phosphide
GaP
indium gallium phosphide
InGaP
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 1. In these example embodiments, the transistor structure 100 has a nanowire or nanoribbon configuration. The transistor structure 100 is formed on a …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
stacking fault/defect density in channel body (InP) | ≤ 1000000 cm⁻² | InP |
layer-to-layer lattice mismatch in buffer structure | ≤ 2.5 % |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,276,694Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 1. In these example embodiments, the transistor structure 100 has a nanowire or nanoribbon configuration. The transistor structure 100 is formed on a …
FIG. 2 shows a section taken through the gate structure 140 and perpendicular to the channel regions 130 of two devices. The gate structure 140 includes a gate …
FIG. 3, the buffer 112 includes a plurality of layers of buffer material. For example, the buffer 112 includes a first layer 11 4a of buffer material of GaP. This …
FIG. 4, a flowchart illustrates a process flow for a method 400 of forming an integrated circuit that includes one or more nanowire or nanoribbon transistor, in …
FIG. 5 after processing the superlattice into fins, in accordance with an embodiment of the present disclosure. [0009] FIGURE 7 illustrates a perspective view …
FIG. 6 after forming a dummy gate structure on the fins, in accordance with an embodiment of the present disclosure. [0010] FIGURE 8 illustrates a perspective …
FIG. 7 after recessing the fins adjacent the gate structure, in accordance with an embodiment of the present disclosure. [0011] FIGURE 9 illustrates a …
FIG. 8 after epitaxial growth of replacement source and drains from the exposed channel material, in accordance with an embodiment of the present disclosure. …
FIG. 9 after removing the dummy gate electrode and releasing nanowires in the channel region, in accordance with an embodiment of the present disclosure. …
FIG. 10 after replacement gate processing, in accordance with an embodiment of the present disclosure. [0014] FIGURE 12 illustrates a perspective view of a …
FIG. 11 after processing the source and drain contacts, in accordance with an embodiment of the present disclosure. [0015] FIGURE 13 illustrates an example …
FIG. 12 illustrates a perspective view of an example transistor structure 100 with S/D contacts 126 formed on the S/D 120, in accordance with some embodiments. …
FIG. 13 illustrates a computing system 1000 implemented with integrated circuit structures and/or transistor devices formed using the techniques disclosed …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit with at least one transistor, the integrated circuit comprising: a substrate comprising silicon; a buffer structure on the substrate, the buffer structure including one or more layers of buffer material comprising indium, gallium, and phosphorous, wherein a ratio of indium to gallium in the one or more layers of buffer material increases from a first value of 0.35 or less to a second value of at least 2; a source and a drain on top of the buffer structure; a body of Group I II -V semiconductor material extending between and connecting the source and the drain; and a gate structure in contact with the body, the gate structure including a gate electrode and a gate dielectric, wherein the gate dielectric is between the body and the gate electrode.
The integrated circuit of claim 1, wherein the Group I II -V semiconductor material comprises indium and phosphorous.
The integrated circuit of claim 1, wherein the Group I II -V semiconductor material comprises indium, gallium, and arsenic.
The integrated circuit of claim 1, wherein the body has fewer than 1E₆ defects per cm 2.
The integrated circuit of claim 1, wherein the one or more layers of buffer material include a layer with a graded ratio of indium to gallium from the first value to the second value.
The integrated circuit of claim 1, wherein the first value is 0.25 or less.
The integrated circuit of claim 1, wherein the buffer layer comprises a first layer with a mismatch no greater than 2.5% with respect to the substrate, a second layer with a lattice mismatch no greater than 2.5% with respect to the first layer, and a third layer with a lattice mismatch no greater than 2.5% with respect to the second layer.
The integrated circuit of claim 1, wherein the body is a nanowire, nanoribbon, or nanosheet and the gate structure wraps around the body.
A nanowire transistor structure comprising: a substrate comprising silicon; a buffer structure on the substrate, the buffer structure including n layers of buffer material and comprising indium, gallium, and phosphorous, wherein a ratio of indium to gallium in a first layer of the n layers is 0.35 or less and the ratio in an nth layer of the n layers is at least 2; a source and a drain on top of the buffer structure; at least one body extending between and connecting the source and the drain, the body comprising a Group I II -V semiconductor material; and a gate structure wrapped around each of the at least one body, the gate structure including a gate electrode and a gate dielectric, wherein the gate dielectric is between each of the at least one body and the gate electrode.
The nanowire transistor structure of claim 12, wherein the body comprises indium and phosphorous.
The nanowire transistor structure of claim 12, wherein the body comprises indium, gallium, and arsenic.
The nanowire transistor structure of claim 12, wherein the n layers of buffer material include a layer with a graded concentration of indium, wherein the ratio increases from a first value of 0.35 or less to a second value of at least 2.
The nanowire transistor structure of claim 12, wherein the n layers of buffer material include a first layer with the ratio of indium to gallium of 0, a second layer with the ratio of 1:3, a third layer with the ratio of 1:1, and a fourth layer with the ratio of 3:1.
The nanowire transistor structure of claim 12, wherein each of the at least one body is selected from a nanowire, a nanoribbon, and a nanosheet.
The nanowire transistor structure of claim 12, wherein the n layers of buffer material have a relaxed lattice constant.
The nanowire transistor structure of claim 12, wherein the nanowire transistor structure is an n-channel transistor.
The nanowire transistor structure of claim 12, wherein the nanowire transistor structure is a p-channel transistor.
Layer stacks claimed or described, ordered top of device to substrate.
integrated circuit transistor (FET)
Materials described outside the worked examples.
gallium phosphide
GaP
indium gallium phosphide
InGaP
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 1. In these example embodiments, the transistor structure 100 has a nanowire or nanoribbon configuration. The transistor structure 100 is formed on a …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
stacking fault/defect density in channel body (InP) | ≤ 1000000 cm⁻² | InP |
layer-to-layer lattice mismatch in buffer structure | ≤ 2.5 % |
Related documents with shared materials, methods, properties, or citations.
nanowire/nanoribbon/nanosheet gate-all-around transistor
Group III-V semiconductor
silicon
Si
indium phosphide
InP
indium gallium arsenide
InGaAs
FIG. 4, a flowchart illustrates a process flow for a method 400 of forming an integrated circuit that includes one or more nanowire or nanoribbon transistor, in …
FIG. 11 after processing the source and drain contacts, in accordance with an embodiment of the present disclosure. [0015] FIGURE 13 illustrates an example …
FIG. 12 illustrates a perspective view of an example transistor structure 100 with S/D contacts 126 formed on the S/D 120, in accordance with some embodiments. …
FIG. 13 illustrates a computing system 1000 implemented with integrated circuit structures and/or transistor devices formed using the techniques disclosed …
Thickness | 5–50 nm | — |
Thickness | 1–950 µm | — |
Thickness | 20–800 µm | — |
Thickness | 30–40 nm | — |
Thickness | 20–500 nm | — |
Thickness | 200–500 nm | — |
Thickness | 2–50 nm | — |
Thickness | 30–50 nm | — |
Thickness | ≥ 0.2 nm | — |
Thickness | ≥ 500 nm | — |
nanowire/nanoribbon/nanosheet gate-all-around transistor
Group III-V semiconductor
silicon
Si
indium phosphide
InP
indium gallium arsenide
InGaAs
FIG. 4, a flowchart illustrates a process flow for a method 400 of forming an integrated circuit that includes one or more nanowire or nanoribbon transistor, in …
FIG. 11 after processing the source and drain contacts, in accordance with an embodiment of the present disclosure. [0015] FIGURE 13 illustrates an example …
FIG. 12 illustrates a perspective view of an example transistor structure 100 with S/D contacts 126 formed on the S/D 120, in accordance with some embodiments. …
FIG. 13 illustrates a computing system 1000 implemented with integrated circuit structures and/or transistor devices formed using the techniques disclosed …
Thickness | 5–50 nm | — |
Thickness | 1–950 µm | — |
Thickness | 20–800 µm | — |
Thickness | 30–40 nm | — |
Thickness | 20–500 nm | — |
Thickness | 200–500 nm | — |
Thickness | 2–50 nm | — |
Thickness | 30–50 nm | — |
Thickness | ≥ 0.2 nm | — |
Thickness | ≥ 500 nm | — |
nanowire/nanoribbon/nanosheet gate-all-around transistor
Group III-V semiconductor
silicon
Si
indium phosphide
InP
indium gallium arsenide
InGaAs
FIG. 4, a flowchart illustrates a process flow for a method 400 of forming an integrated circuit that includes one or more nanowire or nanoribbon transistor, in …
FIG. 11 after processing the source and drain contacts, in accordance with an embodiment of the present disclosure. [0015] FIGURE 13 illustrates an example …
FIG. 12 illustrates a perspective view of an example transistor structure 100 with S/D contacts 126 formed on the S/D 120, in accordance with some embodiments. …
FIG. 13 illustrates a computing system 1000 implemented with integrated circuit structures and/or transistor devices formed using the techniques disclosed …
Thickness | 5–50 nm | — |
Thickness | 1–950 µm | — |
Thickness | 20–800 µm | — |
Thickness | 30–40 nm | — |
Thickness | 20–500 nm | — |
Thickness | 200–500 nm | — |
Thickness | 2–50 nm | — |
Thickness | 30–50 nm | — |
Thickness | ≥ 0.2 nm | — |
Thickness | ≥ 500 nm | — |
nanowire/nanoribbon/nanosheet gate-all-around transistor
Group III-V semiconductor
silicon
Si
indium phosphide
InP
indium gallium arsenide
InGaAs
FIG. 4, a flowchart illustrates a process flow for a method 400 of forming an integrated circuit that includes one or more nanowire or nanoribbon transistor, in …
FIG. 11 after processing the source and drain contacts, in accordance with an embodiment of the present disclosure. [0015] FIGURE 13 illustrates an example …
FIG. 12 illustrates a perspective view of an example transistor structure 100 with S/D contacts 126 formed on the S/D 120, in accordance with some embodiments. …
FIG. 13 illustrates a computing system 1000 implemented with integrated circuit structures and/or transistor devices formed using the techniques disclosed …
Thickness | 5–50 nm | — |
Thickness | 1–950 µm | — |
Thickness | 20–800 µm | — |
Thickness | 30–40 nm | — |
Thickness | 20–500 nm | — |
Thickness | 200–500 nm | — |
Thickness | 2–50 nm | — |
Thickness | 30–50 nm | — |
Thickness | ≥ 0.2 nm | — |
Thickness | ≥ 500 nm | — |