Patent
US 8,823,140GAN VERTICAL BIPOLAR TRANSISTOR
Hui Nie, Andrew Edwards, Isik Kizilyalli, Dave Bour
AVOGY, INC.·US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 8,823,140Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1-12 are provided as an example only, and are not limiting. Furthermore, the figures are not drawn to scale, and the manufacture of the vertical bipolar …
FIG. 2, one or more portions of the first dielectric layer 160 and the two emitter layers 140 and 150 can be removed to expose at least a portion of a surface …
FIG. 3, the second dielectric layer 310 can be a conformal layer. The thickness 315 of the second dielectric layer 310 can be chosen based on desired spacer …
FIG. 4 can be formed by removing at least a portion of the second dielectric layer 310. This removal process, in some embodiments, can include a dry etch, such …
FIG. 5 is a simplified cross-sectional diagram illustrating the formation of a first base contact layer 510 coupled to the base layer 130, spacers 410, and first …
FIG. 6 illustrates the formation of a second base contact layer 610 coupled with the first 10 base contact layer 510. The second base contact layer 610 can …
FIG. 7 shows how at least a portion 710 of the first and second base contact layers 510 and 610 can be removed to form the base contacts from remaining portions …
FIG. 8 illustrates an optional formation of one or more junction termination elements 5 810, or edge termination structures. Some or all of the junction …
FIGS. 9-11 illustrate the formation of a third dielectric layer 910 and the formation of 20 openings 1010 and 1110 to the emitter structure 230. Similar to …
FIG. 12 illustrates the formation of an emitter contact by forming a metal structure 1210 coupled to the emitter structure 230 via the openings 1010 and 1110. …
FIG. 13 is simplified flowchart illustrating a method of fabricating a vertical bipolar 25 transistor, according to an embodiment of the present invention. The …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for fabricating a vertical bipolar transistor, the method comprising: providing a I ll-nitride base structure of a first conductivity type; forming a I ll -nitride emitter structure of a second conductivity type having a first surface and a second surface, the second surface being substantially opposite the first surface, wherein: the first surface of the I ll -nitride emitter structure is coupled to a surface of the I ll -nitride base structure; a first dielectric layer is coupled to the second surface of the I ll -nitride emitter structure; and the I ll -nitride emitter structure has a sidewall adjacent to an exposed portion of the surface of the I ll -nitride base structure; forming a spacer coupled to the sidewall of the I ll -nitride emitter structure and the exposed portion of the surface of the I ll -nitride base structure; and forming a base contact structure comprising a I ll-nitride material coupled to the spacer, the exposed portion of the surface of the I ll -nitride base structure, and the first dielectric layer, such that the first dielectric layer and the spacer are disposed between the base contact structure and the I ll -nitride emitter structure. withdrawn
The method of claim 1 further comprising: forming a second dielectric layer coupled to the base contact structure and the first dielectric layer; removing at least a portion of the second dielectric layer and the first dielectric layer to expose a portion of the second surface of the I ll -nitride emitter structure; and forming a metal structure coupled to the exposed portion of the second surface of the I ll -nitride emitter structure. withdrawn
The method of claim 1 further comprising forming the III- nitride material of the base contact structure using epitaxial regrowth. withdrawn
The method of claim 1 further comprising forming one or more edge termination structures. withdrawn
The method of claim 1 wherein the I ll -nitride base structure comprises indium gallium nitride (InGaN). withdrawn
The method of claim 1 wherein the I ll -nitride emitter structure comprises at least two I ll-nitride epitaxial layers, and forming the I ll -nitride emitter structure comprises: forming a first I ll -nitride epitaxial layer coupled to the surface of the I ll -nitride base structure, the first I ll -nitride epitaxial layer having a first dopant concentration; and forming a second I ll -nitride epitaxial layer coupled to the first I ll -nitride epitaxial layer, the second I ll -nitride epitaxial layer having a second dopant concentration; wherein the first dopant concentration is less than the second dopant concentration. withdrawn
The method of claim 1 wherein forming the base contact structure comprises forming a metal layer coupled to the I ll -nitride material of the base contact structure. withdrawn
A semiconductor device comprising: a I II -nitride base structure of a first conductivity type; a I II -nitride emitter structure of a second conductivity type having a first surface and a second surface, the second surface being substantially opposite the first surface, wherein the first surface of the I II -nitride emitter structure is coupled to a surface of the I ll -nitride base structure; a first dielectric layer coupled to the second surface of the I II -nitride emitter structure; a spacer coupled to a sidewall of the I ll -nitride emitter structure and the surface of the I ll -nitride base structure; and a base contact structure comprising a I ll -nitride material coupled to the spacer, the surface of the I ll -nitride base structure, and the first dielectric layer, such that the first dielectric layer and the spacer are disposed between the base contact structure and the I II -nitride emitter structure.
The semiconductor device of claim 10 further comprising: a second dielectric layer coupled to the base contact structure and the first dielectric layer; and a metal structure coupled to of the second surface of the I ll -nitride emitter structure.
The semiconductor device of claim 10 further comprising one or more edge termination structures.
The semiconductor device of claim 10 wherein the I ll -nitride emitter structure comprises: Page 4 of 7 App l. No. 13/675,9 16 PATENT Arm dt. dated Response to Office Action of a first I II -nitride epitaxial layer coupled to the surface of the I II-nitride base structure, the first I ll -nitride epitaxial layer having a first dopant concentration; and a second I II -nitride epitaxial layer coupled to the first I ll -nitride epitaxial layer, the second I II-nitride epitaxial layer having a second dopant concentration; wherein the first dopant concentration is less than the second dopant concentration.
The semiconductor device of claim 10 wherein the base contact structure comprises a metal layer coupled to the I ll -nitride material of the base contact structure.
A method for fabricating a vertical bipolar transistor, the method comprising: providing a first I₁ -nitride layer of a first conductivity type; forming at least one I₁ -nitride layer of a second conductivity type coupled to the first I II -nitride layer; forming a first dielectric layer coupled to the at least one I ll -nitride layer; removing at least a portion of the first dielectric layer and the at least one III- nitride layer to: expose a surface of the first I ll -nitride layer, and form a layered structure comprising at least a portion of the at least one Ill -nitride layer and the first dielectric layer; forming a spacer coupled to a sidewall of the layered structure; and forming a second I ll-nitride layer of the first conductivity type coupled to the spacer, the exposed surface of the first I ll -nitride layer, and the first dielectric layer, such that the first dielectric layer and the spacer are disposed between the second I ll -nitride layer and the at least one I ll -nitride layer. withdrawn
The method of claim 16 wherein further comprising: removing at least a portion of the second I ll -nitride layer to expose a surface of the first dielectric layer; forming a second dielectric layer coupled to the second I ll -nitride layer and the first dielectric layer; Page 5 of 7 App l. No. 13/675,9 16 PATENT Arm dt. dated Response to Office Action of removing at least a portion of the second dielectric layer and the first dielectric layer to expose a surface of the at least one I II -nitride layer; and forming a metal structure coupled to the exposed surface of the at least one III- nitride layer. withdrawn
The method of claim 16 further comprising forming second III -nitride layer using epitaxial regrowth. withdrawn
The method of claim 16 further comprising forming one or more edge termination structures. withdrawn
The method of claim 16 wherein forming the at least one III- nitride layer comprises: forming a third I ll -nitride epitaxial layer coupled to the first I ll -nitride layer, the third I ll -nitride epitaxial layer having a first dopant concentration; and forming a fourth I ll -nitride epitaxial layer coupled to the third I ll -nitride epitaxial layer, the fourth I ll -nitride epitaxial layer having a second dopant concentration; wherein the first dopant concentration is less than the second dopant concentration. withdrawn
The method of claim 16 further comprising forming a metal layer coupled to the second I ll-nitride layer. Page 6 of 7 withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
vertical bipolar transistor
Materials described outside the worked examples.
III-nitride
III-nitride base contact material
dielectric
Measurements and analyses referenced in the patent, with their drawing references.
FIGS. 1-12 are provided as an example only, and are not limiting. Furthermore, the figures are not drawn to scale, and the manufacture of the vertical bipolar …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 100–300 nm | — |
Temperature | 600–800 °C |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,823,140Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1-12 are provided as an example only, and are not limiting. Furthermore, the figures are not drawn to scale, and the manufacture of the vertical bipolar …
FIG. 2, one or more portions of the first dielectric layer 160 and the two emitter layers 140 and 150 can be removed to expose at least a portion of a surface …
FIG. 3, the second dielectric layer 310 can be a conformal layer. The thickness 315 of the second dielectric layer 310 can be chosen based on desired spacer …
FIG. 4 can be formed by removing at least a portion of the second dielectric layer 310. This removal process, in some embodiments, can include a dry etch, such …
FIG. 5 is a simplified cross-sectional diagram illustrating the formation of a first base contact layer 510 coupled to the base layer 130, spacers 410, and first …
FIG. 6 illustrates the formation of a second base contact layer 610 coupled with the first 10 base contact layer 510. The second base contact layer 610 can …
FIG. 7 shows how at least a portion 710 of the first and second base contact layers 510 and 610 can be removed to form the base contacts from remaining portions …
FIG. 8 illustrates an optional formation of one or more junction termination elements 5 810, or edge termination structures. Some or all of the junction …
FIGS. 9-11 illustrate the formation of a third dielectric layer 910 and the formation of 20 openings 1010 and 1110 to the emitter structure 230. Similar to …
FIG. 12 illustrates the formation of an emitter contact by forming a metal structure 1210 coupled to the emitter structure 230 via the openings 1010 and 1110. …
FIG. 13 is simplified flowchart illustrating a method of fabricating a vertical bipolar 25 transistor, according to an embodiment of the present invention. The …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for fabricating a vertical bipolar transistor, the method comprising: providing a I ll-nitride base structure of a first conductivity type; forming a I ll -nitride emitter structure of a second conductivity type having a first surface and a second surface, the second surface being substantially opposite the first surface, wherein: the first surface of the I ll -nitride emitter structure is coupled to a surface of the I ll -nitride base structure; a first dielectric layer is coupled to the second surface of the I ll -nitride emitter structure; and the I ll -nitride emitter structure has a sidewall adjacent to an exposed portion of the surface of the I ll -nitride base structure; forming a spacer coupled to the sidewall of the I ll -nitride emitter structure and the exposed portion of the surface of the I ll -nitride base structure; and forming a base contact structure comprising a I ll-nitride material coupled to the spacer, the exposed portion of the surface of the I ll -nitride base structure, and the first dielectric layer, such that the first dielectric layer and the spacer are disposed between the base contact structure and the I ll -nitride emitter structure. withdrawn
The method of claim 1 further comprising: forming a second dielectric layer coupled to the base contact structure and the first dielectric layer; removing at least a portion of the second dielectric layer and the first dielectric layer to expose a portion of the second surface of the I ll -nitride emitter structure; and forming a metal structure coupled to the exposed portion of the second surface of the I ll -nitride emitter structure. withdrawn
The method of claim 1 further comprising forming the III- nitride material of the base contact structure using epitaxial regrowth. withdrawn
The method of claim 1 further comprising forming one or more edge termination structures. withdrawn
The method of claim 1 wherein the I ll -nitride base structure comprises indium gallium nitride (InGaN). withdrawn
The method of claim 1 wherein the I ll -nitride emitter structure comprises at least two I ll-nitride epitaxial layers, and forming the I ll -nitride emitter structure comprises: forming a first I ll -nitride epitaxial layer coupled to the surface of the I ll -nitride base structure, the first I ll -nitride epitaxial layer having a first dopant concentration; and forming a second I ll -nitride epitaxial layer coupled to the first I ll -nitride epitaxial layer, the second I ll -nitride epitaxial layer having a second dopant concentration; wherein the first dopant concentration is less than the second dopant concentration. withdrawn
The method of claim 1 wherein forming the base contact structure comprises forming a metal layer coupled to the I ll -nitride material of the base contact structure. withdrawn
A semiconductor device comprising: a I II -nitride base structure of a first conductivity type; a I II -nitride emitter structure of a second conductivity type having a first surface and a second surface, the second surface being substantially opposite the first surface, wherein the first surface of the I II -nitride emitter structure is coupled to a surface of the I ll -nitride base structure; a first dielectric layer coupled to the second surface of the I II -nitride emitter structure; a spacer coupled to a sidewall of the I ll -nitride emitter structure and the surface of the I ll -nitride base structure; and a base contact structure comprising a I ll -nitride material coupled to the spacer, the surface of the I ll -nitride base structure, and the first dielectric layer, such that the first dielectric layer and the spacer are disposed between the base contact structure and the I II -nitride emitter structure.
The semiconductor device of claim 10 further comprising: a second dielectric layer coupled to the base contact structure and the first dielectric layer; and a metal structure coupled to of the second surface of the I ll -nitride emitter structure.
The semiconductor device of claim 10 further comprising one or more edge termination structures.
The semiconductor device of claim 10 wherein the I ll -nitride emitter structure comprises: Page 4 of 7 App l. No. 13/675,9 16 PATENT Arm dt. dated Response to Office Action of a first I II -nitride epitaxial layer coupled to the surface of the I II-nitride base structure, the first I ll -nitride epitaxial layer having a first dopant concentration; and a second I II -nitride epitaxial layer coupled to the first I ll -nitride epitaxial layer, the second I II-nitride epitaxial layer having a second dopant concentration; wherein the first dopant concentration is less than the second dopant concentration.
The semiconductor device of claim 10 wherein the base contact structure comprises a metal layer coupled to the I ll -nitride material of the base contact structure.
A method for fabricating a vertical bipolar transistor, the method comprising: providing a first I₁ -nitride layer of a first conductivity type; forming at least one I₁ -nitride layer of a second conductivity type coupled to the first I II -nitride layer; forming a first dielectric layer coupled to the at least one I ll -nitride layer; removing at least a portion of the first dielectric layer and the at least one III- nitride layer to: expose a surface of the first I ll -nitride layer, and form a layered structure comprising at least a portion of the at least one Ill -nitride layer and the first dielectric layer; forming a spacer coupled to a sidewall of the layered structure; and forming a second I ll-nitride layer of the first conductivity type coupled to the spacer, the exposed surface of the first I ll -nitride layer, and the first dielectric layer, such that the first dielectric layer and the spacer are disposed between the second I ll -nitride layer and the at least one I ll -nitride layer. withdrawn
The method of claim 16 wherein further comprising: removing at least a portion of the second I ll -nitride layer to expose a surface of the first dielectric layer; forming a second dielectric layer coupled to the second I ll -nitride layer and the first dielectric layer; Page 5 of 7 App l. No. 13/675,9 16 PATENT Arm dt. dated Response to Office Action of removing at least a portion of the second dielectric layer and the first dielectric layer to expose a surface of the at least one I II -nitride layer; and forming a metal structure coupled to the exposed surface of the at least one III- nitride layer. withdrawn
The method of claim 16 further comprising forming second III -nitride layer using epitaxial regrowth. withdrawn
The method of claim 16 further comprising forming one or more edge termination structures. withdrawn
The method of claim 16 wherein forming the at least one III- nitride layer comprises: forming a third I ll -nitride epitaxial layer coupled to the first I ll -nitride layer, the third I ll -nitride epitaxial layer having a first dopant concentration; and forming a fourth I ll -nitride epitaxial layer coupled to the third I ll -nitride epitaxial layer, the fourth I ll -nitride epitaxial layer having a second dopant concentration; wherein the first dopant concentration is less than the second dopant concentration. withdrawn
The method of claim 16 further comprising forming a metal layer coupled to the second I ll-nitride layer. Page 6 of 7 withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
vertical bipolar transistor
Materials described outside the worked examples.
III-nitride
III-nitride base contact material
dielectric
Measurements and analyses referenced in the patent, with their drawing references.
FIGS. 1-12 are provided as an example only, and are not limiting. Furthermore, the figures are not drawn to scale, and the manufacture of the vertical bipolar …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 100–300 nm | — |
Temperature | 600–800 °C |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,823,140Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1-12 are provided as an example only, and are not limiting. Furthermore, the figures are not drawn to scale, and the manufacture of the vertical bipolar …
FIG. 2, one or more portions of the first dielectric layer 160 and the two emitter layers 140 and 150 can be removed to expose at least a portion of a surface …
FIG. 3, the second dielectric layer 310 can be a conformal layer. The thickness 315 of the second dielectric layer 310 can be chosen based on desired spacer …
FIG. 4 can be formed by removing at least a portion of the second dielectric layer 310. This removal process, in some embodiments, can include a dry etch, such …
FIG. 5 is a simplified cross-sectional diagram illustrating the formation of a first base contact layer 510 coupled to the base layer 130, spacers 410, and first …
FIG. 6 illustrates the formation of a second base contact layer 610 coupled with the first 10 base contact layer 510. The second base contact layer 610 can …
FIG. 7 shows how at least a portion 710 of the first and second base contact layers 510 and 610 can be removed to form the base contacts from remaining portions …
FIG. 8 illustrates an optional formation of one or more junction termination elements 5 810, or edge termination structures. Some or all of the junction …
FIGS. 9-11 illustrate the formation of a third dielectric layer 910 and the formation of 20 openings 1010 and 1110 to the emitter structure 230. Similar to …
FIG. 12 illustrates the formation of an emitter contact by forming a metal structure 1210 coupled to the emitter structure 230 via the openings 1010 and 1110. …
FIG. 13 is simplified flowchart illustrating a method of fabricating a vertical bipolar 25 transistor, according to an embodiment of the present invention. The …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for fabricating a vertical bipolar transistor, the method comprising: providing a I ll-nitride base structure of a first conductivity type; forming a I ll -nitride emitter structure of a second conductivity type having a first surface and a second surface, the second surface being substantially opposite the first surface, wherein: the first surface of the I ll -nitride emitter structure is coupled to a surface of the I ll -nitride base structure; a first dielectric layer is coupled to the second surface of the I ll -nitride emitter structure; and the I ll -nitride emitter structure has a sidewall adjacent to an exposed portion of the surface of the I ll -nitride base structure; forming a spacer coupled to the sidewall of the I ll -nitride emitter structure and the exposed portion of the surface of the I ll -nitride base structure; and forming a base contact structure comprising a I ll-nitride material coupled to the spacer, the exposed portion of the surface of the I ll -nitride base structure, and the first dielectric layer, such that the first dielectric layer and the spacer are disposed between the base contact structure and the I ll -nitride emitter structure. withdrawn
The method of claim 1 further comprising: forming a second dielectric layer coupled to the base contact structure and the first dielectric layer; removing at least a portion of the second dielectric layer and the first dielectric layer to expose a portion of the second surface of the I ll -nitride emitter structure; and forming a metal structure coupled to the exposed portion of the second surface of the I ll -nitride emitter structure. withdrawn
The method of claim 1 further comprising forming the III- nitride material of the base contact structure using epitaxial regrowth. withdrawn
The method of claim 1 further comprising forming one or more edge termination structures. withdrawn
The method of claim 1 wherein the I ll -nitride base structure comprises indium gallium nitride (InGaN). withdrawn
The method of claim 1 wherein the I ll -nitride emitter structure comprises at least two I ll-nitride epitaxial layers, and forming the I ll -nitride emitter structure comprises: forming a first I ll -nitride epitaxial layer coupled to the surface of the I ll -nitride base structure, the first I ll -nitride epitaxial layer having a first dopant concentration; and forming a second I ll -nitride epitaxial layer coupled to the first I ll -nitride epitaxial layer, the second I ll -nitride epitaxial layer having a second dopant concentration; wherein the first dopant concentration is less than the second dopant concentration. withdrawn
The method of claim 1 wherein forming the base contact structure comprises forming a metal layer coupled to the I ll -nitride material of the base contact structure. withdrawn
A semiconductor device comprising: a I II -nitride base structure of a first conductivity type; a I II -nitride emitter structure of a second conductivity type having a first surface and a second surface, the second surface being substantially opposite the first surface, wherein the first surface of the I II -nitride emitter structure is coupled to a surface of the I ll -nitride base structure; a first dielectric layer coupled to the second surface of the I II -nitride emitter structure; a spacer coupled to a sidewall of the I ll -nitride emitter structure and the surface of the I ll -nitride base structure; and a base contact structure comprising a I ll -nitride material coupled to the spacer, the surface of the I ll -nitride base structure, and the first dielectric layer, such that the first dielectric layer and the spacer are disposed between the base contact structure and the I II -nitride emitter structure.
The semiconductor device of claim 10 further comprising: a second dielectric layer coupled to the base contact structure and the first dielectric layer; and a metal structure coupled to of the second surface of the I ll -nitride emitter structure.
The semiconductor device of claim 10 further comprising one or more edge termination structures.
The semiconductor device of claim 10 wherein the I ll -nitride emitter structure comprises: Page 4 of 7 App l. No. 13/675,9 16 PATENT Arm dt. dated Response to Office Action of a first I II -nitride epitaxial layer coupled to the surface of the I II-nitride base structure, the first I ll -nitride epitaxial layer having a first dopant concentration; and a second I II -nitride epitaxial layer coupled to the first I ll -nitride epitaxial layer, the second I II-nitride epitaxial layer having a second dopant concentration; wherein the first dopant concentration is less than the second dopant concentration.
The semiconductor device of claim 10 wherein the base contact structure comprises a metal layer coupled to the I ll -nitride material of the base contact structure.
A method for fabricating a vertical bipolar transistor, the method comprising: providing a first I₁ -nitride layer of a first conductivity type; forming at least one I₁ -nitride layer of a second conductivity type coupled to the first I II -nitride layer; forming a first dielectric layer coupled to the at least one I ll -nitride layer; removing at least a portion of the first dielectric layer and the at least one III- nitride layer to: expose a surface of the first I ll -nitride layer, and form a layered structure comprising at least a portion of the at least one Ill -nitride layer and the first dielectric layer; forming a spacer coupled to a sidewall of the layered structure; and forming a second I ll-nitride layer of the first conductivity type coupled to the spacer, the exposed surface of the first I ll -nitride layer, and the first dielectric layer, such that the first dielectric layer and the spacer are disposed between the second I ll -nitride layer and the at least one I ll -nitride layer. withdrawn
The method of claim 16 wherein further comprising: removing at least a portion of the second I ll -nitride layer to expose a surface of the first dielectric layer; forming a second dielectric layer coupled to the second I ll -nitride layer and the first dielectric layer; Page 5 of 7 App l. No. 13/675,9 16 PATENT Arm dt. dated Response to Office Action of removing at least a portion of the second dielectric layer and the first dielectric layer to expose a surface of the at least one I II -nitride layer; and forming a metal structure coupled to the exposed surface of the at least one III- nitride layer. withdrawn
The method of claim 16 further comprising forming second III -nitride layer using epitaxial regrowth. withdrawn
The method of claim 16 further comprising forming one or more edge termination structures. withdrawn
The method of claim 16 wherein forming the at least one III- nitride layer comprises: forming a third I ll -nitride epitaxial layer coupled to the first I ll -nitride layer, the third I ll -nitride epitaxial layer having a first dopant concentration; and forming a fourth I ll -nitride epitaxial layer coupled to the third I ll -nitride epitaxial layer, the fourth I ll -nitride epitaxial layer having a second dopant concentration; wherein the first dopant concentration is less than the second dopant concentration. withdrawn
The method of claim 16 further comprising forming a metal layer coupled to the second I ll-nitride layer. Page 6 of 7 withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
vertical bipolar transistor
Materials described outside the worked examples.
III-nitride
III-nitride base contact material
dielectric
Measurements and analyses referenced in the patent, with their drawing references.
FIGS. 1-12 are provided as an example only, and are not limiting. Furthermore, the figures are not drawn to scale, and the manufacture of the vertical bipolar …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 100–300 nm | — |
Temperature | 600–800 °C |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,823,140Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1-12 are provided as an example only, and are not limiting. Furthermore, the figures are not drawn to scale, and the manufacture of the vertical bipolar …
FIG. 2, one or more portions of the first dielectric layer 160 and the two emitter layers 140 and 150 can be removed to expose at least a portion of a surface …
FIG. 3, the second dielectric layer 310 can be a conformal layer. The thickness 315 of the second dielectric layer 310 can be chosen based on desired spacer …
FIG. 4 can be formed by removing at least a portion of the second dielectric layer 310. This removal process, in some embodiments, can include a dry etch, such …
FIG. 5 is a simplified cross-sectional diagram illustrating the formation of a first base contact layer 510 coupled to the base layer 130, spacers 410, and first …
FIG. 6 illustrates the formation of a second base contact layer 610 coupled with the first 10 base contact layer 510. The second base contact layer 610 can …
FIG. 7 shows how at least a portion 710 of the first and second base contact layers 510 and 610 can be removed to form the base contacts from remaining portions …
FIG. 8 illustrates an optional formation of one or more junction termination elements 5 810, or edge termination structures. Some or all of the junction …
FIGS. 9-11 illustrate the formation of a third dielectric layer 910 and the formation of 20 openings 1010 and 1110 to the emitter structure 230. Similar to …
FIG. 12 illustrates the formation of an emitter contact by forming a metal structure 1210 coupled to the emitter structure 230 via the openings 1010 and 1110. …
FIG. 13 is simplified flowchart illustrating a method of fabricating a vertical bipolar 25 transistor, according to an embodiment of the present invention. The …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for fabricating a vertical bipolar transistor, the method comprising: providing a I ll-nitride base structure of a first conductivity type; forming a I ll -nitride emitter structure of a second conductivity type having a first surface and a second surface, the second surface being substantially opposite the first surface, wherein: the first surface of the I ll -nitride emitter structure is coupled to a surface of the I ll -nitride base structure; a first dielectric layer is coupled to the second surface of the I ll -nitride emitter structure; and the I ll -nitride emitter structure has a sidewall adjacent to an exposed portion of the surface of the I ll -nitride base structure; forming a spacer coupled to the sidewall of the I ll -nitride emitter structure and the exposed portion of the surface of the I ll -nitride base structure; and forming a base contact structure comprising a I ll-nitride material coupled to the spacer, the exposed portion of the surface of the I ll -nitride base structure, and the first dielectric layer, such that the first dielectric layer and the spacer are disposed between the base contact structure and the I ll -nitride emitter structure. withdrawn
The method of claim 1 further comprising: forming a second dielectric layer coupled to the base contact structure and the first dielectric layer; removing at least a portion of the second dielectric layer and the first dielectric layer to expose a portion of the second surface of the I ll -nitride emitter structure; and forming a metal structure coupled to the exposed portion of the second surface of the I ll -nitride emitter structure. withdrawn
The method of claim 1 further comprising forming the III- nitride material of the base contact structure using epitaxial regrowth. withdrawn
The method of claim 1 further comprising forming one or more edge termination structures. withdrawn
The method of claim 1 wherein the I ll -nitride base structure comprises indium gallium nitride (InGaN). withdrawn
The method of claim 1 wherein the I ll -nitride emitter structure comprises at least two I ll-nitride epitaxial layers, and forming the I ll -nitride emitter structure comprises: forming a first I ll -nitride epitaxial layer coupled to the surface of the I ll -nitride base structure, the first I ll -nitride epitaxial layer having a first dopant concentration; and forming a second I ll -nitride epitaxial layer coupled to the first I ll -nitride epitaxial layer, the second I ll -nitride epitaxial layer having a second dopant concentration; wherein the first dopant concentration is less than the second dopant concentration. withdrawn
The method of claim 1 wherein forming the base contact structure comprises forming a metal layer coupled to the I ll -nitride material of the base contact structure. withdrawn
A semiconductor device comprising: a I II -nitride base structure of a first conductivity type; a I II -nitride emitter structure of a second conductivity type having a first surface and a second surface, the second surface being substantially opposite the first surface, wherein the first surface of the I II -nitride emitter structure is coupled to a surface of the I ll -nitride base structure; a first dielectric layer coupled to the second surface of the I II -nitride emitter structure; a spacer coupled to a sidewall of the I ll -nitride emitter structure and the surface of the I ll -nitride base structure; and a base contact structure comprising a I ll -nitride material coupled to the spacer, the surface of the I ll -nitride base structure, and the first dielectric layer, such that the first dielectric layer and the spacer are disposed between the base contact structure and the I II -nitride emitter structure.
The semiconductor device of claim 10 further comprising: a second dielectric layer coupled to the base contact structure and the first dielectric layer; and a metal structure coupled to of the second surface of the I ll -nitride emitter structure.
The semiconductor device of claim 10 further comprising one or more edge termination structures.
The semiconductor device of claim 10 wherein the I ll -nitride emitter structure comprises: Page 4 of 7 App l. No. 13/675,9 16 PATENT Arm dt. dated Response to Office Action of a first I II -nitride epitaxial layer coupled to the surface of the I II-nitride base structure, the first I ll -nitride epitaxial layer having a first dopant concentration; and a second I II -nitride epitaxial layer coupled to the first I ll -nitride epitaxial layer, the second I II-nitride epitaxial layer having a second dopant concentration; wherein the first dopant concentration is less than the second dopant concentration.
The semiconductor device of claim 10 wherein the base contact structure comprises a metal layer coupled to the I ll -nitride material of the base contact structure.
A method for fabricating a vertical bipolar transistor, the method comprising: providing a first I₁ -nitride layer of a first conductivity type; forming at least one I₁ -nitride layer of a second conductivity type coupled to the first I II -nitride layer; forming a first dielectric layer coupled to the at least one I ll -nitride layer; removing at least a portion of the first dielectric layer and the at least one III- nitride layer to: expose a surface of the first I ll -nitride layer, and form a layered structure comprising at least a portion of the at least one Ill -nitride layer and the first dielectric layer; forming a spacer coupled to a sidewall of the layered structure; and forming a second I ll-nitride layer of the first conductivity type coupled to the spacer, the exposed surface of the first I ll -nitride layer, and the first dielectric layer, such that the first dielectric layer and the spacer are disposed between the second I ll -nitride layer and the at least one I ll -nitride layer. withdrawn
The method of claim 16 wherein further comprising: removing at least a portion of the second I ll -nitride layer to expose a surface of the first dielectric layer; forming a second dielectric layer coupled to the second I ll -nitride layer and the first dielectric layer; Page 5 of 7 App l. No. 13/675,9 16 PATENT Arm dt. dated Response to Office Action of removing at least a portion of the second dielectric layer and the first dielectric layer to expose a surface of the at least one I II -nitride layer; and forming a metal structure coupled to the exposed surface of the at least one III- nitride layer. withdrawn
The method of claim 16 further comprising forming second III -nitride layer using epitaxial regrowth. withdrawn
The method of claim 16 further comprising forming one or more edge termination structures. withdrawn
The method of claim 16 wherein forming the at least one III- nitride layer comprises: forming a third I ll -nitride epitaxial layer coupled to the first I ll -nitride layer, the third I ll -nitride epitaxial layer having a first dopant concentration; and forming a fourth I ll -nitride epitaxial layer coupled to the third I ll -nitride epitaxial layer, the fourth I ll -nitride epitaxial layer having a second dopant concentration; wherein the first dopant concentration is less than the second dopant concentration. withdrawn
The method of claim 16 further comprising forming a metal layer coupled to the second I ll-nitride layer. Page 6 of 7 withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
vertical bipolar transistor
Materials described outside the worked examples.
III-nitride
III-nitride base contact material
dielectric
Measurements and analyses referenced in the patent, with their drawing references.
FIGS. 1-12 are provided as an example only, and are not limiting. Furthermore, the figures are not drawn to scale, and the manufacture of the vertical bipolar …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 100–300 nm | — |
Temperature | 600–800 °C |
Related documents with shared materials, methods, properties, or citations.
indium gallium nitride
InGaN
metal
gallium nitride
GaN
FIG. 3, the second dielectric layer 310 can be a conformal layer. The thickness 315 of the second dielectric layer 310 can be chosen based on desired spacer …
FIG. 13 is simplified flowchart illustrating a method of fabricating a vertical bipolar 25 transistor, according to an embodiment of the present invention. The …
| — |
Thickness | 50–1000 nm | — |
Thickness | ≤ 1 nm | — |
indium gallium nitride
InGaN
metal
gallium nitride
GaN
FIG. 3, the second dielectric layer 310 can be a conformal layer. The thickness 315 of the second dielectric layer 310 can be chosen based on desired spacer …
FIG. 13 is simplified flowchart illustrating a method of fabricating a vertical bipolar 25 transistor, according to an embodiment of the present invention. The …
| — |
Thickness | 50–1000 nm | — |
Thickness | ≤ 1 nm | — |
indium gallium nitride
InGaN
metal
gallium nitride
GaN
FIG. 3, the second dielectric layer 310 can be a conformal layer. The thickness 315 of the second dielectric layer 310 can be chosen based on desired spacer …
FIG. 13 is simplified flowchart illustrating a method of fabricating a vertical bipolar 25 transistor, according to an embodiment of the present invention. The …
| — |
Thickness | 50–1000 nm | — |
Thickness | ≤ 1 nm | — |
indium gallium nitride
InGaN
metal
gallium nitride
GaN
FIG. 3, the second dielectric layer 310 can be a conformal layer. The thickness 315 of the second dielectric layer 310 can be chosen based on desired spacer …
FIG. 13 is simplified flowchart illustrating a method of fabricating a vertical bipolar 25 transistor, according to an embodiment of the present invention. The …
| — |
Thickness | 50–1000 nm | — |
Thickness | ≤ 1 nm | — |