Patent
Atlas literature
Patent
US 12,520,547 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a partial sectional side elevation view of an electronic device with first and second depletion mode gallium nitride transistors with an aluminum …
FIG. 2 is a partial sectional side elevation view of another electronic device with first and second enhancement mode gallium nitride transistors with an …
FIG. 3 is a partial sectional side elevation view of an electronic device with first and second depletion mode gallium nitride transistors with an aluminum …
FIG. 4 is a partial sectional side elevation view of an electronic device with first and second enhancement mode gallium nitride transistors with an aluminum …
FIG. 5 is a partial sectional side elevation view of an electronic device with first and second depletion mode gallium nitride transistors with an aluminum …
FIG. 6 is a partial sectional side elevation view of an electronic device with first and second enhancement mode gallium nitride transistors with an aluminum …
FIG. 7 is a partial sectional side elevation view of an electronic device with first and second depletion mode gallium nitride transistors with an aluminum …
FIG. 8 is a partial sectional side elevation view of an 5 electronic device with first and second enhancement mode gallium nitride transistors with an aluminum …
FIG. 9.
FIGS. 10-20 are partial sectional side elevation views of the electronic device of
FIG. 11 shows one example, in 50 which an epitaxial deposition process 1100 is performed that deposits the first aluminum gallium nitride sublayer 111 over the …
FIG. 12 shows one example, in which a second epitaxial deposition process 65 1200 is performed that deposits the second aluminum gal- lium nitride sublayer 112 …
FIG. 13 shows one example, in which a third epitaxial deposition process 1300 is performed that deposits the third aluminum gallium nitride sublayer 113 with …
FIG. 14 shows one example, in which an epitaxial deposition process 1400 is performed that deposits the gallium nitride layer 114 over the top side of the …
FIG. 15 shows one example, in which an epitaxial deposition process 1500 is performed that deposits the aluminum gallium nitride back barrier layer 116 on the …
FIG. 16 shows one example, in which an epitaxial deposition process 1600 is performed that deposits the gallium nitride layer 118 on the back barrier layer 116 …
FIG. 17. In one example, the process 1700 deposits the aluminum nitride layer 120 to a thickness of about 10 Å (1 nm) at a process temperature of 900-1100° C. …
FIG. 18. In one example, the process 1800 forms the aluminum gallium nitride layer 121 to a thickness of 10-30 nm at a process temperature of 900-1100° C. The …
FIG. 19 5 shows one example, in which a process 1900 is performed that forms the P-doped gallium nitride layer 124 over a portion of the aluminum gallium …
FIG. 20 shows one example with metallization process 2000 that forms the metallization structure described above in con- nection with
FIG. 21 is a perspective view of a packaged electronic device.
FIG. 35. The method 900 further also includes forming the gate, drain and source and other conductive structures (e.g., 125, 131, 132, 134, 135, 136 and 138 in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit, comprising: a buffer structure over a substrate; a first III-N layer over the buffer structure including aluminum; a gallium nitride layer over the first III-N layer; a second III-N layer over the gallium nitride layer includ-ing aluminum; a transistor having a drain contact, a gate contact and a source contact spaced apart along the second III-N layer; and a gallium nitride structure over the second III-N layer, and a terminal connected to the gallium nitride structure, wherein the terminal is configured to provide a potential to the gallium nitride structure that causes a hole layer to form at an interface between the first III-N layer and the gallium nitride layer.
The integrated circuit of claim 1, wherein the transistor is a first transistor, the drain contact is a first drain contact, the gate contact is a first gate contact and the source contact is a first source contact, and further comprising: a second transistor having a second drain contact, a second gate contact and a second source contact spaced apart along the second III-N layer; and an isolation structure extending through the first III-N layer between the first and second transistors.
The integrated circuit of claim 1, wherein the transistor is a depletion mode transistor and the gate contact is in direct contact with the second III-N layer.
The integrated circuit of claim 1, wherein the transistor is an enhancement mode transistor and a doped gallium nitride layer is between the gate contact and the second III-N layer.
The integrated circuit of claim 1, wherein the terminal is electrically connected to the drain contact.
The integrated circuit of claim 1, wherein the gallium nitride structure contacts the drain contact.
The integrated circuit of claim 1, wherein the drain contact is spaced apart from and between the gallium nitride structure and the gate contact.
The integrated circuit of claim 1, wherein the gallium nitride structure is spaced apart from and between the drain contact and the gate contact.
The integrated circuit of claim 1, wherein the gallium nitride structure is spaced apart from and between the gate contact and the source contact.
The integrated circuit of claim 1, wherein the gallium nitride structure is electrically connected to the gate contact.
An electronic device, comprising: a semiconductor die in a device package, the semicon-ductor die having a switching circuit formed thereover, the switching circuit including a heterojunction first transistor including: 20 a first semiconductor layer including one of aluminum gallium nitride, aluminum nitride, indium aluminum nitride, and indium aluminum gallium nitride; a second semiconductor layer including gallium nitride on the first semiconductor layer; and 25 a third semiconductor layer including aluminum and nitrogen layer on the second semiconductor layer; a first source terminal, a first drain terminal and a first gate terminal on the third semiconductor layer; and a gallium nitride layer on the third semiconductor layer; and a second transistor having a second drain terminal, a second gate terminal and a second source terminal spaced apart along the third semiconductor layer; and a conductive connection between the first source terminal and the second drain terminal.
The electronic device of claim 15, wherein the gallium nitride layer is configured to receive a potential that causes a hole layer to form at an interface between the first and second semiconductor layers.
A method of fabricating an electronic device, the method comprising: forming a first transistor over a semiconductor substrate, the first transistor including: a first semiconductor layer over a semiconductor substrate, the first semiconductor layer including alumi-num gallium nitride, aluminum nitride, indium alu-minum nitride, or indium aluminum gallium nitride; a second semiconductor layer including gallium nitride on the first semiconductor layer; 50 a third semiconductor layer including aluminum and nitrogen over the second semiconductor layer; and B₂ a conductive first source terminal, a first drain terminal and a first gate terminal on the third semiconductor layer; forming a second transistor over the semiconductor substrate, the second transistor having a second drain terminal, a second gate terminal and a second source terminal spaced apart along the third semiconductor layer; forming a gallium nitride structure on the third semiconductor layer; connecting an electrode to the gallium nitride structure; and electrically connecting the first source terminal to the second drain terminal.
An electronic device, comprising: a semiconductor die in a device package, the semicon-ductor die having a switching circuit formed thereover, the switching circuit including a heterojunction tran-sistor including: a first semiconductor layer including one of aluminum gallium nitride, aluminum nitride, indium aluminum nitride, and indium aluminum gallium nitride; a second semiconductor layer including gallium nitride on the first semiconductor layer; and a third semiconductor layer including aluminum and nitrogen layer on the second semiconductor layer; a source terminal, a drain terminal and a gate terminal on the third semiconductor layer; and a gallium nitride layer on the third semiconductor layer, wherein the gallium nitride layer is configured to receive a potential that causes a hole layer to form at an interface between the first and second semiconductor layers.
An integrated circuit, comprising: a buffer structure over a substrate; a first III-N layer over the buffer structure including aluminum; a gallium nitride layer over the first III-N layer; a second III-N layer over the gallium nitride layer includ-ing aluminum; a first transistor having a first drain contact, a first gate contact and a first source contact spaced apart along the second III-N layer; and a second transistor having a second drain contact, a second gate contact and a second source contact spaced apart along the second III-N layer; and an isolation structure extending through the first III-N layer between the first and second transistors; a gallium nitride structure over the second III-N layer, and a terminal connected to the gallium nitride structure; and a conductive connection from the first source contact to the second drain contact. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
monolithic high/low-side GaN FET integrated circuit with hole injector
Materials described outside the worked examples.
first III-N layer including aluminum (back barrier)
gallium nitride
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a partial sectional side elevation view of an electronic device with first and second depletion mode gallium nitride transistors with an aluminum …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 20–5000 nm | — |
Thickness | 300–600 nm |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 6
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,520,547 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a partial sectional side elevation view of an electronic device with first and second depletion mode gallium nitride transistors with an aluminum …
FIG. 2 is a partial sectional side elevation view of another electronic device with first and second enhancement mode gallium nitride transistors with an …
FIG. 3 is a partial sectional side elevation view of an electronic device with first and second depletion mode gallium nitride transistors with an aluminum …
FIG. 4 is a partial sectional side elevation view of an electronic device with first and second enhancement mode gallium nitride transistors with an aluminum …
FIG. 5 is a partial sectional side elevation view of an electronic device with first and second depletion mode gallium nitride transistors with an aluminum …
FIG. 6 is a partial sectional side elevation view of an electronic device with first and second enhancement mode gallium nitride transistors with an aluminum …
FIG. 7 is a partial sectional side elevation view of an electronic device with first and second depletion mode gallium nitride transistors with an aluminum …
FIG. 8 is a partial sectional side elevation view of an 5 electronic device with first and second enhancement mode gallium nitride transistors with an aluminum …
FIG. 9.
FIGS. 10-20 are partial sectional side elevation views of the electronic device of
FIG. 11 shows one example, in 50 which an epitaxial deposition process 1100 is performed that deposits the first aluminum gallium nitride sublayer 111 over the …
FIG. 12 shows one example, in which a second epitaxial deposition process 65 1200 is performed that deposits the second aluminum gal- lium nitride sublayer 112 …
FIG. 13 shows one example, in which a third epitaxial deposition process 1300 is performed that deposits the third aluminum gallium nitride sublayer 113 with …
FIG. 14 shows one example, in which an epitaxial deposition process 1400 is performed that deposits the gallium nitride layer 114 over the top side of the …
FIG. 15 shows one example, in which an epitaxial deposition process 1500 is performed that deposits the aluminum gallium nitride back barrier layer 116 on the …
FIG. 16 shows one example, in which an epitaxial deposition process 1600 is performed that deposits the gallium nitride layer 118 on the back barrier layer 116 …
FIG. 17. In one example, the process 1700 deposits the aluminum nitride layer 120 to a thickness of about 10 Å (1 nm) at a process temperature of 900-1100° C. …
FIG. 18. In one example, the process 1800 forms the aluminum gallium nitride layer 121 to a thickness of 10-30 nm at a process temperature of 900-1100° C. The …
FIG. 19 5 shows one example, in which a process 1900 is performed that forms the P-doped gallium nitride layer 124 over a portion of the aluminum gallium …
FIG. 20 shows one example with metallization process 2000 that forms the metallization structure described above in con- nection with
FIG. 21 is a perspective view of a packaged electronic device.
FIG. 35. The method 900 further also includes forming the gate, drain and source and other conductive structures (e.g., 125, 131, 132, 134, 135, 136 and 138 in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit, comprising: a buffer structure over a substrate; a first III-N layer over the buffer structure including aluminum; a gallium nitride layer over the first III-N layer; a second III-N layer over the gallium nitride layer includ-ing aluminum; a transistor having a drain contact, a gate contact and a source contact spaced apart along the second III-N layer; and a gallium nitride structure over the second III-N layer, and a terminal connected to the gallium nitride structure, wherein the terminal is configured to provide a potential to the gallium nitride structure that causes a hole layer to form at an interface between the first III-N layer and the gallium nitride layer.
The integrated circuit of claim 1, wherein the transistor is a first transistor, the drain contact is a first drain contact, the gate contact is a first gate contact and the source contact is a first source contact, and further comprising: a second transistor having a second drain contact, a second gate contact and a second source contact spaced apart along the second III-N layer; and an isolation structure extending through the first III-N layer between the first and second transistors.
The integrated circuit of claim 1, wherein the transistor is a depletion mode transistor and the gate contact is in direct contact with the second III-N layer.
The integrated circuit of claim 1, wherein the transistor is an enhancement mode transistor and a doped gallium nitride layer is between the gate contact and the second III-N layer.
The integrated circuit of claim 1, wherein the terminal is electrically connected to the drain contact.
The integrated circuit of claim 1, wherein the gallium nitride structure contacts the drain contact.
The integrated circuit of claim 1, wherein the drain contact is spaced apart from and between the gallium nitride structure and the gate contact.
The integrated circuit of claim 1, wherein the gallium nitride structure is spaced apart from and between the drain contact and the gate contact.
The integrated circuit of claim 1, wherein the gallium nitride structure is spaced apart from and between the gate contact and the source contact.
The integrated circuit of claim 1, wherein the gallium nitride structure is electrically connected to the gate contact.
An electronic device, comprising: a semiconductor die in a device package, the semicon-ductor die having a switching circuit formed thereover, the switching circuit including a heterojunction first transistor including: 20 a first semiconductor layer including one of aluminum gallium nitride, aluminum nitride, indium aluminum nitride, and indium aluminum gallium nitride; a second semiconductor layer including gallium nitride on the first semiconductor layer; and 25 a third semiconductor layer including aluminum and nitrogen layer on the second semiconductor layer; a first source terminal, a first drain terminal and a first gate terminal on the third semiconductor layer; and a gallium nitride layer on the third semiconductor layer; and a second transistor having a second drain terminal, a second gate terminal and a second source terminal spaced apart along the third semiconductor layer; and a conductive connection between the first source terminal and the second drain terminal.
The electronic device of claim 15, wherein the gallium nitride layer is configured to receive a potential that causes a hole layer to form at an interface between the first and second semiconductor layers.
A method of fabricating an electronic device, the method comprising: forming a first transistor over a semiconductor substrate, the first transistor including: a first semiconductor layer over a semiconductor substrate, the first semiconductor layer including alumi-num gallium nitride, aluminum nitride, indium alu-minum nitride, or indium aluminum gallium nitride; a second semiconductor layer including gallium nitride on the first semiconductor layer; 50 a third semiconductor layer including aluminum and nitrogen over the second semiconductor layer; and B₂ a conductive first source terminal, a first drain terminal and a first gate terminal on the third semiconductor layer; forming a second transistor over the semiconductor substrate, the second transistor having a second drain terminal, a second gate terminal and a second source terminal spaced apart along the third semiconductor layer; forming a gallium nitride structure on the third semiconductor layer; connecting an electrode to the gallium nitride structure; and electrically connecting the first source terminal to the second drain terminal.
An electronic device, comprising: a semiconductor die in a device package, the semicon-ductor die having a switching circuit formed thereover, the switching circuit including a heterojunction tran-sistor including: a first semiconductor layer including one of aluminum gallium nitride, aluminum nitride, indium aluminum nitride, and indium aluminum gallium nitride; a second semiconductor layer including gallium nitride on the first semiconductor layer; and a third semiconductor layer including aluminum and nitrogen layer on the second semiconductor layer; a source terminal, a drain terminal and a gate terminal on the third semiconductor layer; and a gallium nitride layer on the third semiconductor layer, wherein the gallium nitride layer is configured to receive a potential that causes a hole layer to form at an interface between the first and second semiconductor layers.
An integrated circuit, comprising: a buffer structure over a substrate; a first III-N layer over the buffer structure including aluminum; a gallium nitride layer over the first III-N layer; a second III-N layer over the gallium nitride layer includ-ing aluminum; a first transistor having a first drain contact, a first gate contact and a first source contact spaced apart along the second III-N layer; and a second transistor having a second drain contact, a second gate contact and a second source contact spaced apart along the second III-N layer; and an isolation structure extending through the first III-N layer between the first and second transistors; a gallium nitride structure over the second III-N layer, and a terminal connected to the gallium nitride structure; and a conductive connection from the first source contact to the second drain contact. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
monolithic high/low-side GaN FET integrated circuit with hole injector
Materials described outside the worked examples.
first III-N layer including aluminum (back barrier)
gallium nitride
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a partial sectional side elevation view of an electronic device with first and second depletion mode gallium nitride transistors with an aluminum …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 20–5000 nm | — |
Thickness | 300–600 nm |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 6
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,520,547 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a partial sectional side elevation view of an electronic device with first and second depletion mode gallium nitride transistors with an aluminum …
FIG. 2 is a partial sectional side elevation view of another electronic device with first and second enhancement mode gallium nitride transistors with an …
FIG. 3 is a partial sectional side elevation view of an electronic device with first and second depletion mode gallium nitride transistors with an aluminum …
FIG. 4 is a partial sectional side elevation view of an electronic device with first and second enhancement mode gallium nitride transistors with an aluminum …
FIG. 5 is a partial sectional side elevation view of an electronic device with first and second depletion mode gallium nitride transistors with an aluminum …
FIG. 6 is a partial sectional side elevation view of an electronic device with first and second enhancement mode gallium nitride transistors with an aluminum …
FIG. 7 is a partial sectional side elevation view of an electronic device with first and second depletion mode gallium nitride transistors with an aluminum …
FIG. 8 is a partial sectional side elevation view of an 5 electronic device with first and second enhancement mode gallium nitride transistors with an aluminum …
FIG. 9.
FIGS. 10-20 are partial sectional side elevation views of the electronic device of
FIG. 11 shows one example, in 50 which an epitaxial deposition process 1100 is performed that deposits the first aluminum gallium nitride sublayer 111 over the …
FIG. 12 shows one example, in which a second epitaxial deposition process 65 1200 is performed that deposits the second aluminum gal- lium nitride sublayer 112 …
FIG. 13 shows one example, in which a third epitaxial deposition process 1300 is performed that deposits the third aluminum gallium nitride sublayer 113 with …
FIG. 14 shows one example, in which an epitaxial deposition process 1400 is performed that deposits the gallium nitride layer 114 over the top side of the …
FIG. 15 shows one example, in which an epitaxial deposition process 1500 is performed that deposits the aluminum gallium nitride back barrier layer 116 on the …
FIG. 16 shows one example, in which an epitaxial deposition process 1600 is performed that deposits the gallium nitride layer 118 on the back barrier layer 116 …
FIG. 17. In one example, the process 1700 deposits the aluminum nitride layer 120 to a thickness of about 10 Å (1 nm) at a process temperature of 900-1100° C. …
FIG. 18. In one example, the process 1800 forms the aluminum gallium nitride layer 121 to a thickness of 10-30 nm at a process temperature of 900-1100° C. The …
FIG. 19 5 shows one example, in which a process 1900 is performed that forms the P-doped gallium nitride layer 124 over a portion of the aluminum gallium …
FIG. 20 shows one example with metallization process 2000 that forms the metallization structure described above in con- nection with
FIG. 21 is a perspective view of a packaged electronic device.
FIG. 35. The method 900 further also includes forming the gate, drain and source and other conductive structures (e.g., 125, 131, 132, 134, 135, 136 and 138 in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit, comprising: a buffer structure over a substrate; a first III-N layer over the buffer structure including aluminum; a gallium nitride layer over the first III-N layer; a second III-N layer over the gallium nitride layer includ-ing aluminum; a transistor having a drain contact, a gate contact and a source contact spaced apart along the second III-N layer; and a gallium nitride structure over the second III-N layer, and a terminal connected to the gallium nitride structure, wherein the terminal is configured to provide a potential to the gallium nitride structure that causes a hole layer to form at an interface between the first III-N layer and the gallium nitride layer.
The integrated circuit of claim 1, wherein the transistor is a first transistor, the drain contact is a first drain contact, the gate contact is a first gate contact and the source contact is a first source contact, and further comprising: a second transistor having a second drain contact, a second gate contact and a second source contact spaced apart along the second III-N layer; and an isolation structure extending through the first III-N layer between the first and second transistors.
The integrated circuit of claim 1, wherein the transistor is a depletion mode transistor and the gate contact is in direct contact with the second III-N layer.
The integrated circuit of claim 1, wherein the transistor is an enhancement mode transistor and a doped gallium nitride layer is between the gate contact and the second III-N layer.
The integrated circuit of claim 1, wherein the terminal is electrically connected to the drain contact.
The integrated circuit of claim 1, wherein the gallium nitride structure contacts the drain contact.
The integrated circuit of claim 1, wherein the drain contact is spaced apart from and between the gallium nitride structure and the gate contact.
The integrated circuit of claim 1, wherein the gallium nitride structure is spaced apart from and between the drain contact and the gate contact.
The integrated circuit of claim 1, wherein the gallium nitride structure is spaced apart from and between the gate contact and the source contact.
The integrated circuit of claim 1, wherein the gallium nitride structure is electrically connected to the gate contact.
An electronic device, comprising: a semiconductor die in a device package, the semicon-ductor die having a switching circuit formed thereover, the switching circuit including a heterojunction first transistor including: 20 a first semiconductor layer including one of aluminum gallium nitride, aluminum nitride, indium aluminum nitride, and indium aluminum gallium nitride; a second semiconductor layer including gallium nitride on the first semiconductor layer; and 25 a third semiconductor layer including aluminum and nitrogen layer on the second semiconductor layer; a first source terminal, a first drain terminal and a first gate terminal on the third semiconductor layer; and a gallium nitride layer on the third semiconductor layer; and a second transistor having a second drain terminal, a second gate terminal and a second source terminal spaced apart along the third semiconductor layer; and a conductive connection between the first source terminal and the second drain terminal.
The electronic device of claim 15, wherein the gallium nitride layer is configured to receive a potential that causes a hole layer to form at an interface between the first and second semiconductor layers.
A method of fabricating an electronic device, the method comprising: forming a first transistor over a semiconductor substrate, the first transistor including: a first semiconductor layer over a semiconductor substrate, the first semiconductor layer including alumi-num gallium nitride, aluminum nitride, indium alu-minum nitride, or indium aluminum gallium nitride; a second semiconductor layer including gallium nitride on the first semiconductor layer; 50 a third semiconductor layer including aluminum and nitrogen over the second semiconductor layer; and B₂ a conductive first source terminal, a first drain terminal and a first gate terminal on the third semiconductor layer; forming a second transistor over the semiconductor substrate, the second transistor having a second drain terminal, a second gate terminal and a second source terminal spaced apart along the third semiconductor layer; forming a gallium nitride structure on the third semiconductor layer; connecting an electrode to the gallium nitride structure; and electrically connecting the first source terminal to the second drain terminal.
An electronic device, comprising: a semiconductor die in a device package, the semicon-ductor die having a switching circuit formed thereover, the switching circuit including a heterojunction tran-sistor including: a first semiconductor layer including one of aluminum gallium nitride, aluminum nitride, indium aluminum nitride, and indium aluminum gallium nitride; a second semiconductor layer including gallium nitride on the first semiconductor layer; and a third semiconductor layer including aluminum and nitrogen layer on the second semiconductor layer; a source terminal, a drain terminal and a gate terminal on the third semiconductor layer; and a gallium nitride layer on the third semiconductor layer, wherein the gallium nitride layer is configured to receive a potential that causes a hole layer to form at an interface between the first and second semiconductor layers.
An integrated circuit, comprising: a buffer structure over a substrate; a first III-N layer over the buffer structure including aluminum; a gallium nitride layer over the first III-N layer; a second III-N layer over the gallium nitride layer includ-ing aluminum; a first transistor having a first drain contact, a first gate contact and a first source contact spaced apart along the second III-N layer; and a second transistor having a second drain contact, a second gate contact and a second source contact spaced apart along the second III-N layer; and an isolation structure extending through the first III-N layer between the first and second transistors; a gallium nitride structure over the second III-N layer, and a terminal connected to the gallium nitride structure; and a conductive connection from the first source contact to the second drain contact. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
monolithic high/low-side GaN FET integrated circuit with hole injector
Materials described outside the worked examples.
first III-N layer including aluminum (back barrier)
gallium nitride
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a partial sectional side elevation view of an electronic device with first and second depletion mode gallium nitride transistors with an aluminum …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 20–5000 nm | — |
Thickness | 300–600 nm |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 6
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,520,547 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a partial sectional side elevation view of an electronic device with first and second depletion mode gallium nitride transistors with an aluminum …
FIG. 2 is a partial sectional side elevation view of another electronic device with first and second enhancement mode gallium nitride transistors with an …
FIG. 3 is a partial sectional side elevation view of an electronic device with first and second depletion mode gallium nitride transistors with an aluminum …
FIG. 4 is a partial sectional side elevation view of an electronic device with first and second enhancement mode gallium nitride transistors with an aluminum …
FIG. 5 is a partial sectional side elevation view of an electronic device with first and second depletion mode gallium nitride transistors with an aluminum …
FIG. 6 is a partial sectional side elevation view of an electronic device with first and second enhancement mode gallium nitride transistors with an aluminum …
FIG. 7 is a partial sectional side elevation view of an electronic device with first and second depletion mode gallium nitride transistors with an aluminum …
FIG. 8 is a partial sectional side elevation view of an 5 electronic device with first and second enhancement mode gallium nitride transistors with an aluminum …
FIG. 9.
FIGS. 10-20 are partial sectional side elevation views of the electronic device of
FIG. 11 shows one example, in 50 which an epitaxial deposition process 1100 is performed that deposits the first aluminum gallium nitride sublayer 111 over the …
FIG. 12 shows one example, in which a second epitaxial deposition process 65 1200 is performed that deposits the second aluminum gal- lium nitride sublayer 112 …
FIG. 13 shows one example, in which a third epitaxial deposition process 1300 is performed that deposits the third aluminum gallium nitride sublayer 113 with …
FIG. 14 shows one example, in which an epitaxial deposition process 1400 is performed that deposits the gallium nitride layer 114 over the top side of the …
FIG. 15 shows one example, in which an epitaxial deposition process 1500 is performed that deposits the aluminum gallium nitride back barrier layer 116 on the …
FIG. 16 shows one example, in which an epitaxial deposition process 1600 is performed that deposits the gallium nitride layer 118 on the back barrier layer 116 …
FIG. 17. In one example, the process 1700 deposits the aluminum nitride layer 120 to a thickness of about 10 Å (1 nm) at a process temperature of 900-1100° C. …
FIG. 18. In one example, the process 1800 forms the aluminum gallium nitride layer 121 to a thickness of 10-30 nm at a process temperature of 900-1100° C. The …
FIG. 19 5 shows one example, in which a process 1900 is performed that forms the P-doped gallium nitride layer 124 over a portion of the aluminum gallium …
FIG. 20 shows one example with metallization process 2000 that forms the metallization structure described above in con- nection with
FIG. 21 is a perspective view of a packaged electronic device.
FIG. 35. The method 900 further also includes forming the gate, drain and source and other conductive structures (e.g., 125, 131, 132, 134, 135, 136 and 138 in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit, comprising: a buffer structure over a substrate; a first III-N layer over the buffer structure including aluminum; a gallium nitride layer over the first III-N layer; a second III-N layer over the gallium nitride layer includ-ing aluminum; a transistor having a drain contact, a gate contact and a source contact spaced apart along the second III-N layer; and a gallium nitride structure over the second III-N layer, and a terminal connected to the gallium nitride structure, wherein the terminal is configured to provide a potential to the gallium nitride structure that causes a hole layer to form at an interface between the first III-N layer and the gallium nitride layer.
The integrated circuit of claim 1, wherein the transistor is a first transistor, the drain contact is a first drain contact, the gate contact is a first gate contact and the source contact is a first source contact, and further comprising: a second transistor having a second drain contact, a second gate contact and a second source contact spaced apart along the second III-N layer; and an isolation structure extending through the first III-N layer between the first and second transistors.
The integrated circuit of claim 1, wherein the transistor is a depletion mode transistor and the gate contact is in direct contact with the second III-N layer.
The integrated circuit of claim 1, wherein the transistor is an enhancement mode transistor and a doped gallium nitride layer is between the gate contact and the second III-N layer.
The integrated circuit of claim 1, wherein the terminal is electrically connected to the drain contact.
The integrated circuit of claim 1, wherein the gallium nitride structure contacts the drain contact.
The integrated circuit of claim 1, wherein the drain contact is spaced apart from and between the gallium nitride structure and the gate contact.
The integrated circuit of claim 1, wherein the gallium nitride structure is spaced apart from and between the drain contact and the gate contact.
The integrated circuit of claim 1, wherein the gallium nitride structure is spaced apart from and between the gate contact and the source contact.
The integrated circuit of claim 1, wherein the gallium nitride structure is electrically connected to the gate contact.
An electronic device, comprising: a semiconductor die in a device package, the semicon-ductor die having a switching circuit formed thereover, the switching circuit including a heterojunction first transistor including: 20 a first semiconductor layer including one of aluminum gallium nitride, aluminum nitride, indium aluminum nitride, and indium aluminum gallium nitride; a second semiconductor layer including gallium nitride on the first semiconductor layer; and 25 a third semiconductor layer including aluminum and nitrogen layer on the second semiconductor layer; a first source terminal, a first drain terminal and a first gate terminal on the third semiconductor layer; and a gallium nitride layer on the third semiconductor layer; and a second transistor having a second drain terminal, a second gate terminal and a second source terminal spaced apart along the third semiconductor layer; and a conductive connection between the first source terminal and the second drain terminal.
The electronic device of claim 15, wherein the gallium nitride layer is configured to receive a potential that causes a hole layer to form at an interface between the first and second semiconductor layers.
A method of fabricating an electronic device, the method comprising: forming a first transistor over a semiconductor substrate, the first transistor including: a first semiconductor layer over a semiconductor substrate, the first semiconductor layer including alumi-num gallium nitride, aluminum nitride, indium alu-minum nitride, or indium aluminum gallium nitride; a second semiconductor layer including gallium nitride on the first semiconductor layer; 50 a third semiconductor layer including aluminum and nitrogen over the second semiconductor layer; and B₂ a conductive first source terminal, a first drain terminal and a first gate terminal on the third semiconductor layer; forming a second transistor over the semiconductor substrate, the second transistor having a second drain terminal, a second gate terminal and a second source terminal spaced apart along the third semiconductor layer; forming a gallium nitride structure on the third semiconductor layer; connecting an electrode to the gallium nitride structure; and electrically connecting the first source terminal to the second drain terminal.
An electronic device, comprising: a semiconductor die in a device package, the semicon-ductor die having a switching circuit formed thereover, the switching circuit including a heterojunction tran-sistor including: a first semiconductor layer including one of aluminum gallium nitride, aluminum nitride, indium aluminum nitride, and indium aluminum gallium nitride; a second semiconductor layer including gallium nitride on the first semiconductor layer; and a third semiconductor layer including aluminum and nitrogen layer on the second semiconductor layer; a source terminal, a drain terminal and a gate terminal on the third semiconductor layer; and a gallium nitride layer on the third semiconductor layer, wherein the gallium nitride layer is configured to receive a potential that causes a hole layer to form at an interface between the first and second semiconductor layers.
An integrated circuit, comprising: a buffer structure over a substrate; a first III-N layer over the buffer structure including aluminum; a gallium nitride layer over the first III-N layer; a second III-N layer over the gallium nitride layer includ-ing aluminum; a first transistor having a first drain contact, a first gate contact and a first source contact spaced apart along the second III-N layer; and a second transistor having a second drain contact, a second gate contact and a second source contact spaced apart along the second III-N layer; and an isolation structure extending through the first III-N layer between the first and second transistors; a gallium nitride structure over the second III-N layer, and a terminal connected to the gallium nitride structure; and a conductive connection from the first source contact to the second drain contact. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
monolithic high/low-side GaN FET integrated circuit with hole injector
Materials described outside the worked examples.
first III-N layer including aluminum (back barrier)
gallium nitride
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a partial sectional side elevation view of an electronic device with first and second depletion mode gallium nitride transistors with an aluminum …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 20–5000 nm | — |
Thickness | 300–600 nm |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 6
Related documents with shared materials, methods, properties, or citations.
heterojunction GaN FET half-bridge electronic device in package
single heterojunction GaN FET with hole injector in package
second III-N layer including aluminum (barrier/heteroepitaxy)
first semiconductor layer: aluminum gallium nitride, aluminum nitride, indium aluminum nitride, or indium aluminum gallium nitride
third semiconductor layer including aluminum and nitrogen
aluminum nitride
AlN
aluminum gallium nitride buffer stack
AlGaN
silicon substrate
Si
FIG. 2 is a partial sectional side elevation view of another electronic device with first and second enhancement mode gallium nitride transistors with an …
FIG. 3 is a partial sectional side elevation view of an electronic device with first and second depletion mode gallium nitride transistors with an aluminum …
FIG. 4 is a partial sectional side elevation view of an electronic device with first and second enhancement mode gallium nitride transistors with an aluminum …
FIG. 5 is a partial sectional side elevation view of an electronic device with first and second depletion mode gallium nitride transistors with an aluminum …
FIG. 6 is a partial sectional side elevation view of an electronic device with first and second enhancement mode gallium nitride transistors with an aluminum …
FIG. 7 is a partial sectional side elevation view of an electronic device with first and second depletion mode gallium nitride transistors with an aluminum …
FIG. 8 is a partial sectional side elevation view of an 5 electronic device with first and second enhancement mode gallium nitride transistors with an aluminum …
FIG. 17. In one example, the process 1700 deposits the aluminum nitride layer 120 to a thickness of about 10 Å (1 nm) at a process temperature of 900-1100° C. …
FIG. 18. In one example, the process 1800 forms the aluminum gallium nitride layer 121 to a thickness of 10-30 nm at a process temperature of 900-1100° C. The …
| — |
Thickness | 1.4–1.8 µm | — |
Thickness | 1.4–2 µm | — |
Thickness | 0.5–2 µm | — |
Thickness | 0.1–1 µm | — |
Thickness | 10–30 nm | — |
Thickness | 10–20 nm | — |
Thickness | 50–200 nm | — |
Temperature | 1000–1150 °C | — |
Temperature | 900–1100 °C | — |
Temperature | 1000–1100 °C | — |
Thickness | 0.5–1 µm | — |
Temperature | 900–1050 °C | — |
Temperature | 950–1050 °C | — |
Cited non-patent literature · 2
heterojunction GaN FET half-bridge electronic device in package
single heterojunction GaN FET with hole injector in package
second III-N layer including aluminum (barrier/heteroepitaxy)
first semiconductor layer: aluminum gallium nitride, aluminum nitride, indium aluminum nitride, or indium aluminum gallium nitride
third semiconductor layer including aluminum and nitrogen
aluminum nitride
AlN
aluminum gallium nitride buffer stack
AlGaN
silicon substrate
Si
FIG. 2 is a partial sectional side elevation view of another electronic device with first and second enhancement mode gallium nitride transistors with an …
FIG. 3 is a partial sectional side elevation view of an electronic device with first and second depletion mode gallium nitride transistors with an aluminum …
FIG. 4 is a partial sectional side elevation view of an electronic device with first and second enhancement mode gallium nitride transistors with an aluminum …
FIG. 5 is a partial sectional side elevation view of an electronic device with first and second depletion mode gallium nitride transistors with an aluminum …
FIG. 6 is a partial sectional side elevation view of an electronic device with first and second enhancement mode gallium nitride transistors with an aluminum …
FIG. 7 is a partial sectional side elevation view of an electronic device with first and second depletion mode gallium nitride transistors with an aluminum …
FIG. 8 is a partial sectional side elevation view of an 5 electronic device with first and second enhancement mode gallium nitride transistors with an aluminum …
FIG. 17. In one example, the process 1700 deposits the aluminum nitride layer 120 to a thickness of about 10 Å (1 nm) at a process temperature of 900-1100° C. …
FIG. 18. In one example, the process 1800 forms the aluminum gallium nitride layer 121 to a thickness of 10-30 nm at a process temperature of 900-1100° C. The …
| — |
Thickness | 1.4–1.8 µm | — |
Thickness | 1.4–2 µm | — |
Thickness | 0.5–2 µm | — |
Thickness | 0.1–1 µm | — |
Thickness | 10–30 nm | — |
Thickness | 10–20 nm | — |
Thickness | 50–200 nm | — |
Temperature | 1000–1150 °C | — |
Temperature | 900–1100 °C | — |
Temperature | 1000–1100 °C | — |
Thickness | 0.5–1 µm | — |
Temperature | 900–1050 °C | — |
Temperature | 950–1050 °C | — |
Cited non-patent literature · 2
heterojunction GaN FET half-bridge electronic device in package
single heterojunction GaN FET with hole injector in package
second III-N layer including aluminum (barrier/heteroepitaxy)
first semiconductor layer: aluminum gallium nitride, aluminum nitride, indium aluminum nitride, or indium aluminum gallium nitride
third semiconductor layer including aluminum and nitrogen
aluminum nitride
AlN
aluminum gallium nitride buffer stack
AlGaN
silicon substrate
Si
FIG. 2 is a partial sectional side elevation view of another electronic device with first and second enhancement mode gallium nitride transistors with an …
FIG. 3 is a partial sectional side elevation view of an electronic device with first and second depletion mode gallium nitride transistors with an aluminum …
FIG. 4 is a partial sectional side elevation view of an electronic device with first and second enhancement mode gallium nitride transistors with an aluminum …
FIG. 5 is a partial sectional side elevation view of an electronic device with first and second depletion mode gallium nitride transistors with an aluminum …
FIG. 6 is a partial sectional side elevation view of an electronic device with first and second enhancement mode gallium nitride transistors with an aluminum …
FIG. 7 is a partial sectional side elevation view of an electronic device with first and second depletion mode gallium nitride transistors with an aluminum …
FIG. 8 is a partial sectional side elevation view of an 5 electronic device with first and second enhancement mode gallium nitride transistors with an aluminum …
FIG. 17. In one example, the process 1700 deposits the aluminum nitride layer 120 to a thickness of about 10 Å (1 nm) at a process temperature of 900-1100° C. …
FIG. 18. In one example, the process 1800 forms the aluminum gallium nitride layer 121 to a thickness of 10-30 nm at a process temperature of 900-1100° C. The …
| — |
Thickness | 1.4–1.8 µm | — |
Thickness | 1.4–2 µm | — |
Thickness | 0.5–2 µm | — |
Thickness | 0.1–1 µm | — |
Thickness | 10–30 nm | — |
Thickness | 10–20 nm | — |
Thickness | 50–200 nm | — |
Temperature | 1000–1150 °C | — |
Temperature | 900–1100 °C | — |
Temperature | 1000–1100 °C | — |
Thickness | 0.5–1 µm | — |
Temperature | 900–1050 °C | — |
Temperature | 950–1050 °C | — |
Cited non-patent literature · 2
heterojunction GaN FET half-bridge electronic device in package
single heterojunction GaN FET with hole injector in package
second III-N layer including aluminum (barrier/heteroepitaxy)
first semiconductor layer: aluminum gallium nitride, aluminum nitride, indium aluminum nitride, or indium aluminum gallium nitride
third semiconductor layer including aluminum and nitrogen
aluminum nitride
AlN
aluminum gallium nitride buffer stack
AlGaN
silicon substrate
Si
FIG. 2 is a partial sectional side elevation view of another electronic device with first and second enhancement mode gallium nitride transistors with an …
FIG. 3 is a partial sectional side elevation view of an electronic device with first and second depletion mode gallium nitride transistors with an aluminum …
FIG. 4 is a partial sectional side elevation view of an electronic device with first and second enhancement mode gallium nitride transistors with an aluminum …
FIG. 5 is a partial sectional side elevation view of an electronic device with first and second depletion mode gallium nitride transistors with an aluminum …
FIG. 6 is a partial sectional side elevation view of an electronic device with first and second enhancement mode gallium nitride transistors with an aluminum …
FIG. 7 is a partial sectional side elevation view of an electronic device with first and second depletion mode gallium nitride transistors with an aluminum …
FIG. 8 is a partial sectional side elevation view of an 5 electronic device with first and second enhancement mode gallium nitride transistors with an aluminum …
FIG. 17. In one example, the process 1700 deposits the aluminum nitride layer 120 to a thickness of about 10 Å (1 nm) at a process temperature of 900-1100° C. …
FIG. 18. In one example, the process 1800 forms the aluminum gallium nitride layer 121 to a thickness of 10-30 nm at a process temperature of 900-1100° C. The …
| — |
Thickness | 1.4–1.8 µm | — |
Thickness | 1.4–2 µm | — |
Thickness | 0.5–2 µm | — |
Thickness | 0.1–1 µm | — |
Thickness | 10–30 nm | — |
Thickness | 10–20 nm | — |
Thickness | 50–200 nm | — |
Temperature | 1000–1150 °C | — |
Temperature | 900–1100 °C | — |
Temperature | 1000–1100 °C | — |
Thickness | 0.5–1 µm | — |
Temperature | 900–1050 °C | — |
Temperature | 950–1050 °C | — |
Cited non-patent literature · 2
