Patent
US 10,930,766GE NANO WIRE TRANSISTOR WITH GAAS AS THE SACRIFICIAL LAYER
Willy RACHMADY
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 10,930,766Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 shows top side perspective view of a portion of a semiconductor substrate, such as a portion of a wafer having a sacrificial fin formed thereon and a dielectric material adjacent the sacrificial fin.
Figure 2 shows the structure of
Figure 3 shows the structure of
Figure 4 shows the structure of
Figure 5 shows the structure of
Figure 6 shows the structure of
Figure 7 shows the structure of
Figure 8 shows the structure of
Figure 9 shows the structure of
Figure 10 shows the structure of
Figure 11 shows the structure of
Figure 12 shows a top front perspective view of an embodiment of a structure including a NMOS device and a PMOS device on a substrate in a CMOS implementation.
Figure 13 is an interposer implementing one or more embodiments.
Figure 14 illustrates an embodiment of a computing device.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
Canceled
An integrated circuit structure, comprising: a nanowire above a substrate, the nanowire having a channel region and junction regions on either side of the channel region, the nanowire comprising a group IV material having a first lattice constant; a semiconductor material beneath the junction regions of the nanowire, the semiconductor material comprising a group I II -V material having a second lattice constant similar to the first lattice constant, wherein the junction regions of the nanowire are on the semiconductor material; and a gate stack surrounding the channel region of the nanowire. Previously presented
The integrated circuit structure of claim 2, further comprising: a second nanowire above the nanowire, the second nanowire having a channel region and junction regions on either side of the channel region, the second nanowire comprising the group IV material; and a second semiconductor between the junction regions of the nanowire and the junction regions of the second nanowire, the second semiconductor material comprising the group I II -V material. Previously presented
The integrated circuit structure of claim 2, wherein the group IV material is germanium. Previously presented
The integrated circuit structure of claim 2, wherein the group I II -V material is gallium arsenide. Previously presented
The integrated circuit structure of claim 2, wherein the group IV material is germanium, and the group I II -V material is gallium arsenide. Previously presented
A method of fabricating an integrated circuit structure, the method comprising: forming a nanowire above a semiconductor material above a substrate, the nanowire comprising a group IV material having a first lattice constant, and the semiconductor material comprising a group I II -V material having a second lattice constant similar to the first lattice constant; removing a portion of the semiconductor material to form a channel region of the nanowire, wherein another portion of the semiconductor material remains beneath junction regions of the nanowire; and forming a gate stack surrounding the channel region of the nanowire. Previously presented
The method of claim 8, further comprising: forming a second nanowire above a second semiconductor material formed on the nanowire, the second nanowire comprising the group IV material, and the second semiconductor material comprising the group III -V material; and removing a portion of the second semiconductor material to form a channel region of the second nanowire. Previously presented
The method of claim 8, wherein the group IV material is germanium, and the group I II -V material is gallium arsenide. Previously presented
A computing device, comprising: a board; and a component coupled to the board, the component including an integrated circuit structure, comprising: a nanowire above a substrate, the nanowire having a channel region and junction regions on either side of the channel region, the nanowire comprising a group I V material having a first lattice constant; a semiconductor material beneath the junction regions of the nanowire, the semiconductor material comprising a group I II -V material having a second lattice constant similar to the first lattice constant, wherein the junction regions of the nanowire are on the semiconductor material; and a gate stack surrounding the channel region of the nanowire. Previously presented
The computing device of claim 13, further comprising: a memory coupled to the board. Previously presented
The computing device of claim 13, further comprising: a communication chip coupled to the board. Previously presented
The computing device of claim 13, further comprising: a camera coupled to the board. Previously presented
The computing device of claim 13, further comprising: a battery coupled to the board. Previously presented
The computing device of claim 13, further comprising: an antenna coupled to the board. Previously presented
The computing device of claim 13, wherein the component is a packaged integrated circuit die. Previously presented
The computing device of claim 13, wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor. Previously presented
The computing device of claim 13, wherein the computing device is selected from the group consisting of a mobile phone, a laptop, a desk top computer, a server, and a set-top box. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
gate-all-around nanowire transistor (MOSFET)
Materials described outside the worked examples.
group IV material (nanowire)
group III-V material (sacrificial/junction support)
Additional fabrication and treatment steps described in the patent.
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,930,766Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 shows top side perspective view of a portion of a semiconductor substrate, such as a portion of a wafer having a sacrificial fin formed thereon and a dielectric material adjacent the sacrificial fin.
Figure 2 shows the structure of
Figure 3 shows the structure of
Figure 4 shows the structure of
Figure 5 shows the structure of
Figure 6 shows the structure of
Figure 7 shows the structure of
Figure 8 shows the structure of
Figure 9 shows the structure of
Figure 10 shows the structure of
Figure 11 shows the structure of
Figure 12 shows a top front perspective view of an embodiment of a structure including a NMOS device and a PMOS device on a substrate in a CMOS implementation.
Figure 13 is an interposer implementing one or more embodiments.
Figure 14 illustrates an embodiment of a computing device.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
Canceled
An integrated circuit structure, comprising: a nanowire above a substrate, the nanowire having a channel region and junction regions on either side of the channel region, the nanowire comprising a group IV material having a first lattice constant; a semiconductor material beneath the junction regions of the nanowire, the semiconductor material comprising a group I II -V material having a second lattice constant similar to the first lattice constant, wherein the junction regions of the nanowire are on the semiconductor material; and a gate stack surrounding the channel region of the nanowire. Previously presented
The integrated circuit structure of claim 2, further comprising: a second nanowire above the nanowire, the second nanowire having a channel region and junction regions on either side of the channel region, the second nanowire comprising the group IV material; and a second semiconductor between the junction regions of the nanowire and the junction regions of the second nanowire, the second semiconductor material comprising the group I II -V material. Previously presented
The integrated circuit structure of claim 2, wherein the group IV material is germanium. Previously presented
The integrated circuit structure of claim 2, wherein the group I II -V material is gallium arsenide. Previously presented
The integrated circuit structure of claim 2, wherein the group IV material is germanium, and the group I II -V material is gallium arsenide. Previously presented
A method of fabricating an integrated circuit structure, the method comprising: forming a nanowire above a semiconductor material above a substrate, the nanowire comprising a group IV material having a first lattice constant, and the semiconductor material comprising a group I II -V material having a second lattice constant similar to the first lattice constant; removing a portion of the semiconductor material to form a channel region of the nanowire, wherein another portion of the semiconductor material remains beneath junction regions of the nanowire; and forming a gate stack surrounding the channel region of the nanowire. Previously presented
The method of claim 8, further comprising: forming a second nanowire above a second semiconductor material formed on the nanowire, the second nanowire comprising the group IV material, and the second semiconductor material comprising the group III -V material; and removing a portion of the second semiconductor material to form a channel region of the second nanowire. Previously presented
The method of claim 8, wherein the group IV material is germanium, and the group I II -V material is gallium arsenide. Previously presented
A computing device, comprising: a board; and a component coupled to the board, the component including an integrated circuit structure, comprising: a nanowire above a substrate, the nanowire having a channel region and junction regions on either side of the channel region, the nanowire comprising a group I V material having a first lattice constant; a semiconductor material beneath the junction regions of the nanowire, the semiconductor material comprising a group I II -V material having a second lattice constant similar to the first lattice constant, wherein the junction regions of the nanowire are on the semiconductor material; and a gate stack surrounding the channel region of the nanowire. Previously presented
The computing device of claim 13, further comprising: a memory coupled to the board. Previously presented
The computing device of claim 13, further comprising: a communication chip coupled to the board. Previously presented
The computing device of claim 13, further comprising: a camera coupled to the board. Previously presented
The computing device of claim 13, further comprising: a battery coupled to the board. Previously presented
The computing device of claim 13, further comprising: an antenna coupled to the board. Previously presented
The computing device of claim 13, wherein the component is a packaged integrated circuit die. Previously presented
The computing device of claim 13, wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor. Previously presented
The computing device of claim 13, wherein the computing device is selected from the group consisting of a mobile phone, a laptop, a desk top computer, a server, and a set-top box. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
gate-all-around nanowire transistor (MOSFET)
Materials described outside the worked examples.
group IV material (nanowire)
group III-V material (sacrificial/junction support)
Additional fabrication and treatment steps described in the patent.
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,930,766Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 shows top side perspective view of a portion of a semiconductor substrate, such as a portion of a wafer having a sacrificial fin formed thereon and a dielectric material adjacent the sacrificial fin.
Figure 2 shows the structure of
Figure 3 shows the structure of
Figure 4 shows the structure of
Figure 5 shows the structure of
Figure 6 shows the structure of
Figure 7 shows the structure of
Figure 8 shows the structure of
Figure 9 shows the structure of
Figure 10 shows the structure of
Figure 11 shows the structure of
Figure 12 shows a top front perspective view of an embodiment of a structure including a NMOS device and a PMOS device on a substrate in a CMOS implementation.
Figure 13 is an interposer implementing one or more embodiments.
Figure 14 illustrates an embodiment of a computing device.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
Canceled
An integrated circuit structure, comprising: a nanowire above a substrate, the nanowire having a channel region and junction regions on either side of the channel region, the nanowire comprising a group IV material having a first lattice constant; a semiconductor material beneath the junction regions of the nanowire, the semiconductor material comprising a group I II -V material having a second lattice constant similar to the first lattice constant, wherein the junction regions of the nanowire are on the semiconductor material; and a gate stack surrounding the channel region of the nanowire. Previously presented
The integrated circuit structure of claim 2, further comprising: a second nanowire above the nanowire, the second nanowire having a channel region and junction regions on either side of the channel region, the second nanowire comprising the group IV material; and a second semiconductor between the junction regions of the nanowire and the junction regions of the second nanowire, the second semiconductor material comprising the group I II -V material. Previously presented
The integrated circuit structure of claim 2, wherein the group IV material is germanium. Previously presented
The integrated circuit structure of claim 2, wherein the group I II -V material is gallium arsenide. Previously presented
The integrated circuit structure of claim 2, wherein the group IV material is germanium, and the group I II -V material is gallium arsenide. Previously presented
A method of fabricating an integrated circuit structure, the method comprising: forming a nanowire above a semiconductor material above a substrate, the nanowire comprising a group IV material having a first lattice constant, and the semiconductor material comprising a group I II -V material having a second lattice constant similar to the first lattice constant; removing a portion of the semiconductor material to form a channel region of the nanowire, wherein another portion of the semiconductor material remains beneath junction regions of the nanowire; and forming a gate stack surrounding the channel region of the nanowire. Previously presented
The method of claim 8, further comprising: forming a second nanowire above a second semiconductor material formed on the nanowire, the second nanowire comprising the group IV material, and the second semiconductor material comprising the group III -V material; and removing a portion of the second semiconductor material to form a channel region of the second nanowire. Previously presented
The method of claim 8, wherein the group IV material is germanium, and the group I II -V material is gallium arsenide. Previously presented
A computing device, comprising: a board; and a component coupled to the board, the component including an integrated circuit structure, comprising: a nanowire above a substrate, the nanowire having a channel region and junction regions on either side of the channel region, the nanowire comprising a group I V material having a first lattice constant; a semiconductor material beneath the junction regions of the nanowire, the semiconductor material comprising a group I II -V material having a second lattice constant similar to the first lattice constant, wherein the junction regions of the nanowire are on the semiconductor material; and a gate stack surrounding the channel region of the nanowire. Previously presented
The computing device of claim 13, further comprising: a memory coupled to the board. Previously presented
The computing device of claim 13, further comprising: a communication chip coupled to the board. Previously presented
The computing device of claim 13, further comprising: a camera coupled to the board. Previously presented
The computing device of claim 13, further comprising: a battery coupled to the board. Previously presented
The computing device of claim 13, further comprising: an antenna coupled to the board. Previously presented
The computing device of claim 13, wherein the component is a packaged integrated circuit die. Previously presented
The computing device of claim 13, wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor. Previously presented
The computing device of claim 13, wherein the computing device is selected from the group consisting of a mobile phone, a laptop, a desk top computer, a server, and a set-top box. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
gate-all-around nanowire transistor (MOSFET)
Materials described outside the worked examples.
group IV material (nanowire)
group III-V material (sacrificial/junction support)
Additional fabrication and treatment steps described in the patent.
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,930,766Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 shows top side perspective view of a portion of a semiconductor substrate, such as a portion of a wafer having a sacrificial fin formed thereon and a dielectric material adjacent the sacrificial fin.
Figure 2 shows the structure of
Figure 3 shows the structure of
Figure 4 shows the structure of
Figure 5 shows the structure of
Figure 6 shows the structure of
Figure 7 shows the structure of
Figure 8 shows the structure of
Figure 9 shows the structure of
Figure 10 shows the structure of
Figure 11 shows the structure of
Figure 12 shows a top front perspective view of an embodiment of a structure including a NMOS device and a PMOS device on a substrate in a CMOS implementation.
Figure 13 is an interposer implementing one or more embodiments.
Figure 14 illustrates an embodiment of a computing device.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
Canceled
An integrated circuit structure, comprising: a nanowire above a substrate, the nanowire having a channel region and junction regions on either side of the channel region, the nanowire comprising a group IV material having a first lattice constant; a semiconductor material beneath the junction regions of the nanowire, the semiconductor material comprising a group I II -V material having a second lattice constant similar to the first lattice constant, wherein the junction regions of the nanowire are on the semiconductor material; and a gate stack surrounding the channel region of the nanowire. Previously presented
The integrated circuit structure of claim 2, further comprising: a second nanowire above the nanowire, the second nanowire having a channel region and junction regions on either side of the channel region, the second nanowire comprising the group IV material; and a second semiconductor between the junction regions of the nanowire and the junction regions of the second nanowire, the second semiconductor material comprising the group I II -V material. Previously presented
The integrated circuit structure of claim 2, wherein the group IV material is germanium. Previously presented
The integrated circuit structure of claim 2, wherein the group I II -V material is gallium arsenide. Previously presented
The integrated circuit structure of claim 2, wherein the group IV material is germanium, and the group I II -V material is gallium arsenide. Previously presented
A method of fabricating an integrated circuit structure, the method comprising: forming a nanowire above a semiconductor material above a substrate, the nanowire comprising a group IV material having a first lattice constant, and the semiconductor material comprising a group I II -V material having a second lattice constant similar to the first lattice constant; removing a portion of the semiconductor material to form a channel region of the nanowire, wherein another portion of the semiconductor material remains beneath junction regions of the nanowire; and forming a gate stack surrounding the channel region of the nanowire. Previously presented
The method of claim 8, further comprising: forming a second nanowire above a second semiconductor material formed on the nanowire, the second nanowire comprising the group IV material, and the second semiconductor material comprising the group III -V material; and removing a portion of the second semiconductor material to form a channel region of the second nanowire. Previously presented
The method of claim 8, wherein the group IV material is germanium, and the group I II -V material is gallium arsenide. Previously presented
A computing device, comprising: a board; and a component coupled to the board, the component including an integrated circuit structure, comprising: a nanowire above a substrate, the nanowire having a channel region and junction regions on either side of the channel region, the nanowire comprising a group I V material having a first lattice constant; a semiconductor material beneath the junction regions of the nanowire, the semiconductor material comprising a group I II -V material having a second lattice constant similar to the first lattice constant, wherein the junction regions of the nanowire are on the semiconductor material; and a gate stack surrounding the channel region of the nanowire. Previously presented
The computing device of claim 13, further comprising: a memory coupled to the board. Previously presented
The computing device of claim 13, further comprising: a communication chip coupled to the board. Previously presented
The computing device of claim 13, further comprising: a camera coupled to the board. Previously presented
The computing device of claim 13, further comprising: a battery coupled to the board. Previously presented
The computing device of claim 13, further comprising: an antenna coupled to the board. Previously presented
The computing device of claim 13, wherein the component is a packaged integrated circuit die. Previously presented
The computing device of claim 13, wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor. Previously presented
The computing device of claim 13, wherein the computing device is selected from the group consisting of a mobile phone, a laptop, a desk top computer, a server, and a set-top box. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
gate-all-around nanowire transistor (MOSFET)
Materials described outside the worked examples.
group IV material (nanowire)
group III-V material (sacrificial/junction support)
Additional fabrication and treatment steps described in the patent.
Related documents with shared materials, methods, properties, or citations.
germanium
Ge
gallium arsenide
GaAs
silicon
Si
silicon germanium (buffer layer)
SiGe
germanium
Ge
gallium arsenide
GaAs
silicon
Si
silicon germanium (buffer layer)
SiGe
germanium
Ge
gallium arsenide
GaAs
silicon
Si
silicon germanium (buffer layer)
SiGe
germanium
Ge
gallium arsenide
GaAs
silicon
Si
silicon germanium (buffer layer)
SiGe