Patent
US 9,660,064GaN transistor layers with bi-layer capping stack
Sansaptak Dasgupta, Hui Wui Then, Marko Radosavljevic, Sanaz K. Gardner et al.
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 9,660,064Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 5 is an example process for for ming Ga N channel based tr ansistor layers inclu ing an mInAIN and AIGaN bi-ayer capping st ack on a G aN lay er. 1 0010 1
Figure 6 is a schemat ic cros s section v iew of a portion o f a semi conduc t or substraie base after forming a Galli um Nitride (G aN) channel bas e d transistor h aving a G aN layer grown out of trenches or ga ps in the Silicon subst rate; a nd an InAI N and A IG aN b i-layer capping stack on …
Figure 7 is a schematic cross section view of a portion of a semiconductor substrate base after forming a Gallium Nitride (G aN) channel based fin transistor having a G aN fin layer grown on a Silicon fin; and an In AIN and A I GaN bi -L ayer fin Capping Stack on a GaN f in layer. [0012 1
Figure 8 is a 3-dimensional (3D) cross section along the f in 790 of a portion of a semiconductor substrate base after forming a Gallium Nitride (GaN) channel based fin transistor from layer having a GaN fin layer grown on a Silicon fin; and an InAI N and AlGaN b i -Layer f in Capping Stack on the GaN …
Figure 9 illustrates a computing device, such as a system on a chip (SoC), in accordance with one implementation. only to th e parts shown, which a re meant merel fo th e purpose of illustratio n. A lso, while SVG 14141304.12-26-2013.HPOP₈VO₄PXXIFW3.SPEC.8.svg 1.9 6.27 Black and white SVG …
Figure 2). [0016 1 According to some embodiments, a 2-dimensional e lectron gas (2DEG) channel can be created in G aN layer of GaN transistors by capping the G aN l ayer with a single capping layer. The difference in spontaneous polarization and piezoelectric polarization due to strain in the …
Figure 1). Such transistor layers may be layers of material that are included in or part of a transistor. Such a transistor may be a GaN MOS-high electron mobility transistor (HEM T). T he transistor may be a flat, thin, or t ri-gate transistor; and top surface of the substrate may be single crystal …
Figure 3 and 6-8). I n so me cases, layers 100 may be part of or used to form a flat, thin, t ri- gate, or a G aN M OS-higth electron mobility transistor (HEMT). The transistor may be part of a volta g e r egul ator, a power management inte gra ted circuit (IC), a radio frequency (RL F) po w er …
Figure 4 sho w s plotted point 44 2 as the plot of c harge density 410 for an embodiment wit hout la y er 130 (e.g., w ithout an AIGaN laye r); a nd plo tte d point 444 as a plot of the mobility for that embodiment. Plot 400 shows plotted point 452 as the plot of charge density 410 for an …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method to form transistor layers comprising: forming a GaN channel layer efcom prising (1) GaN material on a top surface of a substrate _, wherein the GaN channel layer comprises a GaN stack having a plurality of GaN layers separated by channel AlN layers, and wherein the (2) a capping AIN layer that has a thickness of between 0.6 and 1.5 nanometers on the GaN material, wherein the GaN channel layer includes islands of GaN material formed between islands that consist of oxide material only that are completely buried under a thickness of the GaN material; for m ing a bi-layer capping stack on a top surface of the GaN channel layer, wherein forming the bi-layer capping stack includes: forming a lower capping AIGaN l ayer of AlGaN material on a top surface of a capping A I N layer comprising A I N material and excluding Indium for m ed on the top surface of the GaN channel layer; and forming an upper capping A l InN layer of AlInN material on a top surface of the Al GaN material, wherein the AlGaN layer comprises AlxGa 1 x) N, where X is less than 0.4; and wherein the A I InN layer is A lyIn(l y)N, where Y is greater than 0.8, wherein a top surface of the AIGaN material forms a setback material surface upon which the A l InN material may be selectively etched, wherein the A l GaN layer has a thickness of between 2 and 10 nm, and causes an electron density of greater than 2.5 E₁₃ cm/2; and wherein the Al I nN layer has a thickness of between 5 and 15 nm, and causes a channel mobility of between 900 and 1000 CM₂/V-s, wherein the bi-layer capping stack causes a sheet resistance of between 200 and 300 ohms per SQR in a 2DEG channel formed in a upper thickness of the GaN layer, and wherein the transistor layers are part of one of a voltage regulator, a power management integrated circuit (IC), a radio frequency (RF) power amplifier, or a system on a chip (SoC).
The method of claim 1, further comprising: forming a gate over a top surface of the AlGaN layer; and forming junction regions on the A I InN layer on either side of the gate.
The method of claim 1, wherein the AlGaN material is formed on and touching a top surface of AIN material of the capping A l N layer, wherein the A l N material excludes A l InN, and wherein the A I InN material is formed on and touching a top surface of the AI GaN material.
The method of claim 1, wherein the GaN channel layer includes islands of GaN material formed between islands of oxide material; and wherein the islands of GaN material have a width or diameter of between 50 and 250 n m, and have a thickness of between 50 and 250 nm.
The method of claim 1, wherein the top surface of the substrate includes a plurality of substrate fins having three sides of substrate material; wherein the GaN channel layer is formed on the three sides of the substrate material; wherein the top surface of the GaN channel layer includes three sides of GaN material; and wherein the bi-layer capping stack is formed on the three sides of the GaN material.
A method of claim 1, wherein the AlGaN layer has a thickness of 2 or 5 nanometers, the Al I nN layer has a thickness of 7 nanometers, and the A I N layer has a thickness of 1 nanometer.
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/141,304 2 Docket No. 42P₆₁₀₇₄
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The transistor layers of claim 11, further comprising: a gate over a top surface of the AlGaN layer; and junction regions on the A l InN layer on either side of the gate.
The transistor layers of claim 16, wherein the gate comprises: a gate dielectric over all of an exposed surface of the A l GaN material in a trench; and a metal gate electrode on the gate dielectric in the trench.
The transistor layers of claim 11, wherein the AlGaN layer has a predetermined thickness configured to cause electrons in a 2DEG cha nn el of the GaN material of the GaN channel layer to be subject to less interface roughness scattering and less alloy scattering, and thus provide a higher mobility than without the AlGaN layer.
canceled
A system for computing comprising: a microprocessor coupled to a memory, the microprocessor having at least one electronic transistor having transistor layers comprising: a GaN channel layer efcomprising (1) GaN material on a top surface of a substrate _, wherein the GaN channel layer comprises a GaN stack having a plurality of GaN layers separated by channel AIN layers, and wherein the(2) a capping A I N layer that has a thickness of between 0.6 and 1.5 nanometers on the GaN material, wherein the GaN channel layer includes islands of GaN material formed between islands that consist of oxide material only that are completely buried under a thickness of the GaN material; a bi-layer capping stack on a top surface of the GaN channel layer, wherein the bi- layer capping stack includes: a lower capping AlGaN layer of A l GaN material on a top surface of a capping A l N layer comprising A l N material and excluding Indium on the top surface of the GaN channel layer; and an upper capping A l InN layer of A l InN material on a top surface of the Al GaN material, wherein the AlGaN layer comprises A l xGa (v x)N, where X is less than 0.4; and wherein the A l InN layer is Aly In(t 1y) N, where Y is greater than 0.8, wherein a top surface of the AI GaN material forms a setback material surface upon which the A I InN material may be selectively etched, wherein the A l GaN layer has a thickness of between 2 and 10 nm, and causes an electron density of greater than 2.5 E₁₃ c m/2; and wherein the A I InN layer has a thickness of between 5 and 15 n m, and causes a channel mobility of between 900 and 1400 CM₂/V-s, wherein the bi-layer capping stack causes a sheet resistance of between 200 and 300 ohms per SQR in a 2DEG channel formed in a upper thickness of the GaN layer, and wherein the transistor is part of one of a voltage regulator, a power management integrated circuit (IC), a radio frequency (RF) power amplifier, or a system on a chip (SoC).
The system of claim 20, further comprising: a gate over a top surface of the AlGaN layer, wherein the gate comprises: a gate dielectric over all of an exposed surface of the AlGaN material in a trench; and a metal gate electrode on the gate dielectric in the trench; and junction regions on the A I InN layer on either side of the gate.
The system of claim 20, wherein the A l GaN material is formed on and touching a top surface of A l N material of the capping A l N layer, wherein the A lN material excludes A IIn N, and wherein the A l InN material is formed on and touching a top surface of the AlGaN material.
The system of claim 20, wherein the GaN channel layer includes islands of GaN material formed between islands of oxide material; and wherein the islands of GaN material have a width or diameter of between 50 and 250 nm, and have a thickness of between 50 and 250 nm.
The system of claim 20, wherein the top surface of the substrate includes a plurality of substrate f in s having three sides of substrate material; wherein the GaN cha nn el layer is f o rmed on the three sides of the substrate material; wherein the top surface of the GaN channel layer includes three sides of GaN material; and wherein the b i-la y er capping stack is formed on the three sides of the GaN material.
The system of claim 20, wherein the A l GaN layer has a thickness of 2 or 5 nanometers, the A l InN layer has a thickness of 7 nanometers, and the A lN layer has a thickness of 1 n anometer.
21-22. 14/141,30 4 5 Docket No. 42P₆₁₀₇₄ canceled
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The transistor of claim 11, wherein the AlGaN material is formed on and touching a top surface of A l N material of the capping A l N layer, wherein the A IN material excludes A lI nN, and wherein the A l InN material is formed on and touching a top surface of the AlGaN material.
canceled
The transistor of claim 11, wherein the GaN channel layer includes islands of GaN material formed between islands of oxide material; and wherein the islands of GaN material have a width or diameter of between 50 and 250 n m, and have a thickness of between 50 and 250 nm.
The transistor of claim 11, wherein the top surface of the substrate includes a plurality of substrate fins having three sides of substrate material; wherein the GaN channel layer is formed on the three sides of the substrate material; wherein the top surface of the GaN channel layer includes three sides of GaN material; and wherein the bi-layer capping stack is formed on the three sides of the GaN material.
The transistor of claim 11, wherein the A I GaN layer has a thickness of 2 or 5 nanometers, the A I InN layer has a thickness of 7 nanometers, and the A IN layer has a thickness of 1 nanometer.
A method to form transistor layers comprising: forming a GaN channel layer efcomprising (1) G aN material on a top surface of a substrate and (2) a capping AiN layer that has a thickness of between 0.6 and 1.5 nanometers on the GaN material, wherein the GaN channel layer includes islands of GaN material formed between islands that consist of oxide material only that are completely buried under a thickness of the GaN material; forming a bi-layer capping stack on a top surface of the G aN chann el layer, wherein forming the bi-layer capping stack includes: forming a lower capping AlGaN layer of A l GaN material on a top surface of a capping A I N layer comprising AIN material and excluding Indium formed on the top surface of the GaN channel layer; forming an upper capping A I InN layer of A l InN material on a top surface of the AI GaN material, wherein the AlGaN layer has a thickness of between 2 and 10 nm, and causes an electron density of greater than 2.5 E₁₃ cm/2; and wherein the A l InN layer has a thickness of between 5 and 15 n m, and causes a channel mobility of between 900 and 1000 CM₂/V-s, wherein the bi-layer capping stack causes a sheet resistance of between 200 and 300 ohms per SQR in a 2DEG channel formed in a upper thickness of the GaN layer, and wherein the transistor layers are part of one of a voltage regulator, a power management integrated circuit (IC), a radio frequency (RF) power amplifier, or a system on a chip (SoC); selectively etching the A lI nN material to expose a top surface of the AlGaN material, wherein selectively etching the A l InN material comprises using a wet etch including a solution to selectively etch the AlInN material but not etch the AlGaN material; 14/141,304 8 Docket No. 42P₆₁₀₇₄ forming a gate dielectric over all of the exposed surface of the A I GaN material; and forming a metal gate electrode on the gate dielectric.
A method of claim 38, wherein the AlGaN layer has a predetermined thickness configured to cause electrons in a 2DEG channel of the GaN material of the GaN channel layer to be subject to less interface roughness scattering and less alloy scattering, and thus provide a higher mobility than without the AlGaN layer.
A method of claim 38, wherein forming the GaN channel layer comprises for m ing the GaN material in a chamber at a temperature of approximately 1050 degrees Celsius (C); wherein forming the AlGaN layer comprises forming AlGaN in a chamber at a temperature of between 1000 and 1050 degrees C; and wherein forming the Al In N layer comprises forming Al InN material in a chamber at a temperature between 700 and 750 degrees C. 14/141,304 9 Docket No. 42P₆₁₀₇₄
Layer stacks claimed or described, ordered top of device to substrate.
GaN MOS-HEMT transistor with bi-layer capping stack
Materials described outside the worked examples.
GaN
AlGaN
AlxGa(1-x)N
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 6 is a schemat ic cros s section v iew of a portion o f a semi conduc t or substraie base after forming a Galli um Nitride (G aN) channel bas e d transistor h aving a G aN layer grown out of trenches or ga ps in the Silicon subst rate; a nd an InAI N and A IG aN b i-layer capping stack on …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Fet Sheet Resistance | 200–300 | GaN |
Fet Mobility | 900–1000 |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,660,064Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 5 is an example process for for ming Ga N channel based tr ansistor layers inclu ing an mInAIN and AIGaN bi-ayer capping st ack on a G aN lay er. 1 0010 1
Figure 6 is a schemat ic cros s section v iew of a portion o f a semi conduc t or substraie base after forming a Galli um Nitride (G aN) channel bas e d transistor h aving a G aN layer grown out of trenches or ga ps in the Silicon subst rate; a nd an InAI N and A IG aN b i-layer capping stack on …
Figure 7 is a schematic cross section view of a portion of a semiconductor substrate base after forming a Gallium Nitride (G aN) channel based fin transistor having a G aN fin layer grown on a Silicon fin; and an In AIN and A I GaN bi -L ayer fin Capping Stack on a GaN f in layer. [0012 1
Figure 8 is a 3-dimensional (3D) cross section along the f in 790 of a portion of a semiconductor substrate base after forming a Gallium Nitride (GaN) channel based fin transistor from layer having a GaN fin layer grown on a Silicon fin; and an InAI N and AlGaN b i -Layer f in Capping Stack on the GaN …
Figure 9 illustrates a computing device, such as a system on a chip (SoC), in accordance with one implementation. only to th e parts shown, which a re meant merel fo th e purpose of illustratio n. A lso, while SVG 14141304.12-26-2013.HPOP₈VO₄PXXIFW3.SPEC.8.svg 1.9 6.27 Black and white SVG …
Figure 2). [0016 1 According to some embodiments, a 2-dimensional e lectron gas (2DEG) channel can be created in G aN layer of GaN transistors by capping the G aN l ayer with a single capping layer. The difference in spontaneous polarization and piezoelectric polarization due to strain in the …
Figure 1). Such transistor layers may be layers of material that are included in or part of a transistor. Such a transistor may be a GaN MOS-high electron mobility transistor (HEM T). T he transistor may be a flat, thin, or t ri-gate transistor; and top surface of the substrate may be single crystal …
Figure 3 and 6-8). I n so me cases, layers 100 may be part of or used to form a flat, thin, t ri- gate, or a G aN M OS-higth electron mobility transistor (HEMT). The transistor may be part of a volta g e r egul ator, a power management inte gra ted circuit (IC), a radio frequency (RL F) po w er …
Figure 4 sho w s plotted point 44 2 as the plot of c harge density 410 for an embodiment wit hout la y er 130 (e.g., w ithout an AIGaN laye r); a nd plo tte d point 444 as a plot of the mobility for that embodiment. Plot 400 shows plotted point 452 as the plot of charge density 410 for an …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method to form transistor layers comprising: forming a GaN channel layer efcom prising (1) GaN material on a top surface of a substrate _, wherein the GaN channel layer comprises a GaN stack having a plurality of GaN layers separated by channel AlN layers, and wherein the (2) a capping AIN layer that has a thickness of between 0.6 and 1.5 nanometers on the GaN material, wherein the GaN channel layer includes islands of GaN material formed between islands that consist of oxide material only that are completely buried under a thickness of the GaN material; for m ing a bi-layer capping stack on a top surface of the GaN channel layer, wherein forming the bi-layer capping stack includes: forming a lower capping AIGaN l ayer of AlGaN material on a top surface of a capping A I N layer comprising A I N material and excluding Indium for m ed on the top surface of the GaN channel layer; and forming an upper capping A l InN layer of AlInN material on a top surface of the Al GaN material, wherein the AlGaN layer comprises AlxGa 1 x) N, where X is less than 0.4; and wherein the A I InN layer is A lyIn(l y)N, where Y is greater than 0.8, wherein a top surface of the AIGaN material forms a setback material surface upon which the A l InN material may be selectively etched, wherein the A l GaN layer has a thickness of between 2 and 10 nm, and causes an electron density of greater than 2.5 E₁₃ cm/2; and wherein the Al I nN layer has a thickness of between 5 and 15 nm, and causes a channel mobility of between 900 and 1000 CM₂/V-s, wherein the bi-layer capping stack causes a sheet resistance of between 200 and 300 ohms per SQR in a 2DEG channel formed in a upper thickness of the GaN layer, and wherein the transistor layers are part of one of a voltage regulator, a power management integrated circuit (IC), a radio frequency (RF) power amplifier, or a system on a chip (SoC).
The method of claim 1, further comprising: forming a gate over a top surface of the AlGaN layer; and forming junction regions on the A I InN layer on either side of the gate.
The method of claim 1, wherein the AlGaN material is formed on and touching a top surface of AIN material of the capping A l N layer, wherein the A l N material excludes A l InN, and wherein the A I InN material is formed on and touching a top surface of the AI GaN material.
The method of claim 1, wherein the GaN channel layer includes islands of GaN material formed between islands of oxide material; and wherein the islands of GaN material have a width or diameter of between 50 and 250 n m, and have a thickness of between 50 and 250 nm.
The method of claim 1, wherein the top surface of the substrate includes a plurality of substrate fins having three sides of substrate material; wherein the GaN channel layer is formed on the three sides of the substrate material; wherein the top surface of the GaN channel layer includes three sides of GaN material; and wherein the bi-layer capping stack is formed on the three sides of the GaN material.
A method of claim 1, wherein the AlGaN layer has a thickness of 2 or 5 nanometers, the Al I nN layer has a thickness of 7 nanometers, and the A I N layer has a thickness of 1 nanometer.
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canceled
/141,304 2 Docket No. 42P₆₁₀₇₄
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The transistor layers of claim 11, further comprising: a gate over a top surface of the AlGaN layer; and junction regions on the A l InN layer on either side of the gate.
The transistor layers of claim 16, wherein the gate comprises: a gate dielectric over all of an exposed surface of the A l GaN material in a trench; and a metal gate electrode on the gate dielectric in the trench.
The transistor layers of claim 11, wherein the AlGaN layer has a predetermined thickness configured to cause electrons in a 2DEG cha nn el of the GaN material of the GaN channel layer to be subject to less interface roughness scattering and less alloy scattering, and thus provide a higher mobility than without the AlGaN layer.
canceled
A system for computing comprising: a microprocessor coupled to a memory, the microprocessor having at least one electronic transistor having transistor layers comprising: a GaN channel layer efcomprising (1) GaN material on a top surface of a substrate _, wherein the GaN channel layer comprises a GaN stack having a plurality of GaN layers separated by channel AIN layers, and wherein the(2) a capping A I N layer that has a thickness of between 0.6 and 1.5 nanometers on the GaN material, wherein the GaN channel layer includes islands of GaN material formed between islands that consist of oxide material only that are completely buried under a thickness of the GaN material; a bi-layer capping stack on a top surface of the GaN channel layer, wherein the bi- layer capping stack includes: a lower capping AlGaN layer of A l GaN material on a top surface of a capping A l N layer comprising A l N material and excluding Indium on the top surface of the GaN channel layer; and an upper capping A l InN layer of A l InN material on a top surface of the Al GaN material, wherein the AlGaN layer comprises A l xGa (v x)N, where X is less than 0.4; and wherein the A l InN layer is Aly In(t 1y) N, where Y is greater than 0.8, wherein a top surface of the AI GaN material forms a setback material surface upon which the A I InN material may be selectively etched, wherein the A l GaN layer has a thickness of between 2 and 10 nm, and causes an electron density of greater than 2.5 E₁₃ c m/2; and wherein the A I InN layer has a thickness of between 5 and 15 n m, and causes a channel mobility of between 900 and 1400 CM₂/V-s, wherein the bi-layer capping stack causes a sheet resistance of between 200 and 300 ohms per SQR in a 2DEG channel formed in a upper thickness of the GaN layer, and wherein the transistor is part of one of a voltage regulator, a power management integrated circuit (IC), a radio frequency (RF) power amplifier, or a system on a chip (SoC).
The system of claim 20, further comprising: a gate over a top surface of the AlGaN layer, wherein the gate comprises: a gate dielectric over all of an exposed surface of the AlGaN material in a trench; and a metal gate electrode on the gate dielectric in the trench; and junction regions on the A I InN layer on either side of the gate.
The system of claim 20, wherein the A l GaN material is formed on and touching a top surface of A l N material of the capping A l N layer, wherein the A lN material excludes A IIn N, and wherein the A l InN material is formed on and touching a top surface of the AlGaN material.
The system of claim 20, wherein the GaN channel layer includes islands of GaN material formed between islands of oxide material; and wherein the islands of GaN material have a width or diameter of between 50 and 250 nm, and have a thickness of between 50 and 250 nm.
The system of claim 20, wherein the top surface of the substrate includes a plurality of substrate f in s having three sides of substrate material; wherein the GaN cha nn el layer is f o rmed on the three sides of the substrate material; wherein the top surface of the GaN channel layer includes three sides of GaN material; and wherein the b i-la y er capping stack is formed on the three sides of the GaN material.
The system of claim 20, wherein the A l GaN layer has a thickness of 2 or 5 nanometers, the A l InN layer has a thickness of 7 nanometers, and the A lN layer has a thickness of 1 n anometer.
21-22. 14/141,30 4 5 Docket No. 42P₆₁₀₇₄ canceled
canceled
canceled
The transistor of claim 11, wherein the AlGaN material is formed on and touching a top surface of A l N material of the capping A l N layer, wherein the A IN material excludes A lI nN, and wherein the A l InN material is formed on and touching a top surface of the AlGaN material.
canceled
The transistor of claim 11, wherein the GaN channel layer includes islands of GaN material formed between islands of oxide material; and wherein the islands of GaN material have a width or diameter of between 50 and 250 n m, and have a thickness of between 50 and 250 nm.
The transistor of claim 11, wherein the top surface of the substrate includes a plurality of substrate fins having three sides of substrate material; wherein the GaN channel layer is formed on the three sides of the substrate material; wherein the top surface of the GaN channel layer includes three sides of GaN material; and wherein the bi-layer capping stack is formed on the three sides of the GaN material.
The transistor of claim 11, wherein the A I GaN layer has a thickness of 2 or 5 nanometers, the A I InN layer has a thickness of 7 nanometers, and the A IN layer has a thickness of 1 nanometer.
A method to form transistor layers comprising: forming a GaN channel layer efcomprising (1) G aN material on a top surface of a substrate and (2) a capping AiN layer that has a thickness of between 0.6 and 1.5 nanometers on the GaN material, wherein the GaN channel layer includes islands of GaN material formed between islands that consist of oxide material only that are completely buried under a thickness of the GaN material; forming a bi-layer capping stack on a top surface of the G aN chann el layer, wherein forming the bi-layer capping stack includes: forming a lower capping AlGaN layer of A l GaN material on a top surface of a capping A I N layer comprising AIN material and excluding Indium formed on the top surface of the GaN channel layer; forming an upper capping A I InN layer of A l InN material on a top surface of the AI GaN material, wherein the AlGaN layer has a thickness of between 2 and 10 nm, and causes an electron density of greater than 2.5 E₁₃ cm/2; and wherein the A l InN layer has a thickness of between 5 and 15 n m, and causes a channel mobility of between 900 and 1000 CM₂/V-s, wherein the bi-layer capping stack causes a sheet resistance of between 200 and 300 ohms per SQR in a 2DEG channel formed in a upper thickness of the GaN layer, and wherein the transistor layers are part of one of a voltage regulator, a power management integrated circuit (IC), a radio frequency (RF) power amplifier, or a system on a chip (SoC); selectively etching the A lI nN material to expose a top surface of the AlGaN material, wherein selectively etching the A l InN material comprises using a wet etch including a solution to selectively etch the AlInN material but not etch the AlGaN material; 14/141,304 8 Docket No. 42P₆₁₀₇₄ forming a gate dielectric over all of the exposed surface of the A I GaN material; and forming a metal gate electrode on the gate dielectric.
A method of claim 38, wherein the AlGaN layer has a predetermined thickness configured to cause electrons in a 2DEG channel of the GaN material of the GaN channel layer to be subject to less interface roughness scattering and less alloy scattering, and thus provide a higher mobility than without the AlGaN layer.
A method of claim 38, wherein forming the GaN channel layer comprises for m ing the GaN material in a chamber at a temperature of approximately 1050 degrees Celsius (C); wherein forming the AlGaN layer comprises forming AlGaN in a chamber at a temperature of between 1000 and 1050 degrees C; and wherein forming the Al In N layer comprises forming Al InN material in a chamber at a temperature between 700 and 750 degrees C. 14/141,304 9 Docket No. 42P₆₁₀₇₄
Layer stacks claimed or described, ordered top of device to substrate.
GaN MOS-HEMT transistor with bi-layer capping stack
Materials described outside the worked examples.
GaN
AlGaN
AlxGa(1-x)N
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 6 is a schemat ic cros s section v iew of a portion o f a semi conduc t or substraie base after forming a Galli um Nitride (G aN) channel bas e d transistor h aving a G aN layer grown out of trenches or ga ps in the Silicon subst rate; a nd an InAI N and A IG aN b i-layer capping stack on …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Fet Sheet Resistance | 200–300 | GaN |
Fet Mobility | 900–1000 |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,660,064Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 5 is an example process for for ming Ga N channel based tr ansistor layers inclu ing an mInAIN and AIGaN bi-ayer capping st ack on a G aN lay er. 1 0010 1
Figure 6 is a schemat ic cros s section v iew of a portion o f a semi conduc t or substraie base after forming a Galli um Nitride (G aN) channel bas e d transistor h aving a G aN layer grown out of trenches or ga ps in the Silicon subst rate; a nd an InAI N and A IG aN b i-layer capping stack on …
Figure 7 is a schematic cross section view of a portion of a semiconductor substrate base after forming a Gallium Nitride (G aN) channel based fin transistor having a G aN fin layer grown on a Silicon fin; and an In AIN and A I GaN bi -L ayer fin Capping Stack on a GaN f in layer. [0012 1
Figure 8 is a 3-dimensional (3D) cross section along the f in 790 of a portion of a semiconductor substrate base after forming a Gallium Nitride (GaN) channel based fin transistor from layer having a GaN fin layer grown on a Silicon fin; and an InAI N and AlGaN b i -Layer f in Capping Stack on the GaN …
Figure 9 illustrates a computing device, such as a system on a chip (SoC), in accordance with one implementation. only to th e parts shown, which a re meant merel fo th e purpose of illustratio n. A lso, while SVG 14141304.12-26-2013.HPOP₈VO₄PXXIFW3.SPEC.8.svg 1.9 6.27 Black and white SVG …
Figure 2). [0016 1 According to some embodiments, a 2-dimensional e lectron gas (2DEG) channel can be created in G aN layer of GaN transistors by capping the G aN l ayer with a single capping layer. The difference in spontaneous polarization and piezoelectric polarization due to strain in the …
Figure 1). Such transistor layers may be layers of material that are included in or part of a transistor. Such a transistor may be a GaN MOS-high electron mobility transistor (HEM T). T he transistor may be a flat, thin, or t ri-gate transistor; and top surface of the substrate may be single crystal …
Figure 3 and 6-8). I n so me cases, layers 100 may be part of or used to form a flat, thin, t ri- gate, or a G aN M OS-higth electron mobility transistor (HEMT). The transistor may be part of a volta g e r egul ator, a power management inte gra ted circuit (IC), a radio frequency (RL F) po w er …
Figure 4 sho w s plotted point 44 2 as the plot of c harge density 410 for an embodiment wit hout la y er 130 (e.g., w ithout an AIGaN laye r); a nd plo tte d point 444 as a plot of the mobility for that embodiment. Plot 400 shows plotted point 452 as the plot of charge density 410 for an …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method to form transistor layers comprising: forming a GaN channel layer efcom prising (1) GaN material on a top surface of a substrate _, wherein the GaN channel layer comprises a GaN stack having a plurality of GaN layers separated by channel AlN layers, and wherein the (2) a capping AIN layer that has a thickness of between 0.6 and 1.5 nanometers on the GaN material, wherein the GaN channel layer includes islands of GaN material formed between islands that consist of oxide material only that are completely buried under a thickness of the GaN material; for m ing a bi-layer capping stack on a top surface of the GaN channel layer, wherein forming the bi-layer capping stack includes: forming a lower capping AIGaN l ayer of AlGaN material on a top surface of a capping A I N layer comprising A I N material and excluding Indium for m ed on the top surface of the GaN channel layer; and forming an upper capping A l InN layer of AlInN material on a top surface of the Al GaN material, wherein the AlGaN layer comprises AlxGa 1 x) N, where X is less than 0.4; and wherein the A I InN layer is A lyIn(l y)N, where Y is greater than 0.8, wherein a top surface of the AIGaN material forms a setback material surface upon which the A l InN material may be selectively etched, wherein the A l GaN layer has a thickness of between 2 and 10 nm, and causes an electron density of greater than 2.5 E₁₃ cm/2; and wherein the Al I nN layer has a thickness of between 5 and 15 nm, and causes a channel mobility of between 900 and 1000 CM₂/V-s, wherein the bi-layer capping stack causes a sheet resistance of between 200 and 300 ohms per SQR in a 2DEG channel formed in a upper thickness of the GaN layer, and wherein the transistor layers are part of one of a voltage regulator, a power management integrated circuit (IC), a radio frequency (RF) power amplifier, or a system on a chip (SoC).
The method of claim 1, further comprising: forming a gate over a top surface of the AlGaN layer; and forming junction regions on the A I InN layer on either side of the gate.
The method of claim 1, wherein the AlGaN material is formed on and touching a top surface of AIN material of the capping A l N layer, wherein the A l N material excludes A l InN, and wherein the A I InN material is formed on and touching a top surface of the AI GaN material.
The method of claim 1, wherein the GaN channel layer includes islands of GaN material formed between islands of oxide material; and wherein the islands of GaN material have a width or diameter of between 50 and 250 n m, and have a thickness of between 50 and 250 nm.
The method of claim 1, wherein the top surface of the substrate includes a plurality of substrate fins having three sides of substrate material; wherein the GaN channel layer is formed on the three sides of the substrate material; wherein the top surface of the GaN channel layer includes three sides of GaN material; and wherein the bi-layer capping stack is formed on the three sides of the GaN material.
A method of claim 1, wherein the AlGaN layer has a thickness of 2 or 5 nanometers, the Al I nN layer has a thickness of 7 nanometers, and the A I N layer has a thickness of 1 nanometer.
2-5. canceled
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canceled
/141,304 2 Docket No. 42P₆₁₀₇₄
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The transistor layers of claim 11, further comprising: a gate over a top surface of the AlGaN layer; and junction regions on the A l InN layer on either side of the gate.
The transistor layers of claim 16, wherein the gate comprises: a gate dielectric over all of an exposed surface of the A l GaN material in a trench; and a metal gate electrode on the gate dielectric in the trench.
The transistor layers of claim 11, wherein the AlGaN layer has a predetermined thickness configured to cause electrons in a 2DEG cha nn el of the GaN material of the GaN channel layer to be subject to less interface roughness scattering and less alloy scattering, and thus provide a higher mobility than without the AlGaN layer.
canceled
A system for computing comprising: a microprocessor coupled to a memory, the microprocessor having at least one electronic transistor having transistor layers comprising: a GaN channel layer efcomprising (1) GaN material on a top surface of a substrate _, wherein the GaN channel layer comprises a GaN stack having a plurality of GaN layers separated by channel AIN layers, and wherein the(2) a capping A I N layer that has a thickness of between 0.6 and 1.5 nanometers on the GaN material, wherein the GaN channel layer includes islands of GaN material formed between islands that consist of oxide material only that are completely buried under a thickness of the GaN material; a bi-layer capping stack on a top surface of the GaN channel layer, wherein the bi- layer capping stack includes: a lower capping AlGaN layer of A l GaN material on a top surface of a capping A l N layer comprising A l N material and excluding Indium on the top surface of the GaN channel layer; and an upper capping A l InN layer of A l InN material on a top surface of the Al GaN material, wherein the AlGaN layer comprises A l xGa (v x)N, where X is less than 0.4; and wherein the A l InN layer is Aly In(t 1y) N, where Y is greater than 0.8, wherein a top surface of the AI GaN material forms a setback material surface upon which the A I InN material may be selectively etched, wherein the A l GaN layer has a thickness of between 2 and 10 nm, and causes an electron density of greater than 2.5 E₁₃ c m/2; and wherein the A I InN layer has a thickness of between 5 and 15 n m, and causes a channel mobility of between 900 and 1400 CM₂/V-s, wherein the bi-layer capping stack causes a sheet resistance of between 200 and 300 ohms per SQR in a 2DEG channel formed in a upper thickness of the GaN layer, and wherein the transistor is part of one of a voltage regulator, a power management integrated circuit (IC), a radio frequency (RF) power amplifier, or a system on a chip (SoC).
The system of claim 20, further comprising: a gate over a top surface of the AlGaN layer, wherein the gate comprises: a gate dielectric over all of an exposed surface of the AlGaN material in a trench; and a metal gate electrode on the gate dielectric in the trench; and junction regions on the A I InN layer on either side of the gate.
The system of claim 20, wherein the A l GaN material is formed on and touching a top surface of A l N material of the capping A l N layer, wherein the A lN material excludes A IIn N, and wherein the A l InN material is formed on and touching a top surface of the AlGaN material.
The system of claim 20, wherein the GaN channel layer includes islands of GaN material formed between islands of oxide material; and wherein the islands of GaN material have a width or diameter of between 50 and 250 nm, and have a thickness of between 50 and 250 nm.
The system of claim 20, wherein the top surface of the substrate includes a plurality of substrate f in s having three sides of substrate material; wherein the GaN cha nn el layer is f o rmed on the three sides of the substrate material; wherein the top surface of the GaN channel layer includes three sides of GaN material; and wherein the b i-la y er capping stack is formed on the three sides of the GaN material.
The system of claim 20, wherein the A l GaN layer has a thickness of 2 or 5 nanometers, the A l InN layer has a thickness of 7 nanometers, and the A lN layer has a thickness of 1 n anometer.
21-22. 14/141,30 4 5 Docket No. 42P₆₁₀₇₄ canceled
canceled
canceled
The transistor of claim 11, wherein the AlGaN material is formed on and touching a top surface of A l N material of the capping A l N layer, wherein the A IN material excludes A lI nN, and wherein the A l InN material is formed on and touching a top surface of the AlGaN material.
canceled
The transistor of claim 11, wherein the GaN channel layer includes islands of GaN material formed between islands of oxide material; and wherein the islands of GaN material have a width or diameter of between 50 and 250 n m, and have a thickness of between 50 and 250 nm.
The transistor of claim 11, wherein the top surface of the substrate includes a plurality of substrate fins having three sides of substrate material; wherein the GaN channel layer is formed on the three sides of the substrate material; wherein the top surface of the GaN channel layer includes three sides of GaN material; and wherein the bi-layer capping stack is formed on the three sides of the GaN material.
The transistor of claim 11, wherein the A I GaN layer has a thickness of 2 or 5 nanometers, the A I InN layer has a thickness of 7 nanometers, and the A IN layer has a thickness of 1 nanometer.
A method to form transistor layers comprising: forming a GaN channel layer efcomprising (1) G aN material on a top surface of a substrate and (2) a capping AiN layer that has a thickness of between 0.6 and 1.5 nanometers on the GaN material, wherein the GaN channel layer includes islands of GaN material formed between islands that consist of oxide material only that are completely buried under a thickness of the GaN material; forming a bi-layer capping stack on a top surface of the G aN chann el layer, wherein forming the bi-layer capping stack includes: forming a lower capping AlGaN layer of A l GaN material on a top surface of a capping A I N layer comprising AIN material and excluding Indium formed on the top surface of the GaN channel layer; forming an upper capping A I InN layer of A l InN material on a top surface of the AI GaN material, wherein the AlGaN layer has a thickness of between 2 and 10 nm, and causes an electron density of greater than 2.5 E₁₃ cm/2; and wherein the A l InN layer has a thickness of between 5 and 15 n m, and causes a channel mobility of between 900 and 1000 CM₂/V-s, wherein the bi-layer capping stack causes a sheet resistance of between 200 and 300 ohms per SQR in a 2DEG channel formed in a upper thickness of the GaN layer, and wherein the transistor layers are part of one of a voltage regulator, a power management integrated circuit (IC), a radio frequency (RF) power amplifier, or a system on a chip (SoC); selectively etching the A lI nN material to expose a top surface of the AlGaN material, wherein selectively etching the A l InN material comprises using a wet etch including a solution to selectively etch the AlInN material but not etch the AlGaN material; 14/141,304 8 Docket No. 42P₆₁₀₇₄ forming a gate dielectric over all of the exposed surface of the A I GaN material; and forming a metal gate electrode on the gate dielectric.
A method of claim 38, wherein the AlGaN layer has a predetermined thickness configured to cause electrons in a 2DEG channel of the GaN material of the GaN channel layer to be subject to less interface roughness scattering and less alloy scattering, and thus provide a higher mobility than without the AlGaN layer.
A method of claim 38, wherein forming the GaN channel layer comprises for m ing the GaN material in a chamber at a temperature of approximately 1050 degrees Celsius (C); wherein forming the AlGaN layer comprises forming AlGaN in a chamber at a temperature of between 1000 and 1050 degrees C; and wherein forming the Al In N layer comprises forming Al InN material in a chamber at a temperature between 700 and 750 degrees C. 14/141,304 9 Docket No. 42P₆₁₀₇₄
Layer stacks claimed or described, ordered top of device to substrate.
GaN MOS-HEMT transistor with bi-layer capping stack
Materials described outside the worked examples.
GaN
AlGaN
AlxGa(1-x)N
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 6 is a schemat ic cros s section v iew of a portion o f a semi conduc t or substraie base after forming a Galli um Nitride (G aN) channel bas e d transistor h aving a G aN layer grown out of trenches or ga ps in the Silicon subst rate; a nd an InAI N and A IG aN b i-layer capping stack on …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Fet Sheet Resistance | 200–300 | GaN |
Fet Mobility | 900–1000 |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,660,064Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 5 is an example process for for ming Ga N channel based tr ansistor layers inclu ing an mInAIN and AIGaN bi-ayer capping st ack on a G aN lay er. 1 0010 1
Figure 6 is a schemat ic cros s section v iew of a portion o f a semi conduc t or substraie base after forming a Galli um Nitride (G aN) channel bas e d transistor h aving a G aN layer grown out of trenches or ga ps in the Silicon subst rate; a nd an InAI N and A IG aN b i-layer capping stack on …
Figure 7 is a schematic cross section view of a portion of a semiconductor substrate base after forming a Gallium Nitride (G aN) channel based fin transistor having a G aN fin layer grown on a Silicon fin; and an In AIN and A I GaN bi -L ayer fin Capping Stack on a GaN f in layer. [0012 1
Figure 8 is a 3-dimensional (3D) cross section along the f in 790 of a portion of a semiconductor substrate base after forming a Gallium Nitride (GaN) channel based fin transistor from layer having a GaN fin layer grown on a Silicon fin; and an InAI N and AlGaN b i -Layer f in Capping Stack on the GaN …
Figure 9 illustrates a computing device, such as a system on a chip (SoC), in accordance with one implementation. only to th e parts shown, which a re meant merel fo th e purpose of illustratio n. A lso, while SVG 14141304.12-26-2013.HPOP₈VO₄PXXIFW3.SPEC.8.svg 1.9 6.27 Black and white SVG …
Figure 2). [0016 1 According to some embodiments, a 2-dimensional e lectron gas (2DEG) channel can be created in G aN layer of GaN transistors by capping the G aN l ayer with a single capping layer. The difference in spontaneous polarization and piezoelectric polarization due to strain in the …
Figure 1). Such transistor layers may be layers of material that are included in or part of a transistor. Such a transistor may be a GaN MOS-high electron mobility transistor (HEM T). T he transistor may be a flat, thin, or t ri-gate transistor; and top surface of the substrate may be single crystal …
Figure 3 and 6-8). I n so me cases, layers 100 may be part of or used to form a flat, thin, t ri- gate, or a G aN M OS-higth electron mobility transistor (HEMT). The transistor may be part of a volta g e r egul ator, a power management inte gra ted circuit (IC), a radio frequency (RL F) po w er …
Figure 4 sho w s plotted point 44 2 as the plot of c harge density 410 for an embodiment wit hout la y er 130 (e.g., w ithout an AIGaN laye r); a nd plo tte d point 444 as a plot of the mobility for that embodiment. Plot 400 shows plotted point 452 as the plot of charge density 410 for an …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method to form transistor layers comprising: forming a GaN channel layer efcom prising (1) GaN material on a top surface of a substrate _, wherein the GaN channel layer comprises a GaN stack having a plurality of GaN layers separated by channel AlN layers, and wherein the (2) a capping AIN layer that has a thickness of between 0.6 and 1.5 nanometers on the GaN material, wherein the GaN channel layer includes islands of GaN material formed between islands that consist of oxide material only that are completely buried under a thickness of the GaN material; for m ing a bi-layer capping stack on a top surface of the GaN channel layer, wherein forming the bi-layer capping stack includes: forming a lower capping AIGaN l ayer of AlGaN material on a top surface of a capping A I N layer comprising A I N material and excluding Indium for m ed on the top surface of the GaN channel layer; and forming an upper capping A l InN layer of AlInN material on a top surface of the Al GaN material, wherein the AlGaN layer comprises AlxGa 1 x) N, where X is less than 0.4; and wherein the A I InN layer is A lyIn(l y)N, where Y is greater than 0.8, wherein a top surface of the AIGaN material forms a setback material surface upon which the A l InN material may be selectively etched, wherein the A l GaN layer has a thickness of between 2 and 10 nm, and causes an electron density of greater than 2.5 E₁₃ cm/2; and wherein the Al I nN layer has a thickness of between 5 and 15 nm, and causes a channel mobility of between 900 and 1000 CM₂/V-s, wherein the bi-layer capping stack causes a sheet resistance of between 200 and 300 ohms per SQR in a 2DEG channel formed in a upper thickness of the GaN layer, and wherein the transistor layers are part of one of a voltage regulator, a power management integrated circuit (IC), a radio frequency (RF) power amplifier, or a system on a chip (SoC).
The method of claim 1, further comprising: forming a gate over a top surface of the AlGaN layer; and forming junction regions on the A I InN layer on either side of the gate.
The method of claim 1, wherein the AlGaN material is formed on and touching a top surface of AIN material of the capping A l N layer, wherein the A l N material excludes A l InN, and wherein the A I InN material is formed on and touching a top surface of the AI GaN material.
The method of claim 1, wherein the GaN channel layer includes islands of GaN material formed between islands of oxide material; and wherein the islands of GaN material have a width or diameter of between 50 and 250 n m, and have a thickness of between 50 and 250 nm.
The method of claim 1, wherein the top surface of the substrate includes a plurality of substrate fins having three sides of substrate material; wherein the GaN channel layer is formed on the three sides of the substrate material; wherein the top surface of the GaN channel layer includes three sides of GaN material; and wherein the bi-layer capping stack is formed on the three sides of the GaN material.
A method of claim 1, wherein the AlGaN layer has a thickness of 2 or 5 nanometers, the Al I nN layer has a thickness of 7 nanometers, and the A I N layer has a thickness of 1 nanometer.
2-5. canceled
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canceled
canceled
/141,304 2 Docket No. 42P₆₁₀₇₄
canceled
The transistor layers of claim 11, further comprising: a gate over a top surface of the AlGaN layer; and junction regions on the A l InN layer on either side of the gate.
The transistor layers of claim 16, wherein the gate comprises: a gate dielectric over all of an exposed surface of the A l GaN material in a trench; and a metal gate electrode on the gate dielectric in the trench.
The transistor layers of claim 11, wherein the AlGaN layer has a predetermined thickness configured to cause electrons in a 2DEG cha nn el of the GaN material of the GaN channel layer to be subject to less interface roughness scattering and less alloy scattering, and thus provide a higher mobility than without the AlGaN layer.
canceled
A system for computing comprising: a microprocessor coupled to a memory, the microprocessor having at least one electronic transistor having transistor layers comprising: a GaN channel layer efcomprising (1) GaN material on a top surface of a substrate _, wherein the GaN channel layer comprises a GaN stack having a plurality of GaN layers separated by channel AIN layers, and wherein the(2) a capping A I N layer that has a thickness of between 0.6 and 1.5 nanometers on the GaN material, wherein the GaN channel layer includes islands of GaN material formed between islands that consist of oxide material only that are completely buried under a thickness of the GaN material; a bi-layer capping stack on a top surface of the GaN channel layer, wherein the bi- layer capping stack includes: a lower capping AlGaN layer of A l GaN material on a top surface of a capping A l N layer comprising A l N material and excluding Indium on the top surface of the GaN channel layer; and an upper capping A l InN layer of A l InN material on a top surface of the Al GaN material, wherein the AlGaN layer comprises A l xGa (v x)N, where X is less than 0.4; and wherein the A l InN layer is Aly In(t 1y) N, where Y is greater than 0.8, wherein a top surface of the AI GaN material forms a setback material surface upon which the A I InN material may be selectively etched, wherein the A l GaN layer has a thickness of between 2 and 10 nm, and causes an electron density of greater than 2.5 E₁₃ c m/2; and wherein the A I InN layer has a thickness of between 5 and 15 n m, and causes a channel mobility of between 900 and 1400 CM₂/V-s, wherein the bi-layer capping stack causes a sheet resistance of between 200 and 300 ohms per SQR in a 2DEG channel formed in a upper thickness of the GaN layer, and wherein the transistor is part of one of a voltage regulator, a power management integrated circuit (IC), a radio frequency (RF) power amplifier, or a system on a chip (SoC).
The system of claim 20, further comprising: a gate over a top surface of the AlGaN layer, wherein the gate comprises: a gate dielectric over all of an exposed surface of the AlGaN material in a trench; and a metal gate electrode on the gate dielectric in the trench; and junction regions on the A I InN layer on either side of the gate.
The system of claim 20, wherein the A l GaN material is formed on and touching a top surface of A l N material of the capping A l N layer, wherein the A lN material excludes A IIn N, and wherein the A l InN material is formed on and touching a top surface of the AlGaN material.
The system of claim 20, wherein the GaN channel layer includes islands of GaN material formed between islands of oxide material; and wherein the islands of GaN material have a width or diameter of between 50 and 250 nm, and have a thickness of between 50 and 250 nm.
The system of claim 20, wherein the top surface of the substrate includes a plurality of substrate f in s having three sides of substrate material; wherein the GaN cha nn el layer is f o rmed on the three sides of the substrate material; wherein the top surface of the GaN channel layer includes three sides of GaN material; and wherein the b i-la y er capping stack is formed on the three sides of the GaN material.
The system of claim 20, wherein the A l GaN layer has a thickness of 2 or 5 nanometers, the A l InN layer has a thickness of 7 nanometers, and the A lN layer has a thickness of 1 n anometer.
21-22. 14/141,30 4 5 Docket No. 42P₆₁₀₇₄ canceled
canceled
canceled
The transistor of claim 11, wherein the AlGaN material is formed on and touching a top surface of A l N material of the capping A l N layer, wherein the A IN material excludes A lI nN, and wherein the A l InN material is formed on and touching a top surface of the AlGaN material.
canceled
The transistor of claim 11, wherein the GaN channel layer includes islands of GaN material formed between islands of oxide material; and wherein the islands of GaN material have a width or diameter of between 50 and 250 n m, and have a thickness of between 50 and 250 nm.
The transistor of claim 11, wherein the top surface of the substrate includes a plurality of substrate fins having three sides of substrate material; wherein the GaN channel layer is formed on the three sides of the substrate material; wherein the top surface of the GaN channel layer includes three sides of GaN material; and wherein the bi-layer capping stack is formed on the three sides of the GaN material.
The transistor of claim 11, wherein the A I GaN layer has a thickness of 2 or 5 nanometers, the A I InN layer has a thickness of 7 nanometers, and the A IN layer has a thickness of 1 nanometer.
A method to form transistor layers comprising: forming a GaN channel layer efcomprising (1) G aN material on a top surface of a substrate and (2) a capping AiN layer that has a thickness of between 0.6 and 1.5 nanometers on the GaN material, wherein the GaN channel layer includes islands of GaN material formed between islands that consist of oxide material only that are completely buried under a thickness of the GaN material; forming a bi-layer capping stack on a top surface of the G aN chann el layer, wherein forming the bi-layer capping stack includes: forming a lower capping AlGaN layer of A l GaN material on a top surface of a capping A I N layer comprising AIN material and excluding Indium formed on the top surface of the GaN channel layer; forming an upper capping A I InN layer of A l InN material on a top surface of the AI GaN material, wherein the AlGaN layer has a thickness of between 2 and 10 nm, and causes an electron density of greater than 2.5 E₁₃ cm/2; and wherein the A l InN layer has a thickness of between 5 and 15 n m, and causes a channel mobility of between 900 and 1000 CM₂/V-s, wherein the bi-layer capping stack causes a sheet resistance of between 200 and 300 ohms per SQR in a 2DEG channel formed in a upper thickness of the GaN layer, and wherein the transistor layers are part of one of a voltage regulator, a power management integrated circuit (IC), a radio frequency (RF) power amplifier, or a system on a chip (SoC); selectively etching the A lI nN material to expose a top surface of the AlGaN material, wherein selectively etching the A l InN material comprises using a wet etch including a solution to selectively etch the AlInN material but not etch the AlGaN material; 14/141,304 8 Docket No. 42P₆₁₀₇₄ forming a gate dielectric over all of the exposed surface of the A I GaN material; and forming a metal gate electrode on the gate dielectric.
A method of claim 38, wherein the AlGaN layer has a predetermined thickness configured to cause electrons in a 2DEG channel of the GaN material of the GaN channel layer to be subject to less interface roughness scattering and less alloy scattering, and thus provide a higher mobility than without the AlGaN layer.
A method of claim 38, wherein forming the GaN channel layer comprises for m ing the GaN material in a chamber at a temperature of approximately 1050 degrees Celsius (C); wherein forming the AlGaN layer comprises forming AlGaN in a chamber at a temperature of between 1000 and 1050 degrees C; and wherein forming the Al In N layer comprises forming Al InN material in a chamber at a temperature between 700 and 750 degrees C. 14/141,304 9 Docket No. 42P₆₁₀₇₄
Layer stacks claimed or described, ordered top of device to substrate.
GaN MOS-HEMT transistor with bi-layer capping stack
Materials described outside the worked examples.
GaN
AlGaN
AlxGa(1-x)N
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 6 is a schemat ic cros s section v iew of a portion o f a semi conduc t or substraie base after forming a Galli um Nitride (G aN) channel bas e d transistor h aving a G aN layer grown out of trenches or ga ps in the Silicon subst rate; a nd an InAI N and A IG aN b i-layer capping stack on …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Fet Sheet Resistance | 200–300 | GaN |
Fet Mobility | 900–1000 |
Related documents with shared materials, methods, properties, or citations.
AlInN
AlyIn(1-y)N
AlN
oxide
oxide island material
Figure 7 is a schematic cross section view of a portion of a semiconductor substrate base after forming a Gallium Nitride (G aN) channel based fin transistor having a G aN fin layer grown on a Silicon fin; and an In AIN and A I GaN bi -L ayer fin Capping Stack on a GaN f in layer. [0012 1
Figure 8 is a 3-dimensional (3D) cross section along the f in 790 of a portion of a semiconductor substrate base after forming a Gallium Nitride (GaN) channel based fin transistor from layer having a GaN fin layer grown on a Silicon fin; and an InAI N and AlGaN b i -Layer f in Capping Stack on the GaN …
Figure 2). [0016 1 According to some embodiments, a 2-dimensional e lectron gas (2DEG) channel can be created in G aN layer of GaN transistors by capping the G aN l ayer with a single capping layer. The difference in spontaneous polarization and piezoelectric polarization due to strain in the …
Figure 1). Such transistor layers may be layers of material that are included in or part of a transistor. Such a transistor may be a GaN MOS-high electron mobility transistor (HEM T). T he transistor may be a flat, thin, or t ri-gate transistor; and top surface of the substrate may be single crystal …
Figure 3 and 6-8). I n so me cases, layers 100 may be part of or used to form a flat, thin, t ri- gate, or a G aN M OS-higth electron mobility transistor (HEMT). The transistor may be part of a volta g e r egul ator, a power management inte gra ted circuit (IC), a radio frequency (RL F) po w er …
Figure 4 sho w s plotted point 44 2 as the plot of c harge density 410 for an embodiment wit hout la y er 130 (e.g., w ithout an AIGaN laye r); a nd plo tte d point 444 as a plot of the mobility for that embodiment. Plot 400 shows plotted point 452 as the plot of charge density 410 for an …
2deg Electron Density | ≥ 25000000000000 | GaN |
Thickness | 0.6–1.5 nm | — |
Thickness | 2–10 nm | — |
Thickness | 5–15 nm | — |
Thickness | 900–1000 CM | — |
Thickness | 5–30 nm | — |
Thickness | 900–1400 CM | — |
Thickness | 50–250 nm | — |
AlInN
AlyIn(1-y)N
AlN
oxide
oxide island material
Figure 7 is a schematic cross section view of a portion of a semiconductor substrate base after forming a Gallium Nitride (G aN) channel based fin transistor having a G aN fin layer grown on a Silicon fin; and an In AIN and A I GaN bi -L ayer fin Capping Stack on a GaN f in layer. [0012 1
Figure 8 is a 3-dimensional (3D) cross section along the f in 790 of a portion of a semiconductor substrate base after forming a Gallium Nitride (GaN) channel based fin transistor from layer having a GaN fin layer grown on a Silicon fin; and an InAI N and AlGaN b i -Layer f in Capping Stack on the GaN …
Figure 2). [0016 1 According to some embodiments, a 2-dimensional e lectron gas (2DEG) channel can be created in G aN layer of GaN transistors by capping the G aN l ayer with a single capping layer. The difference in spontaneous polarization and piezoelectric polarization due to strain in the …
Figure 1). Such transistor layers may be layers of material that are included in or part of a transistor. Such a transistor may be a GaN MOS-high electron mobility transistor (HEM T). T he transistor may be a flat, thin, or t ri-gate transistor; and top surface of the substrate may be single crystal …
Figure 3 and 6-8). I n so me cases, layers 100 may be part of or used to form a flat, thin, t ri- gate, or a G aN M OS-higth electron mobility transistor (HEMT). The transistor may be part of a volta g e r egul ator, a power management inte gra ted circuit (IC), a radio frequency (RL F) po w er …
Figure 4 sho w s plotted point 44 2 as the plot of c harge density 410 for an embodiment wit hout la y er 130 (e.g., w ithout an AIGaN laye r); a nd plo tte d point 444 as a plot of the mobility for that embodiment. Plot 400 shows plotted point 452 as the plot of charge density 410 for an …
2deg Electron Density | ≥ 25000000000000 | GaN |
Thickness | 0.6–1.5 nm | — |
Thickness | 2–10 nm | — |
Thickness | 5–15 nm | — |
Thickness | 900–1000 CM | — |
Thickness | 5–30 nm | — |
Thickness | 900–1400 CM | — |
Thickness | 50–250 nm | — |
AlInN
AlyIn(1-y)N
AlN
oxide
oxide island material
Figure 7 is a schematic cross section view of a portion of a semiconductor substrate base after forming a Gallium Nitride (G aN) channel based fin transistor having a G aN fin layer grown on a Silicon fin; and an In AIN and A I GaN bi -L ayer fin Capping Stack on a GaN f in layer. [0012 1
Figure 8 is a 3-dimensional (3D) cross section along the f in 790 of a portion of a semiconductor substrate base after forming a Gallium Nitride (GaN) channel based fin transistor from layer having a GaN fin layer grown on a Silicon fin; and an InAI N and AlGaN b i -Layer f in Capping Stack on the GaN …
Figure 2). [0016 1 According to some embodiments, a 2-dimensional e lectron gas (2DEG) channel can be created in G aN layer of GaN transistors by capping the G aN l ayer with a single capping layer. The difference in spontaneous polarization and piezoelectric polarization due to strain in the …
Figure 1). Such transistor layers may be layers of material that are included in or part of a transistor. Such a transistor may be a GaN MOS-high electron mobility transistor (HEM T). T he transistor may be a flat, thin, or t ri-gate transistor; and top surface of the substrate may be single crystal …
Figure 3 and 6-8). I n so me cases, layers 100 may be part of or used to form a flat, thin, t ri- gate, or a G aN M OS-higth electron mobility transistor (HEMT). The transistor may be part of a volta g e r egul ator, a power management inte gra ted circuit (IC), a radio frequency (RL F) po w er …
Figure 4 sho w s plotted point 44 2 as the plot of c harge density 410 for an embodiment wit hout la y er 130 (e.g., w ithout an AIGaN laye r); a nd plo tte d point 444 as a plot of the mobility for that embodiment. Plot 400 shows plotted point 452 as the plot of charge density 410 for an …
2deg Electron Density | ≥ 25000000000000 | GaN |
Thickness | 0.6–1.5 nm | — |
Thickness | 2–10 nm | — |
Thickness | 5–15 nm | — |
Thickness | 900–1000 CM | — |
Thickness | 5–30 nm | — |
Thickness | 900–1400 CM | — |
Thickness | 50–250 nm | — |
AlInN
AlyIn(1-y)N
AlN
oxide
oxide island material
Figure 7 is a schematic cross section view of a portion of a semiconductor substrate base after forming a Gallium Nitride (G aN) channel based fin transistor having a G aN fin layer grown on a Silicon fin; and an In AIN and A I GaN bi -L ayer fin Capping Stack on a GaN f in layer. [0012 1
Figure 8 is a 3-dimensional (3D) cross section along the f in 790 of a portion of a semiconductor substrate base after forming a Gallium Nitride (GaN) channel based fin transistor from layer having a GaN fin layer grown on a Silicon fin; and an InAI N and AlGaN b i -Layer f in Capping Stack on the GaN …
Figure 2). [0016 1 According to some embodiments, a 2-dimensional e lectron gas (2DEG) channel can be created in G aN layer of GaN transistors by capping the G aN l ayer with a single capping layer. The difference in spontaneous polarization and piezoelectric polarization due to strain in the …
Figure 1). Such transistor layers may be layers of material that are included in or part of a transistor. Such a transistor may be a GaN MOS-high electron mobility transistor (HEM T). T he transistor may be a flat, thin, or t ri-gate transistor; and top surface of the substrate may be single crystal …
Figure 3 and 6-8). I n so me cases, layers 100 may be part of or used to form a flat, thin, t ri- gate, or a G aN M OS-higth electron mobility transistor (HEMT). The transistor may be part of a volta g e r egul ator, a power management inte gra ted circuit (IC), a radio frequency (RL F) po w er …
Figure 4 sho w s plotted point 44 2 as the plot of c harge density 410 for an embodiment wit hout la y er 130 (e.g., w ithout an AIGaN laye r); a nd plo tte d point 444 as a plot of the mobility for that embodiment. Plot 400 shows plotted point 452 as the plot of charge density 410 for an …
2deg Electron Density | ≥ 25000000000000 | GaN |
Thickness | 0.6–1.5 nm | — |
Thickness | 2–10 nm | — |
Thickness | 5–15 nm | — |
Thickness | 900–1000 CM | — |
Thickness | 5–30 nm | — |
Thickness | 900–1400 CM | — |
Thickness | 50–250 nm | — |