Patent
US 9,064,842SEMICONDUCTOR DEVICE INCLUDING GRAPHENE LAYER AND METHOD OF MAKING THE SEMICONDUCTOR DEVICE
Ageeth Anke Bol
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 9,064,842Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 illustrates a related art graphene device (e.g., a graphene transistor and, more 1 0 particularly, a graphene field effect transistor (FET)) 110;
Figure 2 illustrates a semiconductor device 200 according to an exemplary aspect of the present invention;
Figure 3 illustrates a method 300 of forming a semiconductor device, according to an exemplary aspect of the present invention; 1 5
Figure 4A illustrates forming an oxide layer 410a in the method 400 of making a semiconductor device, according to an exemplary aspect of the present invention;
Figure 4B illustrates forming a trench 415a in the method 400 of making a semiconductor device, according to an exemplary aspect of the present invention;
Figure 4C illustrates forming first plural contacts 420a, 420b in the method 400 of making 20 a semiconductor device, according to an exemplary aspect of the present invention;
Figure 4 D illustrates forming a graphene layer 430 in the method 400 of making a semiconductor device, according to an exemplary aspect of the present invention;
Figure 4E illustrates forming second plural contacts 440a, 440b in the method 400 of making a semiconductor device, according to an exemplary aspect of the present invention; 25
Figure 4F illustrates the device 450 made by the method 400 of making a semiconductor device, according to an exemplary aspect of the present invention;
Figure 5A illustrates the first plural contacts 520a, 520b in the device 500, according to an exemplary aspect of the present invention;
Figure 5B illustrates the graphene layer 530 in the device 500, according to an exemplary 30 aspect of the present invention;
Figure 5 C illustrates the second plural contacts 540a, 540b in the device 500, according to 4 YO R₉₂₀₁₁₀₅₅₈US 1 an exemplary aspect of the present invention;
Figure 5D illustrates a interface between the oxide layer 5 10 b and a contact 520b of the first plural contacts 520a, 520b in the device 500, according to an exemplary aspect of the present invention; 5
Figure 5E illustrates a plan view of the device 500, according to an exemplary aspect of the present invention;
Figure 6A illustrates test results for a double-contacted device (e.g., device 200) including CVD-grown single-layer graphene, according to an exemplary aspect of the present invention;
Figure 6B illustrates test results for a double-contacted device (e.g., device 200) including 1 0 mechanically exfoliated bilayer graphene, according to an exemplary aspect of the present invention;
Figure 7A provides a graph illustrating a contact resistance distribution from a plurality of test sets including single-layer graphene devices tested by the inventors; and
Figure 7B illustrates an SEM image of a test set 750, with a device 750 according to an 1 5 exemplary aspect of the present invention (e.g., a double-contacted device) on the left side of the set 700, and the top-contacted device 760 on the right side of the set 700.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
(Cu rr ently amended) A semiconductor device, comprising: a semiconductor substrate; a dielectric layer formed in the semiconductor substrate; first plural contacts formed in the dielectric layer such that the dielectric layer comprises: a first portion which is formed between the first plural contacts; and a second portion which is formed between the semiconductor substrate and the first plural contacts substrate; a graphene layer formed on an upper surface of the first portion of the dielectric layer substrate and on an upper surface of the first plural contacts; and second plural contacts formed on the graphene layer such that the graphene layer is formed between the first plural contacts and the second plural contacts, wherein an area of contact of the first plural contacts is substantially the same as an area of contact of the second plural contacts, and the first plural contacts are substantially aligned with the second plural contacts to form a double-contact configuration, and wherein the upper surface of the first plural contacts is substantially co-planar with the upper surface of the first portion of the dielectric layer substrate, such that the graphene layer comprises an undistorted graphene layer.
(Cu rr ently amended) The semiconductor device of claim 1, wherein the dielectric layer substrate comprises plural trenches, and the first plural contacts are formed in the plural trenches, respectively.
The semiconductor device of claim 1, wherein the first plural contacts comprise a titanium layer, and a palladium layer formed on the titanium layer.
The semiconductor device of claim 1, wherein the graphene layer comprises one of a single-layer of graphene that was grown by chemical vapor deposition (CVD), and Docket No. YOR₉₂₀₁₁₀₅₅₈U S 1 3 Serial No. 13/425,302 YOR.867 bilayer graphene that was mechanically exfoliated from graphite flakes.
The semiconductor device of claim 1, wherein the second plural contacts comprise a titanium layer formed on the graphene layer, a palladium layer formed on the titanium layer, and a gold layer formed on the palladium layer.
The semiconductor device of claim 1, wherein an offset of a contact of the second plural contacts from a contact of the first plural contacts is not greater than 2 0 nm.
The semiconductor device of claim 1, wherein a contact resistance of the first plural contacts and the second plural contacts is less than 450 Q. m.
(Cu rr ently amended) The semiconductor device of claim 1, wherein the semiconductor substrate comprises a p+ Si substrate, and the dielectric layer comprises a layer of SiO 2 formed on the p+ Si substrate, and the first plural contacts are embedded in the layer of SiO 2.
(Cu rr ently amended) The semiconductor device of claim 1, wherein the dielectric layer substrate comprises an oxide layer and the first plural contacts are formed in the oxide layer, such that the upper surface of the first plural contacts is substantially co-planar with an upper surface of the oxide layer, and the graphene layer is formed on the upper surface of the first plural contacts and the upper surface of the oxide layer.
The semiconductor device of claim 1, wherein a width of the first plural contacts is substantially equal to a width of the second plural contacts, such that an innermost edge of the first plural contacts is aligned with an innermost edge of the second plural contacts, and an outermost edge of the first plural contacts is aligned with an outermost edge of the second plural contacts.
The semiconductor device of claim 1, wherein a thickness of the first plural contacts is in a range from 20 nm to 300 nm.
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(Cu rr ently amended) A semiconductor device, comprising: a semiconductor substrate; a dielectric layer comprising a pair of trenches; first source and drain contacts formed in the pair of trenches of the such that the dielectric layer comprises: a first portion which is formed between the first source and drain contacts; and a second portion which is formed between the semiconductor substrate and the first source and drain contacts substrate; Docket No. Y O R₉₂₀₁₁₀₅₅₈US₁ 4 Serial No. 13/425,302 YOR.867 a graphene layer formed on the first portion of the dielectric layer substrate and on the first source and drain contacts, an upper surface of the first source and drain contacts being substantially co-planar with an upper surface of the first portion of the dielectric layer substrate, and the graphene layer being formed on the upper surface of the first source and drain contacts and the upper surface of the first portion of the dielectric layer substrate, and a difference in height between the upper surface of the first source and drain contacts and a height of the upper surface of the first portion of the dielectric layer substrate being no greater than 5 nm, such that the graphene layer comprises an undistorted graphene layer; and second source and drain contacts formed on the graphene layer such that the graphene layer is formed between the first source and drain contacts and the second source and drain contacts, an area of the first source and drain contacts being substantially the same as an area of the second source and drain contacts, and the first source and drain contacts being substantially aligned with the second source and drain contacts to form a double-contact configuration.
(Cu rr ently amended) A graphene field effect transistor (FET), comprising: a back gate comprising a doped semiconductor substrate; a gate dielectric comprising a dielectric layer formed on the doped semiconductor substrate; first source and drain contacts embedded in the dielectric layer such that the dielectric layer comprises: a first portion which is formed between the first source and drain contacts; and a second portion which is formed between the doped semiconductor substrate and the first source and drain contacts; a channel layer comprising a graphene layer formed on a surface of the first portion of the gate dielectric layer and on a surface of the first source and drain contacts; and second source and drain contacts formed on the graphene layer such that the graphene layer is formed between the first source and drain contacts and the second source and drain contacts, wherein an area of contact of the first source and drain contacts is substantially the same as an area of contact of the second source and drain contacts, and the first source and drain contacts are substantially aligned with the second source and drain contacts to form a double- contact configuration, and Docket No. Y O R₉₂₀₁₁₀₅₅₈US₁ 5 Serial No. 13/425,302 YOR.867 wherein the surface of the first source and drain contacts is substantially co-planar with the surface of the first portion of the gate dielectric layer, such that the graphene layer comprises an undistorted graphene layer.
(Cu rr ently amended) A method of forming a semiconductor device, comprising: forming a dielectric layer in a semiconductor substrate; forming first plural contacts in the dielectric layer such that the dielectric layer comprises: a first portion which is formed between the first plural contacts; and a second portion which is formed between the semiconductor substrate and the first plural contacts a substrate; forming a graphene layer on an upper surface of the first portion of the dielectric layer substrate and on an upper surface of the first plural contacts; and forming second plural contacts on the graphene layer such that the graphene layer is formed between the first plural contacts and the second plural contacts, wherein an area of contact of the first plural contacts is substantially the same as an area of contact of the second plural contacts, and the first plural contacts are substantially aligned with the second plural contacts to form a double-contact configuration, and wherein the upper surface of the first plural contacts is substantially co-planar with the upper surface of the first portion of the dielectric layer substrate, such that the graphene layer comprises an undistorted graphene layer.
The method of claim 15, wherein the forming of the first plural contacts comp ri ses: etching the substrate to form a pair of trenches; forming a titanium layer in the pair of trenches; and forming a palladium layer formed on the titanium layer in the pair of trenches.
(Cu rr ently amended) The method of claim 15, wherein the forming of the graphene layer comprises one of: growing single-layer graphene by chemical vapor deposition (CVD) on a copper foil, transferring the grown single-layer graphene onto the first portion of the dielectric layer substrate Docket No. Y O R₉₂₀₁₁₀₅₅₈U S 1 6 Serial No. 13/425,302 YOR.867 and the first plural contacts, and patterning the single-layer graphene; and mechanically exfoliating bilayer graphene from graphite flakes.
The method of claim 15, wherein the forming of the second plural contacts comp ri ses: forming a titanium layer on the graphene layer; forming a palladium layer on the titanium layer; and forming a gold layer formed on the palladium layer.
The method of claim 15, wherein the forming of the second plural contacts comprises forming the second plural contacts such that an offset of a contact of the second plural contacts from a contact of the first plural contacts is not greater than 2 0 nm.
(Cu rr ently amended) The method of claim 15, wherein the semiconductor substrate comprises a p + Si substrate, and a layer of SiO 2 formed on the p + Si substrate, and the forming of the first source and drain contacts comprises embedding the first and second drain contacts in the layer of SiO 2.
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(Cu rr ently amended) A method of forming a semiconductor device, comprising: forming a dielectric layer in a semiconductor substrate; forming first source and drain contacts in the dielectric layer a substrate, such that: the dielectric layer comprises a first portion which is formed between the first Docket No. Y O R₉₂₀₁₁₀₅₅₈US₁ 7 Serial No. 13/425,302 YOR.867 source and drain contacts, and a second portion which is formed between the semiconductor substrate and the first source and drain contacts; and an upper surface of the first source and drain contacts is substantially co-planar with an upper surface of the first portion of the dielectric layer; substrate, and such that a difference in height between the upper surface of the first source and drain contacts and a height of the upper surface of the first portion of the dielectric layer substrate is no greater than 5 nm; forming a graphene layer on the upper surface of the first source and drain contacts and the upper surface of the first portion of the dielectric layer substrate such that the graphene layer comprises an undistorted graphene layer; and forming second source and drain contacts on the graphene layer such that the graphene layer is formed between the first source and drain contacts and the second source and drain contacts in a double-contact configuration, an area of the first source and drain contacts being substantially the same as an area of the second source and drain contacts, and the first source and drain contacts being substantially aligned with the second source and drain contacts.
Layer stacks claimed or described, ordered top of device to substrate.
double-contact semiconductor device with graphene layer
graphene field effect transistor (FET) with double-contact configuration
Materials described outside the worked examples.
graphene layer
dielectric layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 1 illustrates a related art graphene device (e.g., a graphene transistor and, more 1 0 particularly, a graphene field effect transistor (FET)) 110;
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Fet Contact Resistance | ≤ 450 Ω·μm | — |
Thickness | 0–300 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
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US 9,064,842Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 illustrates a related art graphene device (e.g., a graphene transistor and, more 1 0 particularly, a graphene field effect transistor (FET)) 110;
Figure 2 illustrates a semiconductor device 200 according to an exemplary aspect of the present invention;
Figure 3 illustrates a method 300 of forming a semiconductor device, according to an exemplary aspect of the present invention; 1 5
Figure 4A illustrates forming an oxide layer 410a in the method 400 of making a semiconductor device, according to an exemplary aspect of the present invention;
Figure 4B illustrates forming a trench 415a in the method 400 of making a semiconductor device, according to an exemplary aspect of the present invention;
Figure 4C illustrates forming first plural contacts 420a, 420b in the method 400 of making 20 a semiconductor device, according to an exemplary aspect of the present invention;
Figure 4 D illustrates forming a graphene layer 430 in the method 400 of making a semiconductor device, according to an exemplary aspect of the present invention;
Figure 4E illustrates forming second plural contacts 440a, 440b in the method 400 of making a semiconductor device, according to an exemplary aspect of the present invention; 25
Figure 4F illustrates the device 450 made by the method 400 of making a semiconductor device, according to an exemplary aspect of the present invention;
Figure 5A illustrates the first plural contacts 520a, 520b in the device 500, according to an exemplary aspect of the present invention;
Figure 5B illustrates the graphene layer 530 in the device 500, according to an exemplary 30 aspect of the present invention;
Figure 5 C illustrates the second plural contacts 540a, 540b in the device 500, according to 4 YO R₉₂₀₁₁₀₅₅₈US 1 an exemplary aspect of the present invention;
Figure 5D illustrates a interface between the oxide layer 5 10 b and a contact 520b of the first plural contacts 520a, 520b in the device 500, according to an exemplary aspect of the present invention; 5
Figure 5E illustrates a plan view of the device 500, according to an exemplary aspect of the present invention;
Figure 6A illustrates test results for a double-contacted device (e.g., device 200) including CVD-grown single-layer graphene, according to an exemplary aspect of the present invention;
Figure 6B illustrates test results for a double-contacted device (e.g., device 200) including 1 0 mechanically exfoliated bilayer graphene, according to an exemplary aspect of the present invention;
Figure 7A provides a graph illustrating a contact resistance distribution from a plurality of test sets including single-layer graphene devices tested by the inventors; and
Figure 7B illustrates an SEM image of a test set 750, with a device 750 according to an 1 5 exemplary aspect of the present invention (e.g., a double-contacted device) on the left side of the set 700, and the top-contacted device 760 on the right side of the set 700.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
(Cu rr ently amended) A semiconductor device, comprising: a semiconductor substrate; a dielectric layer formed in the semiconductor substrate; first plural contacts formed in the dielectric layer such that the dielectric layer comprises: a first portion which is formed between the first plural contacts; and a second portion which is formed between the semiconductor substrate and the first plural contacts substrate; a graphene layer formed on an upper surface of the first portion of the dielectric layer substrate and on an upper surface of the first plural contacts; and second plural contacts formed on the graphene layer such that the graphene layer is formed between the first plural contacts and the second plural contacts, wherein an area of contact of the first plural contacts is substantially the same as an area of contact of the second plural contacts, and the first plural contacts are substantially aligned with the second plural contacts to form a double-contact configuration, and wherein the upper surface of the first plural contacts is substantially co-planar with the upper surface of the first portion of the dielectric layer substrate, such that the graphene layer comprises an undistorted graphene layer.
(Cu rr ently amended) The semiconductor device of claim 1, wherein the dielectric layer substrate comprises plural trenches, and the first plural contacts are formed in the plural trenches, respectively.
The semiconductor device of claim 1, wherein the first plural contacts comprise a titanium layer, and a palladium layer formed on the titanium layer.
The semiconductor device of claim 1, wherein the graphene layer comprises one of a single-layer of graphene that was grown by chemical vapor deposition (CVD), and Docket No. YOR₉₂₀₁₁₀₅₅₈U S 1 3 Serial No. 13/425,302 YOR.867 bilayer graphene that was mechanically exfoliated from graphite flakes.
The semiconductor device of claim 1, wherein the second plural contacts comprise a titanium layer formed on the graphene layer, a palladium layer formed on the titanium layer, and a gold layer formed on the palladium layer.
The semiconductor device of claim 1, wherein an offset of a contact of the second plural contacts from a contact of the first plural contacts is not greater than 2 0 nm.
The semiconductor device of claim 1, wherein a contact resistance of the first plural contacts and the second plural contacts is less than 450 Q. m.
(Cu rr ently amended) The semiconductor device of claim 1, wherein the semiconductor substrate comprises a p+ Si substrate, and the dielectric layer comprises a layer of SiO 2 formed on the p+ Si substrate, and the first plural contacts are embedded in the layer of SiO 2.
(Cu rr ently amended) The semiconductor device of claim 1, wherein the dielectric layer substrate comprises an oxide layer and the first plural contacts are formed in the oxide layer, such that the upper surface of the first plural contacts is substantially co-planar with an upper surface of the oxide layer, and the graphene layer is formed on the upper surface of the first plural contacts and the upper surface of the oxide layer.
The semiconductor device of claim 1, wherein a width of the first plural contacts is substantially equal to a width of the second plural contacts, such that an innermost edge of the first plural contacts is aligned with an innermost edge of the second plural contacts, and an outermost edge of the first plural contacts is aligned with an outermost edge of the second plural contacts.
The semiconductor device of claim 1, wherein a thickness of the first plural contacts is in a range from 20 nm to 300 nm.
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(Cu rr ently amended) A semiconductor device, comprising: a semiconductor substrate; a dielectric layer comprising a pair of trenches; first source and drain contacts formed in the pair of trenches of the such that the dielectric layer comprises: a first portion which is formed between the first source and drain contacts; and a second portion which is formed between the semiconductor substrate and the first source and drain contacts substrate; Docket No. Y O R₉₂₀₁₁₀₅₅₈US₁ 4 Serial No. 13/425,302 YOR.867 a graphene layer formed on the first portion of the dielectric layer substrate and on the first source and drain contacts, an upper surface of the first source and drain contacts being substantially co-planar with an upper surface of the first portion of the dielectric layer substrate, and the graphene layer being formed on the upper surface of the first source and drain contacts and the upper surface of the first portion of the dielectric layer substrate, and a difference in height between the upper surface of the first source and drain contacts and a height of the upper surface of the first portion of the dielectric layer substrate being no greater than 5 nm, such that the graphene layer comprises an undistorted graphene layer; and second source and drain contacts formed on the graphene layer such that the graphene layer is formed between the first source and drain contacts and the second source and drain contacts, an area of the first source and drain contacts being substantially the same as an area of the second source and drain contacts, and the first source and drain contacts being substantially aligned with the second source and drain contacts to form a double-contact configuration.
(Cu rr ently amended) A graphene field effect transistor (FET), comprising: a back gate comprising a doped semiconductor substrate; a gate dielectric comprising a dielectric layer formed on the doped semiconductor substrate; first source and drain contacts embedded in the dielectric layer such that the dielectric layer comprises: a first portion which is formed between the first source and drain contacts; and a second portion which is formed between the doped semiconductor substrate and the first source and drain contacts; a channel layer comprising a graphene layer formed on a surface of the first portion of the gate dielectric layer and on a surface of the first source and drain contacts; and second source and drain contacts formed on the graphene layer such that the graphene layer is formed between the first source and drain contacts and the second source and drain contacts, wherein an area of contact of the first source and drain contacts is substantially the same as an area of contact of the second source and drain contacts, and the first source and drain contacts are substantially aligned with the second source and drain contacts to form a double- contact configuration, and Docket No. Y O R₉₂₀₁₁₀₅₅₈US₁ 5 Serial No. 13/425,302 YOR.867 wherein the surface of the first source and drain contacts is substantially co-planar with the surface of the first portion of the gate dielectric layer, such that the graphene layer comprises an undistorted graphene layer.
(Cu rr ently amended) A method of forming a semiconductor device, comprising: forming a dielectric layer in a semiconductor substrate; forming first plural contacts in the dielectric layer such that the dielectric layer comprises: a first portion which is formed between the first plural contacts; and a second portion which is formed between the semiconductor substrate and the first plural contacts a substrate; forming a graphene layer on an upper surface of the first portion of the dielectric layer substrate and on an upper surface of the first plural contacts; and forming second plural contacts on the graphene layer such that the graphene layer is formed between the first plural contacts and the second plural contacts, wherein an area of contact of the first plural contacts is substantially the same as an area of contact of the second plural contacts, and the first plural contacts are substantially aligned with the second plural contacts to form a double-contact configuration, and wherein the upper surface of the first plural contacts is substantially co-planar with the upper surface of the first portion of the dielectric layer substrate, such that the graphene layer comprises an undistorted graphene layer.
The method of claim 15, wherein the forming of the first plural contacts comp ri ses: etching the substrate to form a pair of trenches; forming a titanium layer in the pair of trenches; and forming a palladium layer formed on the titanium layer in the pair of trenches.
(Cu rr ently amended) The method of claim 15, wherein the forming of the graphene layer comprises one of: growing single-layer graphene by chemical vapor deposition (CVD) on a copper foil, transferring the grown single-layer graphene onto the first portion of the dielectric layer substrate Docket No. Y O R₉₂₀₁₁₀₅₅₈U S 1 6 Serial No. 13/425,302 YOR.867 and the first plural contacts, and patterning the single-layer graphene; and mechanically exfoliating bilayer graphene from graphite flakes.
The method of claim 15, wherein the forming of the second plural contacts comp ri ses: forming a titanium layer on the graphene layer; forming a palladium layer on the titanium layer; and forming a gold layer formed on the palladium layer.
The method of claim 15, wherein the forming of the second plural contacts comprises forming the second plural contacts such that an offset of a contact of the second plural contacts from a contact of the first plural contacts is not greater than 2 0 nm.
(Cu rr ently amended) The method of claim 15, wherein the semiconductor substrate comprises a p + Si substrate, and a layer of SiO 2 formed on the p + Si substrate, and the forming of the first source and drain contacts comprises embedding the first and second drain contacts in the layer of SiO 2.
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(Cu rr ently amended) A method of forming a semiconductor device, comprising: forming a dielectric layer in a semiconductor substrate; forming first source and drain contacts in the dielectric layer a substrate, such that: the dielectric layer comprises a first portion which is formed between the first Docket No. Y O R₉₂₀₁₁₀₅₅₈US₁ 7 Serial No. 13/425,302 YOR.867 source and drain contacts, and a second portion which is formed between the semiconductor substrate and the first source and drain contacts; and an upper surface of the first source and drain contacts is substantially co-planar with an upper surface of the first portion of the dielectric layer; substrate, and such that a difference in height between the upper surface of the first source and drain contacts and a height of the upper surface of the first portion of the dielectric layer substrate is no greater than 5 nm; forming a graphene layer on the upper surface of the first source and drain contacts and the upper surface of the first portion of the dielectric layer substrate such that the graphene layer comprises an undistorted graphene layer; and forming second source and drain contacts on the graphene layer such that the graphene layer is formed between the first source and drain contacts and the second source and drain contacts in a double-contact configuration, an area of the first source and drain contacts being substantially the same as an area of the second source and drain contacts, and the first source and drain contacts being substantially aligned with the second source and drain contacts.
Layer stacks claimed or described, ordered top of device to substrate.
double-contact semiconductor device with graphene layer
graphene field effect transistor (FET) with double-contact configuration
Materials described outside the worked examples.
graphene layer
dielectric layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 1 illustrates a related art graphene device (e.g., a graphene transistor and, more 1 0 particularly, a graphene field effect transistor (FET)) 110;
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Fet Contact Resistance | ≤ 450 Ω·μm | — |
Thickness | 0–300 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
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US 9,064,842Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 illustrates a related art graphene device (e.g., a graphene transistor and, more 1 0 particularly, a graphene field effect transistor (FET)) 110;
Figure 2 illustrates a semiconductor device 200 according to an exemplary aspect of the present invention;
Figure 3 illustrates a method 300 of forming a semiconductor device, according to an exemplary aspect of the present invention; 1 5
Figure 4A illustrates forming an oxide layer 410a in the method 400 of making a semiconductor device, according to an exemplary aspect of the present invention;
Figure 4B illustrates forming a trench 415a in the method 400 of making a semiconductor device, according to an exemplary aspect of the present invention;
Figure 4C illustrates forming first plural contacts 420a, 420b in the method 400 of making 20 a semiconductor device, according to an exemplary aspect of the present invention;
Figure 4 D illustrates forming a graphene layer 430 in the method 400 of making a semiconductor device, according to an exemplary aspect of the present invention;
Figure 4E illustrates forming second plural contacts 440a, 440b in the method 400 of making a semiconductor device, according to an exemplary aspect of the present invention; 25
Figure 4F illustrates the device 450 made by the method 400 of making a semiconductor device, according to an exemplary aspect of the present invention;
Figure 5A illustrates the first plural contacts 520a, 520b in the device 500, according to an exemplary aspect of the present invention;
Figure 5B illustrates the graphene layer 530 in the device 500, according to an exemplary 30 aspect of the present invention;
Figure 5 C illustrates the second plural contacts 540a, 540b in the device 500, according to 4 YO R₉₂₀₁₁₀₅₅₈US 1 an exemplary aspect of the present invention;
Figure 5D illustrates a interface between the oxide layer 5 10 b and a contact 520b of the first plural contacts 520a, 520b in the device 500, according to an exemplary aspect of the present invention; 5
Figure 5E illustrates a plan view of the device 500, according to an exemplary aspect of the present invention;
Figure 6A illustrates test results for a double-contacted device (e.g., device 200) including CVD-grown single-layer graphene, according to an exemplary aspect of the present invention;
Figure 6B illustrates test results for a double-contacted device (e.g., device 200) including 1 0 mechanically exfoliated bilayer graphene, according to an exemplary aspect of the present invention;
Figure 7A provides a graph illustrating a contact resistance distribution from a plurality of test sets including single-layer graphene devices tested by the inventors; and
Figure 7B illustrates an SEM image of a test set 750, with a device 750 according to an 1 5 exemplary aspect of the present invention (e.g., a double-contacted device) on the left side of the set 700, and the top-contacted device 760 on the right side of the set 700.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
(Cu rr ently amended) A semiconductor device, comprising: a semiconductor substrate; a dielectric layer formed in the semiconductor substrate; first plural contacts formed in the dielectric layer such that the dielectric layer comprises: a first portion which is formed between the first plural contacts; and a second portion which is formed between the semiconductor substrate and the first plural contacts substrate; a graphene layer formed on an upper surface of the first portion of the dielectric layer substrate and on an upper surface of the first plural contacts; and second plural contacts formed on the graphene layer such that the graphene layer is formed between the first plural contacts and the second plural contacts, wherein an area of contact of the first plural contacts is substantially the same as an area of contact of the second plural contacts, and the first plural contacts are substantially aligned with the second plural contacts to form a double-contact configuration, and wherein the upper surface of the first plural contacts is substantially co-planar with the upper surface of the first portion of the dielectric layer substrate, such that the graphene layer comprises an undistorted graphene layer.
(Cu rr ently amended) The semiconductor device of claim 1, wherein the dielectric layer substrate comprises plural trenches, and the first plural contacts are formed in the plural trenches, respectively.
The semiconductor device of claim 1, wherein the first plural contacts comprise a titanium layer, and a palladium layer formed on the titanium layer.
The semiconductor device of claim 1, wherein the graphene layer comprises one of a single-layer of graphene that was grown by chemical vapor deposition (CVD), and Docket No. YOR₉₂₀₁₁₀₅₅₈U S 1 3 Serial No. 13/425,302 YOR.867 bilayer graphene that was mechanically exfoliated from graphite flakes.
The semiconductor device of claim 1, wherein the second plural contacts comprise a titanium layer formed on the graphene layer, a palladium layer formed on the titanium layer, and a gold layer formed on the palladium layer.
The semiconductor device of claim 1, wherein an offset of a contact of the second plural contacts from a contact of the first plural contacts is not greater than 2 0 nm.
The semiconductor device of claim 1, wherein a contact resistance of the first plural contacts and the second plural contacts is less than 450 Q. m.
(Cu rr ently amended) The semiconductor device of claim 1, wherein the semiconductor substrate comprises a p+ Si substrate, and the dielectric layer comprises a layer of SiO 2 formed on the p+ Si substrate, and the first plural contacts are embedded in the layer of SiO 2.
(Cu rr ently amended) The semiconductor device of claim 1, wherein the dielectric layer substrate comprises an oxide layer and the first plural contacts are formed in the oxide layer, such that the upper surface of the first plural contacts is substantially co-planar with an upper surface of the oxide layer, and the graphene layer is formed on the upper surface of the first plural contacts and the upper surface of the oxide layer.
The semiconductor device of claim 1, wherein a width of the first plural contacts is substantially equal to a width of the second plural contacts, such that an innermost edge of the first plural contacts is aligned with an innermost edge of the second plural contacts, and an outermost edge of the first plural contacts is aligned with an outermost edge of the second plural contacts.
The semiconductor device of claim 1, wherein a thickness of the first plural contacts is in a range from 20 nm to 300 nm.
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(Cu rr ently amended) A semiconductor device, comprising: a semiconductor substrate; a dielectric layer comprising a pair of trenches; first source and drain contacts formed in the pair of trenches of the such that the dielectric layer comprises: a first portion which is formed between the first source and drain contacts; and a second portion which is formed between the semiconductor substrate and the first source and drain contacts substrate; Docket No. Y O R₉₂₀₁₁₀₅₅₈US₁ 4 Serial No. 13/425,302 YOR.867 a graphene layer formed on the first portion of the dielectric layer substrate and on the first source and drain contacts, an upper surface of the first source and drain contacts being substantially co-planar with an upper surface of the first portion of the dielectric layer substrate, and the graphene layer being formed on the upper surface of the first source and drain contacts and the upper surface of the first portion of the dielectric layer substrate, and a difference in height between the upper surface of the first source and drain contacts and a height of the upper surface of the first portion of the dielectric layer substrate being no greater than 5 nm, such that the graphene layer comprises an undistorted graphene layer; and second source and drain contacts formed on the graphene layer such that the graphene layer is formed between the first source and drain contacts and the second source and drain contacts, an area of the first source and drain contacts being substantially the same as an area of the second source and drain contacts, and the first source and drain contacts being substantially aligned with the second source and drain contacts to form a double-contact configuration.
(Cu rr ently amended) A graphene field effect transistor (FET), comprising: a back gate comprising a doped semiconductor substrate; a gate dielectric comprising a dielectric layer formed on the doped semiconductor substrate; first source and drain contacts embedded in the dielectric layer such that the dielectric layer comprises: a first portion which is formed between the first source and drain contacts; and a second portion which is formed between the doped semiconductor substrate and the first source and drain contacts; a channel layer comprising a graphene layer formed on a surface of the first portion of the gate dielectric layer and on a surface of the first source and drain contacts; and second source and drain contacts formed on the graphene layer such that the graphene layer is formed between the first source and drain contacts and the second source and drain contacts, wherein an area of contact of the first source and drain contacts is substantially the same as an area of contact of the second source and drain contacts, and the first source and drain contacts are substantially aligned with the second source and drain contacts to form a double- contact configuration, and Docket No. Y O R₉₂₀₁₁₀₅₅₈US₁ 5 Serial No. 13/425,302 YOR.867 wherein the surface of the first source and drain contacts is substantially co-planar with the surface of the first portion of the gate dielectric layer, such that the graphene layer comprises an undistorted graphene layer.
(Cu rr ently amended) A method of forming a semiconductor device, comprising: forming a dielectric layer in a semiconductor substrate; forming first plural contacts in the dielectric layer such that the dielectric layer comprises: a first portion which is formed between the first plural contacts; and a second portion which is formed between the semiconductor substrate and the first plural contacts a substrate; forming a graphene layer on an upper surface of the first portion of the dielectric layer substrate and on an upper surface of the first plural contacts; and forming second plural contacts on the graphene layer such that the graphene layer is formed between the first plural contacts and the second plural contacts, wherein an area of contact of the first plural contacts is substantially the same as an area of contact of the second plural contacts, and the first plural contacts are substantially aligned with the second plural contacts to form a double-contact configuration, and wherein the upper surface of the first plural contacts is substantially co-planar with the upper surface of the first portion of the dielectric layer substrate, such that the graphene layer comprises an undistorted graphene layer.
The method of claim 15, wherein the forming of the first plural contacts comp ri ses: etching the substrate to form a pair of trenches; forming a titanium layer in the pair of trenches; and forming a palladium layer formed on the titanium layer in the pair of trenches.
(Cu rr ently amended) The method of claim 15, wherein the forming of the graphene layer comprises one of: growing single-layer graphene by chemical vapor deposition (CVD) on a copper foil, transferring the grown single-layer graphene onto the first portion of the dielectric layer substrate Docket No. Y O R₉₂₀₁₁₀₅₅₈U S 1 6 Serial No. 13/425,302 YOR.867 and the first plural contacts, and patterning the single-layer graphene; and mechanically exfoliating bilayer graphene from graphite flakes.
The method of claim 15, wherein the forming of the second plural contacts comp ri ses: forming a titanium layer on the graphene layer; forming a palladium layer on the titanium layer; and forming a gold layer formed on the palladium layer.
The method of claim 15, wherein the forming of the second plural contacts comprises forming the second plural contacts such that an offset of a contact of the second plural contacts from a contact of the first plural contacts is not greater than 2 0 nm.
(Cu rr ently amended) The method of claim 15, wherein the semiconductor substrate comprises a p + Si substrate, and a layer of SiO 2 formed on the p + Si substrate, and the forming of the first source and drain contacts comprises embedding the first and second drain contacts in the layer of SiO 2.
18-19. canceled
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(Cu rr ently amended) A method of forming a semiconductor device, comprising: forming a dielectric layer in a semiconductor substrate; forming first source and drain contacts in the dielectric layer a substrate, such that: the dielectric layer comprises a first portion which is formed between the first Docket No. Y O R₉₂₀₁₁₀₅₅₈US₁ 7 Serial No. 13/425,302 YOR.867 source and drain contacts, and a second portion which is formed between the semiconductor substrate and the first source and drain contacts; and an upper surface of the first source and drain contacts is substantially co-planar with an upper surface of the first portion of the dielectric layer; substrate, and such that a difference in height between the upper surface of the first source and drain contacts and a height of the upper surface of the first portion of the dielectric layer substrate is no greater than 5 nm; forming a graphene layer on the upper surface of the first source and drain contacts and the upper surface of the first portion of the dielectric layer substrate such that the graphene layer comprises an undistorted graphene layer; and forming second source and drain contacts on the graphene layer such that the graphene layer is formed between the first source and drain contacts and the second source and drain contacts in a double-contact configuration, an area of the first source and drain contacts being substantially the same as an area of the second source and drain contacts, and the first source and drain contacts being substantially aligned with the second source and drain contacts.
Layer stacks claimed or described, ordered top of device to substrate.
double-contact semiconductor device with graphene layer
graphene field effect transistor (FET) with double-contact configuration
Materials described outside the worked examples.
graphene layer
dielectric layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 1 illustrates a related art graphene device (e.g., a graphene transistor and, more 1 0 particularly, a graphene field effect transistor (FET)) 110;
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Fet Contact Resistance | ≤ 450 Ω·μm | — |
Thickness | 0–300 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,064,842Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 illustrates a related art graphene device (e.g., a graphene transistor and, more 1 0 particularly, a graphene field effect transistor (FET)) 110;
Figure 2 illustrates a semiconductor device 200 according to an exemplary aspect of the present invention;
Figure 3 illustrates a method 300 of forming a semiconductor device, according to an exemplary aspect of the present invention; 1 5
Figure 4A illustrates forming an oxide layer 410a in the method 400 of making a semiconductor device, according to an exemplary aspect of the present invention;
Figure 4B illustrates forming a trench 415a in the method 400 of making a semiconductor device, according to an exemplary aspect of the present invention;
Figure 4C illustrates forming first plural contacts 420a, 420b in the method 400 of making 20 a semiconductor device, according to an exemplary aspect of the present invention;
Figure 4 D illustrates forming a graphene layer 430 in the method 400 of making a semiconductor device, according to an exemplary aspect of the present invention;
Figure 4E illustrates forming second plural contacts 440a, 440b in the method 400 of making a semiconductor device, according to an exemplary aspect of the present invention; 25
Figure 4F illustrates the device 450 made by the method 400 of making a semiconductor device, according to an exemplary aspect of the present invention;
Figure 5A illustrates the first plural contacts 520a, 520b in the device 500, according to an exemplary aspect of the present invention;
Figure 5B illustrates the graphene layer 530 in the device 500, according to an exemplary 30 aspect of the present invention;
Figure 5 C illustrates the second plural contacts 540a, 540b in the device 500, according to 4 YO R₉₂₀₁₁₀₅₅₈US 1 an exemplary aspect of the present invention;
Figure 5D illustrates a interface between the oxide layer 5 10 b and a contact 520b of the first plural contacts 520a, 520b in the device 500, according to an exemplary aspect of the present invention; 5
Figure 5E illustrates a plan view of the device 500, according to an exemplary aspect of the present invention;
Figure 6A illustrates test results for a double-contacted device (e.g., device 200) including CVD-grown single-layer graphene, according to an exemplary aspect of the present invention;
Figure 6B illustrates test results for a double-contacted device (e.g., device 200) including 1 0 mechanically exfoliated bilayer graphene, according to an exemplary aspect of the present invention;
Figure 7A provides a graph illustrating a contact resistance distribution from a plurality of test sets including single-layer graphene devices tested by the inventors; and
Figure 7B illustrates an SEM image of a test set 750, with a device 750 according to an 1 5 exemplary aspect of the present invention (e.g., a double-contacted device) on the left side of the set 700, and the top-contacted device 760 on the right side of the set 700.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
(Cu rr ently amended) A semiconductor device, comprising: a semiconductor substrate; a dielectric layer formed in the semiconductor substrate; first plural contacts formed in the dielectric layer such that the dielectric layer comprises: a first portion which is formed between the first plural contacts; and a second portion which is formed between the semiconductor substrate and the first plural contacts substrate; a graphene layer formed on an upper surface of the first portion of the dielectric layer substrate and on an upper surface of the first plural contacts; and second plural contacts formed on the graphene layer such that the graphene layer is formed between the first plural contacts and the second plural contacts, wherein an area of contact of the first plural contacts is substantially the same as an area of contact of the second plural contacts, and the first plural contacts are substantially aligned with the second plural contacts to form a double-contact configuration, and wherein the upper surface of the first plural contacts is substantially co-planar with the upper surface of the first portion of the dielectric layer substrate, such that the graphene layer comprises an undistorted graphene layer.
(Cu rr ently amended) The semiconductor device of claim 1, wherein the dielectric layer substrate comprises plural trenches, and the first plural contacts are formed in the plural trenches, respectively.
The semiconductor device of claim 1, wherein the first plural contacts comprise a titanium layer, and a palladium layer formed on the titanium layer.
The semiconductor device of claim 1, wherein the graphene layer comprises one of a single-layer of graphene that was grown by chemical vapor deposition (CVD), and Docket No. YOR₉₂₀₁₁₀₅₅₈U S 1 3 Serial No. 13/425,302 YOR.867 bilayer graphene that was mechanically exfoliated from graphite flakes.
The semiconductor device of claim 1, wherein the second plural contacts comprise a titanium layer formed on the graphene layer, a palladium layer formed on the titanium layer, and a gold layer formed on the palladium layer.
The semiconductor device of claim 1, wherein an offset of a contact of the second plural contacts from a contact of the first plural contacts is not greater than 2 0 nm.
The semiconductor device of claim 1, wherein a contact resistance of the first plural contacts and the second plural contacts is less than 450 Q. m.
(Cu rr ently amended) The semiconductor device of claim 1, wherein the semiconductor substrate comprises a p+ Si substrate, and the dielectric layer comprises a layer of SiO 2 formed on the p+ Si substrate, and the first plural contacts are embedded in the layer of SiO 2.
(Cu rr ently amended) The semiconductor device of claim 1, wherein the dielectric layer substrate comprises an oxide layer and the first plural contacts are formed in the oxide layer, such that the upper surface of the first plural contacts is substantially co-planar with an upper surface of the oxide layer, and the graphene layer is formed on the upper surface of the first plural contacts and the upper surface of the oxide layer.
The semiconductor device of claim 1, wherein a width of the first plural contacts is substantially equal to a width of the second plural contacts, such that an innermost edge of the first plural contacts is aligned with an innermost edge of the second plural contacts, and an outermost edge of the first plural contacts is aligned with an outermost edge of the second plural contacts.
The semiconductor device of claim 1, wherein a thickness of the first plural contacts is in a range from 20 nm to 300 nm.
3-4. canceled
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(Cu rr ently amended) A semiconductor device, comprising: a semiconductor substrate; a dielectric layer comprising a pair of trenches; first source and drain contacts formed in the pair of trenches of the such that the dielectric layer comprises: a first portion which is formed between the first source and drain contacts; and a second portion which is formed between the semiconductor substrate and the first source and drain contacts substrate; Docket No. Y O R₉₂₀₁₁₀₅₅₈US₁ 4 Serial No. 13/425,302 YOR.867 a graphene layer formed on the first portion of the dielectric layer substrate and on the first source and drain contacts, an upper surface of the first source and drain contacts being substantially co-planar with an upper surface of the first portion of the dielectric layer substrate, and the graphene layer being formed on the upper surface of the first source and drain contacts and the upper surface of the first portion of the dielectric layer substrate, and a difference in height between the upper surface of the first source and drain contacts and a height of the upper surface of the first portion of the dielectric layer substrate being no greater than 5 nm, such that the graphene layer comprises an undistorted graphene layer; and second source and drain contacts formed on the graphene layer such that the graphene layer is formed between the first source and drain contacts and the second source and drain contacts, an area of the first source and drain contacts being substantially the same as an area of the second source and drain contacts, and the first source and drain contacts being substantially aligned with the second source and drain contacts to form a double-contact configuration.
(Cu rr ently amended) A graphene field effect transistor (FET), comprising: a back gate comprising a doped semiconductor substrate; a gate dielectric comprising a dielectric layer formed on the doped semiconductor substrate; first source and drain contacts embedded in the dielectric layer such that the dielectric layer comprises: a first portion which is formed between the first source and drain contacts; and a second portion which is formed between the doped semiconductor substrate and the first source and drain contacts; a channel layer comprising a graphene layer formed on a surface of the first portion of the gate dielectric layer and on a surface of the first source and drain contacts; and second source and drain contacts formed on the graphene layer such that the graphene layer is formed between the first source and drain contacts and the second source and drain contacts, wherein an area of contact of the first source and drain contacts is substantially the same as an area of contact of the second source and drain contacts, and the first source and drain contacts are substantially aligned with the second source and drain contacts to form a double- contact configuration, and Docket No. Y O R₉₂₀₁₁₀₅₅₈US₁ 5 Serial No. 13/425,302 YOR.867 wherein the surface of the first source and drain contacts is substantially co-planar with the surface of the first portion of the gate dielectric layer, such that the graphene layer comprises an undistorted graphene layer.
(Cu rr ently amended) A method of forming a semiconductor device, comprising: forming a dielectric layer in a semiconductor substrate; forming first plural contacts in the dielectric layer such that the dielectric layer comprises: a first portion which is formed between the first plural contacts; and a second portion which is formed between the semiconductor substrate and the first plural contacts a substrate; forming a graphene layer on an upper surface of the first portion of the dielectric layer substrate and on an upper surface of the first plural contacts; and forming second plural contacts on the graphene layer such that the graphene layer is formed between the first plural contacts and the second plural contacts, wherein an area of contact of the first plural contacts is substantially the same as an area of contact of the second plural contacts, and the first plural contacts are substantially aligned with the second plural contacts to form a double-contact configuration, and wherein the upper surface of the first plural contacts is substantially co-planar with the upper surface of the first portion of the dielectric layer substrate, such that the graphene layer comprises an undistorted graphene layer.
The method of claim 15, wherein the forming of the first plural contacts comp ri ses: etching the substrate to form a pair of trenches; forming a titanium layer in the pair of trenches; and forming a palladium layer formed on the titanium layer in the pair of trenches.
(Cu rr ently amended) The method of claim 15, wherein the forming of the graphene layer comprises one of: growing single-layer graphene by chemical vapor deposition (CVD) on a copper foil, transferring the grown single-layer graphene onto the first portion of the dielectric layer substrate Docket No. Y O R₉₂₀₁₁₀₅₅₈U S 1 6 Serial No. 13/425,302 YOR.867 and the first plural contacts, and patterning the single-layer graphene; and mechanically exfoliating bilayer graphene from graphite flakes.
The method of claim 15, wherein the forming of the second plural contacts comp ri ses: forming a titanium layer on the graphene layer; forming a palladium layer on the titanium layer; and forming a gold layer formed on the palladium layer.
The method of claim 15, wherein the forming of the second plural contacts comprises forming the second plural contacts such that an offset of a contact of the second plural contacts from a contact of the first plural contacts is not greater than 2 0 nm.
(Cu rr ently amended) The method of claim 15, wherein the semiconductor substrate comprises a p + Si substrate, and a layer of SiO 2 formed on the p + Si substrate, and the forming of the first source and drain contacts comprises embedding the first and second drain contacts in the layer of SiO 2.
18-19. canceled
canceled
canceled
(Cu rr ently amended) A method of forming a semiconductor device, comprising: forming a dielectric layer in a semiconductor substrate; forming first source and drain contacts in the dielectric layer a substrate, such that: the dielectric layer comprises a first portion which is formed between the first Docket No. Y O R₉₂₀₁₁₀₅₅₈US₁ 7 Serial No. 13/425,302 YOR.867 source and drain contacts, and a second portion which is formed between the semiconductor substrate and the first source and drain contacts; and an upper surface of the first source and drain contacts is substantially co-planar with an upper surface of the first portion of the dielectric layer; substrate, and such that a difference in height between the upper surface of the first source and drain contacts and a height of the upper surface of the first portion of the dielectric layer substrate is no greater than 5 nm; forming a graphene layer on the upper surface of the first source and drain contacts and the upper surface of the first portion of the dielectric layer substrate such that the graphene layer comprises an undistorted graphene layer; and forming second source and drain contacts on the graphene layer such that the graphene layer is formed between the first source and drain contacts and the second source and drain contacts in a double-contact configuration, an area of the first source and drain contacts being substantially the same as an area of the second source and drain contacts, and the first source and drain contacts being substantially aligned with the second source and drain contacts.
Layer stacks claimed or described, ordered top of device to substrate.
double-contact semiconductor device with graphene layer
graphene field effect transistor (FET) with double-contact configuration
Materials described outside the worked examples.
graphene layer
dielectric layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 1 illustrates a related art graphene device (e.g., a graphene transistor and, more 1 0 particularly, a graphene field effect transistor (FET)) 110;
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Fet Contact Resistance | ≤ 450 Ω·μm | — |
Thickness | 0–300 nm |
Related documents with shared materials, methods, properties, or citations.
first plural contacts
titanium
Ti
palladium
Pd
gold
Au
p+ Si substrate
SiO₂ layer
SiO₂
copper foil
Figure 7A provides a graph illustrating a contact resistance distribution from a plurality of test sets including single-layer graphene devices tested by the inventors; and
Figure 7B illustrates an SEM image of a test set 750, with a device 750 according to an 1 5 exemplary aspect of the present invention (e.g., a double-contacted device) on the left side of the set 700, and the top-contacted device 760 on the right side of the set 700.
| — |
Thickness | 0–1000 nm | — |
Thickness | ≤ 1 nm | — |
Thickness | ≥ 5 nm | — |
Thickness | 20–1000 nm | — |
Thickness | 20–300 nm | — |
first plural contacts
titanium
Ti
palladium
Pd
gold
Au
p+ Si substrate
SiO₂ layer
SiO₂
copper foil
Figure 7A provides a graph illustrating a contact resistance distribution from a plurality of test sets including single-layer graphene devices tested by the inventors; and
Figure 7B illustrates an SEM image of a test set 750, with a device 750 according to an 1 5 exemplary aspect of the present invention (e.g., a double-contacted device) on the left side of the set 700, and the top-contacted device 760 on the right side of the set 700.
| — |
Thickness | 0–1000 nm | — |
Thickness | ≤ 1 nm | — |
Thickness | ≥ 5 nm | — |
Thickness | 20–1000 nm | — |
Thickness | 20–300 nm | — |
first plural contacts
titanium
Ti
palladium
Pd
gold
Au
p+ Si substrate
SiO₂ layer
SiO₂
copper foil
Figure 7A provides a graph illustrating a contact resistance distribution from a plurality of test sets including single-layer graphene devices tested by the inventors; and
Figure 7B illustrates an SEM image of a test set 750, with a device 750 according to an 1 5 exemplary aspect of the present invention (e.g., a double-contacted device) on the left side of the set 700, and the top-contacted device 760 on the right side of the set 700.
| — |
Thickness | 0–1000 nm | — |
Thickness | ≤ 1 nm | — |
Thickness | ≥ 5 nm | — |
Thickness | 20–1000 nm | — |
Thickness | 20–300 nm | — |
first plural contacts
titanium
Ti
palladium
Pd
gold
Au
p+ Si substrate
SiO₂ layer
SiO₂
copper foil
Figure 7A provides a graph illustrating a contact resistance distribution from a plurality of test sets including single-layer graphene devices tested by the inventors; and
Figure 7B illustrates an SEM image of a test set 750, with a device 750 according to an 1 5 exemplary aspect of the present invention (e.g., a double-contacted device) on the left side of the set 700, and the top-contacted device 760 on the right side of the set 700.
| — |
Thickness | 0–1000 nm | — |
Thickness | ≤ 1 nm | — |
Thickness | ≥ 5 nm | — |
Thickness | 20–1000 nm | — |
Thickness | 20–300 nm | — |