Patent
Atlas literature
Patent
US 12,255,232 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a diagram of an example environment in which 25 systems and/or methods described herein may be imple- mented.
FIG. 2 is a diagram of an example semiconductor struc- ture described herein.
FIG. 3 is a diagram of an example semiconductor struc- 30 ture described herein.
FIG. 4L. Alternatively, the SiN layer 404 may be omitted when silicon is not implanted into the liner 304. As shown in
FIG. 5 is a diagram of example components of one or more devices of
FIGS. 6 and 7 are flowcharts of example processes associated with forming semiconductor structures described herein.
FIG. 7. Additionally, or alternatively, two or more of the blocks of process 700 may be performed in parallel. In this way, depositing gallium nitride and …
FIGS. 35 4A-4R. As shown in
FIG. 50 3. As a result, contact resistance is reduced at the aluminum nitride liner to improve current flow in the pixel sensor 200, as described in further …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device, comprising: a substrate; a drain structure in the substrate comprising a buffer portion in the substrate, a drain portion above the buffer portion, and a liner disposed between the drain portion and the substrate, wherein the buffer portion comprises B₂ gallium nitride and carbon (GaN:C), the drain portion comprises doped gallium nitride (GaN), and the liner comprises aluminum nitride (AlN); a source comprising doped material; and a channel electrically connecting the drain to the source, wherein the liner includes implanted silicon at least at an interface between the channel and the liner.
The semiconductor device of claim 1, further compris-ing: a gate structure formed over the channel, wherein the gate structure is associated with a breakdown field larger than 7×105 Volts per centimeter (V/cm).
The semiconductor device of claim 1, wherein current is to flow from the drain structure to the source through the channel with a current density of at least 5400 milliamperes per millimeter (mA/mm) at 10 Volts.
The semiconductor device of claim 1, wherein the drain portion comprises cubic GaN (c-GaN).
The semiconductor device of claim 1, wherein the buffer portion forms a substantially V-shaped structure.
The semiconductor device of claim 1, wherein the liner has a thickness of no more than 5 nanometers (nm).
A method, comprising: forming an upper recess in a substrate, wherein the upper recess is substantially rectangular; forming a liner comprising aluminum nitride (AlN) on sidewalls of the upper recess; forming a lower recess in the substrate, wherein the lower recess is substantially V-shaped; implanting silicon in the liner at least at an interface between the liner and a portion of the substrate to include a channel; and forming a drain structure comprising doped gallium nitride (GaN) in the lower recess and the upper recess.
The method of claim 7, wherein forming the upper recess comprises: patterning a photoresist material over the substrate; and forming the upper recess in the substrate using lithogra-phy, wherein the photoresist material is removed after the drain structure is formed.
The method of claim 7, wherein forming the liner comprises: depositing AlN on the sidewalls and a bottom surface of the upper recess; and etching the AlN from the bottom surface of the upper recess.
The method of claim 7, further comprising: forming a layer of silicon nitride (SiN) on the sidewalls and a bottom surface of the upper recess; and etching the SiN from the bottom surface of the upper recess.
The method of claim 7, wherein forming the drain structure comprises: forming a buffer portion comprising gallium nitride and carbon (GaN:C) in at least the lower recess; and forming a drain portion comprising doped gallium nitride (n-GaN) in at least the upper recess.
A method, comprising: forming an upper recess in a substrate, wherein the upper recess is substantially rectangular; forming a liner comprising aluminum nitride (AlN) on sidewalls of the upper recess; forming a lower recess in the substrate, wherein the lower recess is substantially V-shaped; forming a buffer portion comprising gallium nitride and carbon (GaN:C) in at least the lower recess; and forming a drain portion comprising doped gallium nitride (n-GaN) in at least the upper recess.
The method of claim 14, wherein forming the lower recess comprises: using tetramethyl ammonium hydroxide (TMAH) to etch the lower recess under the upper recess.
The method of claim 14, wherein forming the buffer portion comprises: depositing gallium nitride and carbon using atomic layer deposition (ALD), wherein the GaN:C is formed in the lower recess and polycrystalline GaN:C (poly-GaN:C) is formed over the substrate; and etching the poly-GaN:C using hydrochloric acid (HCl).
The method of claim 14, further comprising: forming doped silicon on the substrate that has an interface with the liner to form a channel.
The method of claim 14, further comprising: forming a photoresist layer over the substrate, wherein the photoresist layer is used to form the upper recess with lithography; and etching the photoresist layer using a buffered oxide etch (BOE) after forming the drain portion. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
gallium nitride drain transistor
Materials described outside the worked examples.
gallium nitride and carbon
GaN:C
doped gallium nitride
GaN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
gate structure breakdown field | ≥ 700000 V/cm | — |
drain-to-source current density at 10 V | >=5400 mA/mm | — |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 1
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,255,232 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a diagram of an example environment in which 25 systems and/or methods described herein may be imple- mented.
FIG. 2 is a diagram of an example semiconductor struc- ture described herein.
FIG. 3 is a diagram of an example semiconductor struc- 30 ture described herein.
FIG. 4L. Alternatively, the SiN layer 404 may be omitted when silicon is not implanted into the liner 304. As shown in
FIG. 5 is a diagram of example components of one or more devices of
FIGS. 6 and 7 are flowcharts of example processes associated with forming semiconductor structures described herein.
FIG. 7. Additionally, or alternatively, two or more of the blocks of process 700 may be performed in parallel. In this way, depositing gallium nitride and …
FIGS. 35 4A-4R. As shown in
FIG. 50 3. As a result, contact resistance is reduced at the aluminum nitride liner to improve current flow in the pixel sensor 200, as described in further …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device, comprising: a substrate; a drain structure in the substrate comprising a buffer portion in the substrate, a drain portion above the buffer portion, and a liner disposed between the drain portion and the substrate, wherein the buffer portion comprises B₂ gallium nitride and carbon (GaN:C), the drain portion comprises doped gallium nitride (GaN), and the liner comprises aluminum nitride (AlN); a source comprising doped material; and a channel electrically connecting the drain to the source, wherein the liner includes implanted silicon at least at an interface between the channel and the liner.
The semiconductor device of claim 1, further compris-ing: a gate structure formed over the channel, wherein the gate structure is associated with a breakdown field larger than 7×105 Volts per centimeter (V/cm).
The semiconductor device of claim 1, wherein current is to flow from the drain structure to the source through the channel with a current density of at least 5400 milliamperes per millimeter (mA/mm) at 10 Volts.
The semiconductor device of claim 1, wherein the drain portion comprises cubic GaN (c-GaN).
The semiconductor device of claim 1, wherein the buffer portion forms a substantially V-shaped structure.
The semiconductor device of claim 1, wherein the liner has a thickness of no more than 5 nanometers (nm).
A method, comprising: forming an upper recess in a substrate, wherein the upper recess is substantially rectangular; forming a liner comprising aluminum nitride (AlN) on sidewalls of the upper recess; forming a lower recess in the substrate, wherein the lower recess is substantially V-shaped; implanting silicon in the liner at least at an interface between the liner and a portion of the substrate to include a channel; and forming a drain structure comprising doped gallium nitride (GaN) in the lower recess and the upper recess.
The method of claim 7, wherein forming the upper recess comprises: patterning a photoresist material over the substrate; and forming the upper recess in the substrate using lithogra-phy, wherein the photoresist material is removed after the drain structure is formed.
The method of claim 7, wherein forming the liner comprises: depositing AlN on the sidewalls and a bottom surface of the upper recess; and etching the AlN from the bottom surface of the upper recess.
The method of claim 7, further comprising: forming a layer of silicon nitride (SiN) on the sidewalls and a bottom surface of the upper recess; and etching the SiN from the bottom surface of the upper recess.
The method of claim 7, wherein forming the drain structure comprises: forming a buffer portion comprising gallium nitride and carbon (GaN:C) in at least the lower recess; and forming a drain portion comprising doped gallium nitride (n-GaN) in at least the upper recess.
A method, comprising: forming an upper recess in a substrate, wherein the upper recess is substantially rectangular; forming a liner comprising aluminum nitride (AlN) on sidewalls of the upper recess; forming a lower recess in the substrate, wherein the lower recess is substantially V-shaped; forming a buffer portion comprising gallium nitride and carbon (GaN:C) in at least the lower recess; and forming a drain portion comprising doped gallium nitride (n-GaN) in at least the upper recess.
The method of claim 14, wherein forming the lower recess comprises: using tetramethyl ammonium hydroxide (TMAH) to etch the lower recess under the upper recess.
The method of claim 14, wherein forming the buffer portion comprises: depositing gallium nitride and carbon using atomic layer deposition (ALD), wherein the GaN:C is formed in the lower recess and polycrystalline GaN:C (poly-GaN:C) is formed over the substrate; and etching the poly-GaN:C using hydrochloric acid (HCl).
The method of claim 14, further comprising: forming doped silicon on the substrate that has an interface with the liner to form a channel.
The method of claim 14, further comprising: forming a photoresist layer over the substrate, wherein the photoresist layer is used to form the upper recess with lithography; and etching the photoresist layer using a buffered oxide etch (BOE) after forming the drain portion. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
gallium nitride drain transistor
Materials described outside the worked examples.
gallium nitride and carbon
GaN:C
doped gallium nitride
GaN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
gate structure breakdown field | ≥ 700000 V/cm | — |
drain-to-source current density at 10 V | >=5400 mA/mm | — |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 1
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,255,232 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a diagram of an example environment in which 25 systems and/or methods described herein may be imple- mented.
FIG. 2 is a diagram of an example semiconductor struc- ture described herein.
FIG. 3 is a diagram of an example semiconductor struc- 30 ture described herein.
FIG. 4L. Alternatively, the SiN layer 404 may be omitted when silicon is not implanted into the liner 304. As shown in
FIG. 5 is a diagram of example components of one or more devices of
FIGS. 6 and 7 are flowcharts of example processes associated with forming semiconductor structures described herein.
FIG. 7. Additionally, or alternatively, two or more of the blocks of process 700 may be performed in parallel. In this way, depositing gallium nitride and …
FIGS. 35 4A-4R. As shown in
FIG. 50 3. As a result, contact resistance is reduced at the aluminum nitride liner to improve current flow in the pixel sensor 200, as described in further …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device, comprising: a substrate; a drain structure in the substrate comprising a buffer portion in the substrate, a drain portion above the buffer portion, and a liner disposed between the drain portion and the substrate, wherein the buffer portion comprises B₂ gallium nitride and carbon (GaN:C), the drain portion comprises doped gallium nitride (GaN), and the liner comprises aluminum nitride (AlN); a source comprising doped material; and a channel electrically connecting the drain to the source, wherein the liner includes implanted silicon at least at an interface between the channel and the liner.
The semiconductor device of claim 1, further compris-ing: a gate structure formed over the channel, wherein the gate structure is associated with a breakdown field larger than 7×105 Volts per centimeter (V/cm).
The semiconductor device of claim 1, wherein current is to flow from the drain structure to the source through the channel with a current density of at least 5400 milliamperes per millimeter (mA/mm) at 10 Volts.
The semiconductor device of claim 1, wherein the drain portion comprises cubic GaN (c-GaN).
The semiconductor device of claim 1, wherein the buffer portion forms a substantially V-shaped structure.
The semiconductor device of claim 1, wherein the liner has a thickness of no more than 5 nanometers (nm).
A method, comprising: forming an upper recess in a substrate, wherein the upper recess is substantially rectangular; forming a liner comprising aluminum nitride (AlN) on sidewalls of the upper recess; forming a lower recess in the substrate, wherein the lower recess is substantially V-shaped; implanting silicon in the liner at least at an interface between the liner and a portion of the substrate to include a channel; and forming a drain structure comprising doped gallium nitride (GaN) in the lower recess and the upper recess.
The method of claim 7, wherein forming the upper recess comprises: patterning a photoresist material over the substrate; and forming the upper recess in the substrate using lithogra-phy, wherein the photoresist material is removed after the drain structure is formed.
The method of claim 7, wherein forming the liner comprises: depositing AlN on the sidewalls and a bottom surface of the upper recess; and etching the AlN from the bottom surface of the upper recess.
The method of claim 7, further comprising: forming a layer of silicon nitride (SiN) on the sidewalls and a bottom surface of the upper recess; and etching the SiN from the bottom surface of the upper recess.
The method of claim 7, wherein forming the drain structure comprises: forming a buffer portion comprising gallium nitride and carbon (GaN:C) in at least the lower recess; and forming a drain portion comprising doped gallium nitride (n-GaN) in at least the upper recess.
A method, comprising: forming an upper recess in a substrate, wherein the upper recess is substantially rectangular; forming a liner comprising aluminum nitride (AlN) on sidewalls of the upper recess; forming a lower recess in the substrate, wherein the lower recess is substantially V-shaped; forming a buffer portion comprising gallium nitride and carbon (GaN:C) in at least the lower recess; and forming a drain portion comprising doped gallium nitride (n-GaN) in at least the upper recess.
The method of claim 14, wherein forming the lower recess comprises: using tetramethyl ammonium hydroxide (TMAH) to etch the lower recess under the upper recess.
The method of claim 14, wherein forming the buffer portion comprises: depositing gallium nitride and carbon using atomic layer deposition (ALD), wherein the GaN:C is formed in the lower recess and polycrystalline GaN:C (poly-GaN:C) is formed over the substrate; and etching the poly-GaN:C using hydrochloric acid (HCl).
The method of claim 14, further comprising: forming doped silicon on the substrate that has an interface with the liner to form a channel.
The method of claim 14, further comprising: forming a photoresist layer over the substrate, wherein the photoresist layer is used to form the upper recess with lithography; and etching the photoresist layer using a buffered oxide etch (BOE) after forming the drain portion. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
gallium nitride drain transistor
Materials described outside the worked examples.
gallium nitride and carbon
GaN:C
doped gallium nitride
GaN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
gate structure breakdown field | ≥ 700000 V/cm | — |
drain-to-source current density at 10 V | >=5400 mA/mm | — |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 1
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,255,232 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a diagram of an example environment in which 25 systems and/or methods described herein may be imple- mented.
FIG. 2 is a diagram of an example semiconductor struc- ture described herein.
FIG. 3 is a diagram of an example semiconductor struc- 30 ture described herein.
FIG. 4L. Alternatively, the SiN layer 404 may be omitted when silicon is not implanted into the liner 304. As shown in
FIG. 5 is a diagram of example components of one or more devices of
FIGS. 6 and 7 are flowcharts of example processes associated with forming semiconductor structures described herein.
FIG. 7. Additionally, or alternatively, two or more of the blocks of process 700 may be performed in parallel. In this way, depositing gallium nitride and …
FIGS. 35 4A-4R. As shown in
FIG. 50 3. As a result, contact resistance is reduced at the aluminum nitride liner to improve current flow in the pixel sensor 200, as described in further …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device, comprising: a substrate; a drain structure in the substrate comprising a buffer portion in the substrate, a drain portion above the buffer portion, and a liner disposed between the drain portion and the substrate, wherein the buffer portion comprises B₂ gallium nitride and carbon (GaN:C), the drain portion comprises doped gallium nitride (GaN), and the liner comprises aluminum nitride (AlN); a source comprising doped material; and a channel electrically connecting the drain to the source, wherein the liner includes implanted silicon at least at an interface between the channel and the liner.
The semiconductor device of claim 1, further compris-ing: a gate structure formed over the channel, wherein the gate structure is associated with a breakdown field larger than 7×105 Volts per centimeter (V/cm).
The semiconductor device of claim 1, wherein current is to flow from the drain structure to the source through the channel with a current density of at least 5400 milliamperes per millimeter (mA/mm) at 10 Volts.
The semiconductor device of claim 1, wherein the drain portion comprises cubic GaN (c-GaN).
The semiconductor device of claim 1, wherein the buffer portion forms a substantially V-shaped structure.
The semiconductor device of claim 1, wherein the liner has a thickness of no more than 5 nanometers (nm).
A method, comprising: forming an upper recess in a substrate, wherein the upper recess is substantially rectangular; forming a liner comprising aluminum nitride (AlN) on sidewalls of the upper recess; forming a lower recess in the substrate, wherein the lower recess is substantially V-shaped; implanting silicon in the liner at least at an interface between the liner and a portion of the substrate to include a channel; and forming a drain structure comprising doped gallium nitride (GaN) in the lower recess and the upper recess.
The method of claim 7, wherein forming the upper recess comprises: patterning a photoresist material over the substrate; and forming the upper recess in the substrate using lithogra-phy, wherein the photoresist material is removed after the drain structure is formed.
The method of claim 7, wherein forming the liner comprises: depositing AlN on the sidewalls and a bottom surface of the upper recess; and etching the AlN from the bottom surface of the upper recess.
The method of claim 7, further comprising: forming a layer of silicon nitride (SiN) on the sidewalls and a bottom surface of the upper recess; and etching the SiN from the bottom surface of the upper recess.
The method of claim 7, wherein forming the drain structure comprises: forming a buffer portion comprising gallium nitride and carbon (GaN:C) in at least the lower recess; and forming a drain portion comprising doped gallium nitride (n-GaN) in at least the upper recess.
A method, comprising: forming an upper recess in a substrate, wherein the upper recess is substantially rectangular; forming a liner comprising aluminum nitride (AlN) on sidewalls of the upper recess; forming a lower recess in the substrate, wherein the lower recess is substantially V-shaped; forming a buffer portion comprising gallium nitride and carbon (GaN:C) in at least the lower recess; and forming a drain portion comprising doped gallium nitride (n-GaN) in at least the upper recess.
The method of claim 14, wherein forming the lower recess comprises: using tetramethyl ammonium hydroxide (TMAH) to etch the lower recess under the upper recess.
The method of claim 14, wherein forming the buffer portion comprises: depositing gallium nitride and carbon using atomic layer deposition (ALD), wherein the GaN:C is formed in the lower recess and polycrystalline GaN:C (poly-GaN:C) is formed over the substrate; and etching the poly-GaN:C using hydrochloric acid (HCl).
The method of claim 14, further comprising: forming doped silicon on the substrate that has an interface with the liner to form a channel.
The method of claim 14, further comprising: forming a photoresist layer over the substrate, wherein the photoresist layer is used to form the upper recess with lithography; and etching the photoresist layer using a buffered oxide etch (BOE) after forming the drain portion. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
gallium nitride drain transistor
Materials described outside the worked examples.
gallium nitride and carbon
GaN:C
doped gallium nitride
GaN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
gate structure breakdown field | ≥ 700000 V/cm | — |
drain-to-source current density at 10 V | >=5400 mA/mm | — |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 1
Related documents with shared materials, methods, properties, or citations.
aluminum nitride
AlN
implanted silicon
Si
cubic gallium nitride
c-GaN
silicon nitride
SiN
polycrystalline gallium nitride and carbon
poly-GaN:C
| ≤ 5 nm |
AlN |
Thickness | ≤ 5 nm | — |
Thickness | ≥ 1 nm | — |
Thickness | ≥ 5 nm | — |
Thickness | ≥ 45 Å | — |
aluminum nitride
AlN
implanted silicon
Si
cubic gallium nitride
c-GaN
silicon nitride
SiN
polycrystalline gallium nitride and carbon
poly-GaN:C
| ≤ 5 nm |
AlN |
Thickness | ≤ 5 nm | — |
Thickness | ≥ 1 nm | — |
Thickness | ≥ 5 nm | — |
Thickness | ≥ 45 Å | — |
aluminum nitride
AlN
implanted silicon
Si
cubic gallium nitride
c-GaN
silicon nitride
SiN
polycrystalline gallium nitride and carbon
poly-GaN:C
| ≤ 5 nm |
AlN |
Thickness | ≤ 5 nm | — |
Thickness | ≥ 1 nm | — |
Thickness | ≥ 5 nm | — |
Thickness | ≥ 45 Å | — |
aluminum nitride
AlN
implanted silicon
Si
cubic gallium nitride
c-GaN
silicon nitride
SiN
polycrystalline gallium nitride and carbon
poly-GaN:C
| ≤ 5 nm |
AlN |
Thickness | ≤ 5 nm | — |
Thickness | ≥ 1 nm | — |
Thickness | ≥ 5 nm | — |
Thickness | ≥ 45 Å | — |
