SEMICONDUCTOR DEVICE INCLUDING h-BN INSULATING LAYER AND ITS MANUFACTURING METHOD

Kazufumi TANAKA

Patent

Atlas literature

Patent

US 9,607,824

SEMICONDUCTOR DEVICE INCLUDING h-BN INSULATING LAYER AND ITS MANUFACTURING METHOD

Kazufumi TANAKA

Drawings

Patent drawings and their descriptions. Click a drawing to enlarge it.

FIG. 1

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FIG. 16

Claims

Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.

16 independent · 2 dependent

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1. 3
  Dependent← claim 2BNBNh-BNsemiconductor light-emitting device
  [[The]] A semiconductor device as set forth in claim 2, comprising: a support substrate; an insulating layer provided on said support substrate; and a semiconductor element provided on said insulating layer, wherein said insulating layer comprises: a lower insulating layer consisting of amorphous boron nitride provided directly on an upper surface of said support substrate; and an upper insulating layer provided on an entire surface of said lower insulating layer and including amorphous boron nitride and hexagonal system boron nitride particles in said amorphous boron nitride, wherein grooves are provided on a surface of said upper insulating layer, and wherein said grooves are grid-shaped.
2. 4
  Dependent← claim 2BNBNh-BNsemiconductor light-emitting device
  [[The]] A semiconductor device as set forth in claim 2, comprising: a support substrate; an insulating layer provided on said support substrate; and a semiconductor element provided on said insulating layer, wherein said insulating layer comprises: Response to Final Oﬃce Action Page 3 Serial Number: 14/958,644 Attorney Docket: 15570 a lower insulating layer consisting of amorphous boron nitride provided directly on an upper surface of said support substrate; and an upper insulating layer provided on an entire surface of said lower insulating layer and including amorphous boron nitride and hexagonal system boron nitride particles in said amorphous boron nitride, wherein grooves are provided on a surface of said upper insulating layer, and wherein a depth D of said grooves satisﬁes: T/2 < D < 2T/3 where T is a thickness of said upper insulating layer.
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Device structures

Layer stacks claimed or described, ordered top of device to substrate.

semiconductor light-emitting device

AlInGaN (p-type, Mg-doped)p-type semiconductor layer

AlInGaN (active layer)active layer

AlInGaN (n-type, Si-doped)n-type semiconductor layer

BNupper insulating layer

BNlower insulating layer

Sisupport substrate

Materials

Materials described outside the worked examples.

amorphous boron nitride

Lower Insulating Layer

Upper Insulating Layer Matrix

hexagonal boron nitride particles

h-BN

Upper Insulating Layer Filler

Process steps

Additional fabrication and treatment steps described in the patent.

Sputtering

Step 1

Process details

target:hexagonal system boron nitride

layer formed:lower insulating layer (amorphous boron nitride)

sputtering gas:excluding nitrogen gas

Materials:BN

Why these are connected

Related documents with shared materials, methods, properties, or citations.

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