Patent
US 11,296,237Integration of graphene and boron nitride hetero-structure device over semiconductor layer
Archana Venugopal
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 11,296,237Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A microelectronic device, comprising: a graphitic layer including at least one layer of graphene over a semiconductor substrate having a first conductivity type, the graphitic layer having a channel region, a first contact region adjacent to the channel region and a second contact region adjacent to the channel region; a gate over the channel region; a first connection including a first metallic layer touching the graphitic layer in the first contact region; a second connection including a second metallic layer touching the graphitic layer in the second contact region; a first contact field region in the semiconductor substrate under the first contact region of the graphitic layer; a second contact field region in the semiconductor substrate under the second contact region of the graphitic layer,,,,,; and a backgate region having [[a]] the first conductivity type in the semiconductor substrate under the channel region and between the first and second contact field regions at a top surface of the semiconductor substrate, wherein the graphitic layer is isolated from the backgate region, the first contact field region, and the second contact field region, and wherein at least one of the first contact field region and the second contact field region has a second opposite conductivity type. Currently amended
Claims 2-20: Cancelled Canceled
Canceled
An integrated circuit, comprising: first and second contact field regions having a second conductivity type in a semiconductor substrate having an opposite first conductivity type; a backgate region having the first conductivity type within the semiconductor substrate between the first and second contact field regions at a top surface of the semiconductor substrate; an isolation dielectric layer over the backgate region; a graphitic layer over the isolation dielectric layer; a first metallic connection touching the graphitic layer over the first contact field region; a second metallic connection touching the graphitic layer over the second contact field region; and a conductive gate over the graphitic layer and between the metallic connections. Currently amended
The integrated circuit of Claim 21, further comprising a layer of boron nitride between the isolation dielectric layer and the graphitic layer. Previously presented
The integrated circuit of Claim 21, further comprising a layer of boron nitride between the conductive gate and the graphitic layer. Previously presented
The integrated circuit of Claim 21, wherein the backgate region extends from a well region that provides electrical contact to the backgate region from a surface of the semiconductor substrate. Previously presented
The integrated circuit of Claim 21, wherein the graphitic layer comprises one or more layers of graphene. Previously presented
The integrated circuit of Claim 21, wherein the first and second contact field regions and the first and second metallic connections are connected to separate corresponding electrical contacts. Previously presented
Cancelled Canceled
Claims 29-30: Cancelled Canceled
Canceled
A method of forming an integrated circuit, comprising: forming a well having a first conductivity type in a semiconductor substrate having the first conductivity type; forming first and second contact field regions having a second opposite conductivity type in the well, the first and second contact field regions being spaced apart by a backgate region of the well; forming an isolation dielectric layer over the backgate region; forming a graphitic layer over the isolation dielectric layer; forming a first metallic connection to the graphitic layer over the first contact field region and a second metallic connection to the graphitic layer over the second contact field region; and forming a conductive gate over the graphitic layer and between the metallic connections. Previously presented
The method of Claim 31, further comprising forming a layer of boron nitride between the isolation dielectric layer and the graphitic layer. Previously presented
The method of Claim 31, further comprising forming a layer of boron nitride between the conductive gate and the graphitic layer. Previously presented
The method of Claim 31, wherein the backgate region has a first conductivity type and the first and second contact field regions have a second opposite conductivity type. Previously presented
The method of Claim 31, further comprising forming an electrical contact to the well. Previously presented
The method of Claim 31, wherein the graphitic layer comprises one or more layers of graphene. Previously presented
The method of Claim 31, further comprising forming a separate corresponding electrical contact to each of the first and second contact field regions and the first and second metallic connections. Previously presented
The method of Claim 31, further comprising forming a metal oxide semiconductor (MOS) transistor in or over the semiconductor substrate, the MOS transistor having a gate dielectric layer with a thickness and a composition substantially equal to a thickness and a composition of the isolation dielectric layer area. Previously presented
The method of Claim 31, further comprising an forming an NMOS transistor in or over the semiconductor substrate, wherein a dopant distribution of the first and second contact field regions is substantially equal to a dopant distribution of n-type source and drain regions of the NMOS transistor. Previously presented
An integrated circuit, comprising: a gated graphene component including: a backgate region between first and second contact field regions in a semiconductor substrate; an isolation dielectric layer over the backgate region; a graphitic layer over the isolation dielectric layer; a first metallic connection touching the graphitic layer over the first contact field region; a second metallic connection touching the graphitic layer over the second contact field region; and a conductive gate over the graphitic layer and between the metallic connections; and a metal oxide semiconductor (MOS) transistor formed in or over the semiconductor substrate, the MOS transistor having a gate dielectric layer with a thickness and a composition substantially equal to a thickness and a composition of the isolation dielectric layer. Previously presented
The integrated circuit of Claim 41, further comprising a layer of boron nitride between the isolation dielectric layer and the graphitic layer. New
An integrated circuit, comprising: a gated graphene component including: a backgate region between first and second contact field regions in a semiconductor substrate; an isolation dielectric layer over the backgate region; a graphitic layer over the isolation dielectric layer; a first metallic connection touching the graphitic layer over the first contact field region; a second metallic connection touching the graphitic layer over the second contact field region; and a conductive gate over the graphitic layer and between the metallic connections; and an NMOS transistor formed in or over the semiconductor substrate, wherein a dopant distribution of the first and second contact field regions is substantially equal to a dopant distribution of n-type source and drain regions of the NMOS transistor. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
microelectronic device with gated graphene (claim 1)
gated graphene integrated circuit
Materials described outside the worked examples.
graphene/graphitic layer
semiconductor substrate
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,296,237Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A microelectronic device, comprising: a graphitic layer including at least one layer of graphene over a semiconductor substrate having a first conductivity type, the graphitic layer having a channel region, a first contact region adjacent to the channel region and a second contact region adjacent to the channel region; a gate over the channel region; a first connection including a first metallic layer touching the graphitic layer in the first contact region; a second connection including a second metallic layer touching the graphitic layer in the second contact region; a first contact field region in the semiconductor substrate under the first contact region of the graphitic layer; a second contact field region in the semiconductor substrate under the second contact region of the graphitic layer,,,,,; and a backgate region having [[a]] the first conductivity type in the semiconductor substrate under the channel region and between the first and second contact field regions at a top surface of the semiconductor substrate, wherein the graphitic layer is isolated from the backgate region, the first contact field region, and the second contact field region, and wherein at least one of the first contact field region and the second contact field region has a second opposite conductivity type. Currently amended
Claims 2-20: Cancelled Canceled
Canceled
An integrated circuit, comprising: first and second contact field regions having a second conductivity type in a semiconductor substrate having an opposite first conductivity type; a backgate region having the first conductivity type within the semiconductor substrate between the first and second contact field regions at a top surface of the semiconductor substrate; an isolation dielectric layer over the backgate region; a graphitic layer over the isolation dielectric layer; a first metallic connection touching the graphitic layer over the first contact field region; a second metallic connection touching the graphitic layer over the second contact field region; and a conductive gate over the graphitic layer and between the metallic connections. Currently amended
The integrated circuit of Claim 21, further comprising a layer of boron nitride between the isolation dielectric layer and the graphitic layer. Previously presented
The integrated circuit of Claim 21, further comprising a layer of boron nitride between the conductive gate and the graphitic layer. Previously presented
The integrated circuit of Claim 21, wherein the backgate region extends from a well region that provides electrical contact to the backgate region from a surface of the semiconductor substrate. Previously presented
The integrated circuit of Claim 21, wherein the graphitic layer comprises one or more layers of graphene. Previously presented
The integrated circuit of Claim 21, wherein the first and second contact field regions and the first and second metallic connections are connected to separate corresponding electrical contacts. Previously presented
Cancelled Canceled
Claims 29-30: Cancelled Canceled
Canceled
A method of forming an integrated circuit, comprising: forming a well having a first conductivity type in a semiconductor substrate having the first conductivity type; forming first and second contact field regions having a second opposite conductivity type in the well, the first and second contact field regions being spaced apart by a backgate region of the well; forming an isolation dielectric layer over the backgate region; forming a graphitic layer over the isolation dielectric layer; forming a first metallic connection to the graphitic layer over the first contact field region and a second metallic connection to the graphitic layer over the second contact field region; and forming a conductive gate over the graphitic layer and between the metallic connections. Previously presented
The method of Claim 31, further comprising forming a layer of boron nitride between the isolation dielectric layer and the graphitic layer. Previously presented
The method of Claim 31, further comprising forming a layer of boron nitride between the conductive gate and the graphitic layer. Previously presented
The method of Claim 31, wherein the backgate region has a first conductivity type and the first and second contact field regions have a second opposite conductivity type. Previously presented
The method of Claim 31, further comprising forming an electrical contact to the well. Previously presented
The method of Claim 31, wherein the graphitic layer comprises one or more layers of graphene. Previously presented
The method of Claim 31, further comprising forming a separate corresponding electrical contact to each of the first and second contact field regions and the first and second metallic connections. Previously presented
The method of Claim 31, further comprising forming a metal oxide semiconductor (MOS) transistor in or over the semiconductor substrate, the MOS transistor having a gate dielectric layer with a thickness and a composition substantially equal to a thickness and a composition of the isolation dielectric layer area. Previously presented
The method of Claim 31, further comprising an forming an NMOS transistor in or over the semiconductor substrate, wherein a dopant distribution of the first and second contact field regions is substantially equal to a dopant distribution of n-type source and drain regions of the NMOS transistor. Previously presented
An integrated circuit, comprising: a gated graphene component including: a backgate region between first and second contact field regions in a semiconductor substrate; an isolation dielectric layer over the backgate region; a graphitic layer over the isolation dielectric layer; a first metallic connection touching the graphitic layer over the first contact field region; a second metallic connection touching the graphitic layer over the second contact field region; and a conductive gate over the graphitic layer and between the metallic connections; and a metal oxide semiconductor (MOS) transistor formed in or over the semiconductor substrate, the MOS transistor having a gate dielectric layer with a thickness and a composition substantially equal to a thickness and a composition of the isolation dielectric layer. Previously presented
The integrated circuit of Claim 41, further comprising a layer of boron nitride between the isolation dielectric layer and the graphitic layer. New
An integrated circuit, comprising: a gated graphene component including: a backgate region between first and second contact field regions in a semiconductor substrate; an isolation dielectric layer over the backgate region; a graphitic layer over the isolation dielectric layer; a first metallic connection touching the graphitic layer over the first contact field region; a second metallic connection touching the graphitic layer over the second contact field region; and a conductive gate over the graphitic layer and between the metallic connections; and an NMOS transistor formed in or over the semiconductor substrate, wherein a dopant distribution of the first and second contact field regions is substantially equal to a dopant distribution of n-type source and drain regions of the NMOS transistor. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
microelectronic device with gated graphene (claim 1)
gated graphene integrated circuit
Materials described outside the worked examples.
graphene/graphitic layer
semiconductor substrate
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,296,237Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A microelectronic device, comprising: a graphitic layer including at least one layer of graphene over a semiconductor substrate having a first conductivity type, the graphitic layer having a channel region, a first contact region adjacent to the channel region and a second contact region adjacent to the channel region; a gate over the channel region; a first connection including a first metallic layer touching the graphitic layer in the first contact region; a second connection including a second metallic layer touching the graphitic layer in the second contact region; a first contact field region in the semiconductor substrate under the first contact region of the graphitic layer; a second contact field region in the semiconductor substrate under the second contact region of the graphitic layer,,,,,; and a backgate region having [[a]] the first conductivity type in the semiconductor substrate under the channel region and between the first and second contact field regions at a top surface of the semiconductor substrate, wherein the graphitic layer is isolated from the backgate region, the first contact field region, and the second contact field region, and wherein at least one of the first contact field region and the second contact field region has a second opposite conductivity type. Currently amended
Claims 2-20: Cancelled Canceled
Canceled
An integrated circuit, comprising: first and second contact field regions having a second conductivity type in a semiconductor substrate having an opposite first conductivity type; a backgate region having the first conductivity type within the semiconductor substrate between the first and second contact field regions at a top surface of the semiconductor substrate; an isolation dielectric layer over the backgate region; a graphitic layer over the isolation dielectric layer; a first metallic connection touching the graphitic layer over the first contact field region; a second metallic connection touching the graphitic layer over the second contact field region; and a conductive gate over the graphitic layer and between the metallic connections. Currently amended
The integrated circuit of Claim 21, further comprising a layer of boron nitride between the isolation dielectric layer and the graphitic layer. Previously presented
The integrated circuit of Claim 21, further comprising a layer of boron nitride between the conductive gate and the graphitic layer. Previously presented
The integrated circuit of Claim 21, wherein the backgate region extends from a well region that provides electrical contact to the backgate region from a surface of the semiconductor substrate. Previously presented
The integrated circuit of Claim 21, wherein the graphitic layer comprises one or more layers of graphene. Previously presented
The integrated circuit of Claim 21, wherein the first and second contact field regions and the first and second metallic connections are connected to separate corresponding electrical contacts. Previously presented
Cancelled Canceled
Claims 29-30: Cancelled Canceled
Canceled
A method of forming an integrated circuit, comprising: forming a well having a first conductivity type in a semiconductor substrate having the first conductivity type; forming first and second contact field regions having a second opposite conductivity type in the well, the first and second contact field regions being spaced apart by a backgate region of the well; forming an isolation dielectric layer over the backgate region; forming a graphitic layer over the isolation dielectric layer; forming a first metallic connection to the graphitic layer over the first contact field region and a second metallic connection to the graphitic layer over the second contact field region; and forming a conductive gate over the graphitic layer and between the metallic connections. Previously presented
The method of Claim 31, further comprising forming a layer of boron nitride between the isolation dielectric layer and the graphitic layer. Previously presented
The method of Claim 31, further comprising forming a layer of boron nitride between the conductive gate and the graphitic layer. Previously presented
The method of Claim 31, wherein the backgate region has a first conductivity type and the first and second contact field regions have a second opposite conductivity type. Previously presented
The method of Claim 31, further comprising forming an electrical contact to the well. Previously presented
The method of Claim 31, wherein the graphitic layer comprises one or more layers of graphene. Previously presented
The method of Claim 31, further comprising forming a separate corresponding electrical contact to each of the first and second contact field regions and the first and second metallic connections. Previously presented
The method of Claim 31, further comprising forming a metal oxide semiconductor (MOS) transistor in or over the semiconductor substrate, the MOS transistor having a gate dielectric layer with a thickness and a composition substantially equal to a thickness and a composition of the isolation dielectric layer area. Previously presented
The method of Claim 31, further comprising an forming an NMOS transistor in or over the semiconductor substrate, wherein a dopant distribution of the first and second contact field regions is substantially equal to a dopant distribution of n-type source and drain regions of the NMOS transistor. Previously presented
An integrated circuit, comprising: a gated graphene component including: a backgate region between first and second contact field regions in a semiconductor substrate; an isolation dielectric layer over the backgate region; a graphitic layer over the isolation dielectric layer; a first metallic connection touching the graphitic layer over the first contact field region; a second metallic connection touching the graphitic layer over the second contact field region; and a conductive gate over the graphitic layer and between the metallic connections; and a metal oxide semiconductor (MOS) transistor formed in or over the semiconductor substrate, the MOS transistor having a gate dielectric layer with a thickness and a composition substantially equal to a thickness and a composition of the isolation dielectric layer. Previously presented
The integrated circuit of Claim 41, further comprising a layer of boron nitride between the isolation dielectric layer and the graphitic layer. New
An integrated circuit, comprising: a gated graphene component including: a backgate region between first and second contact field regions in a semiconductor substrate; an isolation dielectric layer over the backgate region; a graphitic layer over the isolation dielectric layer; a first metallic connection touching the graphitic layer over the first contact field region; a second metallic connection touching the graphitic layer over the second contact field region; and a conductive gate over the graphitic layer and between the metallic connections; and an NMOS transistor formed in or over the semiconductor substrate, wherein a dopant distribution of the first and second contact field regions is substantially equal to a dopant distribution of n-type source and drain regions of the NMOS transistor. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
microelectronic device with gated graphene (claim 1)
gated graphene integrated circuit
Materials described outside the worked examples.
graphene/graphitic layer
semiconductor substrate
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,296,237Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A microelectronic device, comprising: a graphitic layer including at least one layer of graphene over a semiconductor substrate having a first conductivity type, the graphitic layer having a channel region, a first contact region adjacent to the channel region and a second contact region adjacent to the channel region; a gate over the channel region; a first connection including a first metallic layer touching the graphitic layer in the first contact region; a second connection including a second metallic layer touching the graphitic layer in the second contact region; a first contact field region in the semiconductor substrate under the first contact region of the graphitic layer; a second contact field region in the semiconductor substrate under the second contact region of the graphitic layer,,,,,; and a backgate region having [[a]] the first conductivity type in the semiconductor substrate under the channel region and between the first and second contact field regions at a top surface of the semiconductor substrate, wherein the graphitic layer is isolated from the backgate region, the first contact field region, and the second contact field region, and wherein at least one of the first contact field region and the second contact field region has a second opposite conductivity type. Currently amended
Claims 2-20: Cancelled Canceled
Canceled
An integrated circuit, comprising: first and second contact field regions having a second conductivity type in a semiconductor substrate having an opposite first conductivity type; a backgate region having the first conductivity type within the semiconductor substrate between the first and second contact field regions at a top surface of the semiconductor substrate; an isolation dielectric layer over the backgate region; a graphitic layer over the isolation dielectric layer; a first metallic connection touching the graphitic layer over the first contact field region; a second metallic connection touching the graphitic layer over the second contact field region; and a conductive gate over the graphitic layer and between the metallic connections. Currently amended
The integrated circuit of Claim 21, further comprising a layer of boron nitride between the isolation dielectric layer and the graphitic layer. Previously presented
The integrated circuit of Claim 21, further comprising a layer of boron nitride between the conductive gate and the graphitic layer. Previously presented
The integrated circuit of Claim 21, wherein the backgate region extends from a well region that provides electrical contact to the backgate region from a surface of the semiconductor substrate. Previously presented
The integrated circuit of Claim 21, wherein the graphitic layer comprises one or more layers of graphene. Previously presented
The integrated circuit of Claim 21, wherein the first and second contact field regions and the first and second metallic connections are connected to separate corresponding electrical contacts. Previously presented
Cancelled Canceled
Claims 29-30: Cancelled Canceled
Canceled
A method of forming an integrated circuit, comprising: forming a well having a first conductivity type in a semiconductor substrate having the first conductivity type; forming first and second contact field regions having a second opposite conductivity type in the well, the first and second contact field regions being spaced apart by a backgate region of the well; forming an isolation dielectric layer over the backgate region; forming a graphitic layer over the isolation dielectric layer; forming a first metallic connection to the graphitic layer over the first contact field region and a second metallic connection to the graphitic layer over the second contact field region; and forming a conductive gate over the graphitic layer and between the metallic connections. Previously presented
The method of Claim 31, further comprising forming a layer of boron nitride between the isolation dielectric layer and the graphitic layer. Previously presented
The method of Claim 31, further comprising forming a layer of boron nitride between the conductive gate and the graphitic layer. Previously presented
The method of Claim 31, wherein the backgate region has a first conductivity type and the first and second contact field regions have a second opposite conductivity type. Previously presented
The method of Claim 31, further comprising forming an electrical contact to the well. Previously presented
The method of Claim 31, wherein the graphitic layer comprises one or more layers of graphene. Previously presented
The method of Claim 31, further comprising forming a separate corresponding electrical contact to each of the first and second contact field regions and the first and second metallic connections. Previously presented
The method of Claim 31, further comprising forming a metal oxide semiconductor (MOS) transistor in or over the semiconductor substrate, the MOS transistor having a gate dielectric layer with a thickness and a composition substantially equal to a thickness and a composition of the isolation dielectric layer area. Previously presented
The method of Claim 31, further comprising an forming an NMOS transistor in or over the semiconductor substrate, wherein a dopant distribution of the first and second contact field regions is substantially equal to a dopant distribution of n-type source and drain regions of the NMOS transistor. Previously presented
An integrated circuit, comprising: a gated graphene component including: a backgate region between first and second contact field regions in a semiconductor substrate; an isolation dielectric layer over the backgate region; a graphitic layer over the isolation dielectric layer; a first metallic connection touching the graphitic layer over the first contact field region; a second metallic connection touching the graphitic layer over the second contact field region; and a conductive gate over the graphitic layer and between the metallic connections; and a metal oxide semiconductor (MOS) transistor formed in or over the semiconductor substrate, the MOS transistor having a gate dielectric layer with a thickness and a composition substantially equal to a thickness and a composition of the isolation dielectric layer. Previously presented
The integrated circuit of Claim 41, further comprising a layer of boron nitride between the isolation dielectric layer and the graphitic layer. New
An integrated circuit, comprising: a gated graphene component including: a backgate region between first and second contact field regions in a semiconductor substrate; an isolation dielectric layer over the backgate region; a graphitic layer over the isolation dielectric layer; a first metallic connection touching the graphitic layer over the first contact field region; a second metallic connection touching the graphitic layer over the second contact field region; and a conductive gate over the graphitic layer and between the metallic connections; and an NMOS transistor formed in or over the semiconductor substrate, wherein a dopant distribution of the first and second contact field regions is substantially equal to a dopant distribution of n-type source and drain regions of the NMOS transistor. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
microelectronic device with gated graphene (claim 1)
gated graphene integrated circuit
Materials described outside the worked examples.
graphene/graphitic layer
semiconductor substrate
Related documents with shared materials, methods, properties, or citations.
MOS transistor co-integrated with gated graphene component
No layer stack recorded.
NMOS transistor co-integrated with gated graphene component
No layer stack recorded.
isolation dielectric layer
boron nitride
BN
MOS transistor co-integrated with gated graphene component
No layer stack recorded.
NMOS transistor co-integrated with gated graphene component
No layer stack recorded.
isolation dielectric layer
boron nitride
BN
MOS transistor co-integrated with gated graphene component
No layer stack recorded.
NMOS transistor co-integrated with gated graphene component
No layer stack recorded.
isolation dielectric layer
boron nitride
BN
MOS transistor co-integrated with gated graphene component
No layer stack recorded.
NMOS transistor co-integrated with gated graphene component
No layer stack recorded.
isolation dielectric layer
boron nitride
BN