Patent
Atlas literature
Patent
US 12,520,513 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified cross-sectional view illustrating a semiconductor device according to an embodiment of the present disclosure;
FIGS. 2A-2D are simplified cross-sectional views illus- trating the fabrication of a semiconductor device including a plurality of semiconductor fins surrounding …
FIG. 3 is a simplified cross-sectional view illustrating variations of the regrown gates along sidewalls of the semiconductor fins;
FIGS. 4A-4G show results of regrowth profiles on respec- tive 200 nm, 400 nm, 500 nm, 550 nm, 600 nm, 650 nm, and 800 nm regrowth wafers according to an …
FIG. 5 is a plan view of a fin pattern layout for explaining the terms that are used in the present disclosure;
FIG. 6 is a plan view of a fin pattern layout illustrating semiconductor fins having shorter lengths according to an embodiment of the present disclosure;
FIG. 7B shows growth thickness variations on an 800 nm regrowth wafer according to an embodiment of the present disclosure;
FIG. 8B shows growth thickness variations on an 800 nm regrowth wafer based on FIB data according to an embodi- 5 ment of the present disclosure;
FIGS. 9A-9D are Nomarski-contrast micrograph images illustrating the effect of different fin lengths of an 800 nm regrowth wafer according to an embodiment of …
FIGS. 10A and 10B are high-resolution Nomarski-con- trast micrograph images illustrating the effect of different fin lengths for a 25 µm fin and a 1000 µm fin on …
FIGS. 11A-11D are Nomarski-contrast micrograph images illustrating and the variation (standard deviation sigma, range) of 25 µm, 50 µm, 100 µm, and 1000 µm fin …
FIG. 12 is an oblique view SEM image of a 0.3 µm×25 µm (width×length) fin array with a 2 µm pitch on a 500 nm regrowth wafer according to an embodiment of the …
FIG. 13 is a plan view of a fin pattern layout illustrating semiconductor fins having short lengths according to an embodiment of the present disclosure;
FIG. 14 is a plan view of a fin pattern layout illustrating semiconductor fins having short lengths according to 30 another embodiment of the present disclosure;
FIG. 15 is a plan view of a fin pattern layout illustrating semiconductor fins having short lengths according to yet another embodiment of the present …
FIG. 16 is a simplified flowchart illustrating a method of 35 fabricating a semiconductor device having a fin array according to an embodiment of the present …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of fabricating a semiconductor device, the method comprising: providing a substrate structure comprising a semiconduc-tor substrate of a first conductivity type, a drift layer on the semiconductor substrate, and a fin array on the drift layer and surrounded by a recess region, wherein the fin array comprises a first row of fins and a second row of fins parallel to each other and separated from each other by a space, the first row of fins comprising a plurality of first elongated fins extending parallel to each other in a first direction and arranged with a first distance between each other, and the second row of fins com-prising a plurality of second elongated fins extending parallel to each other in a second direction parallel to the first direction and arranged with a second distance between each other; and epitaxially regrowing a gate layer of a second conductiv-ity type opposite the first conductivity type on the drift layer and filling the recess region, the gate layer sur-rounding the first row of fins and the second row of fins; wherein: the second distance is equal to the first distance and the space between the first row of fins and the second row of fins is equal to the first distance to improve uniformity of the gate layer the gate layer and to reduce channel length variation; and the plurality of first elongated fins and the plurality of 30 second elongated fins are configured to provide a vertical conducting channel for the semiconductor device.
The method of claim 1, further comprising: forming a plurality of source contacts, each coupled to an upper surface of each fin of the fin array; forming one or more gate contacts on the gate layer; and forming a drain contact coupled to the semiconductor substrate.
The method of claim 1, wherein providing the substrate structure comprises: providing the semiconductor substrate; epitaxially growing the drift layer on the semiconductor substrate; epitaxially growing a semiconductor layer having the first conductivity type on the drift layer; forming a metal layer on the semiconductor layer; forming a patterned hard mask layer on the metal layer; and etching the metal layer and the semiconductor layer using the patterned hard mask layer as a mask to form the fin array and the recess region surrounding the fin array.
The method of claim 1, wherein the gate layer has an upper surface substantially flush with an upper surface of the fin array.
The method of claim 1, wherein the plurality of first elongated fins and the plurality of second elongated fins are offset from each other by an amount equal to the space.
The method of claim 1, wherein the method further comprises forming a metal layer on the gate layer.
The method of claim 1, wherein the plurality of first elongated fins and the plurality of second elongated fins have equal length.
The method of claim 1, wherein the plurality of first elongated fins and the plurality of second elongated fins are arranged in a plurality of columns, a first portion of the plurality of first elongated fins and a first portion of the B₂ plurality of second elongated fins in a first column having a length different than a length of a second portion of the plurality of first elongated fins and a second portion of the plurality of second elongated fins in a second column adjacent to the first column.
The method of claim 1, wherein a first portion of the plurality of first elongated fins and a first portion of the plurality of second elongated fins disposed in a center region of the semiconductor device has a length greater than a second portion of the plurality of first elongated fins and a second portion of the plurality of second elongated fins disposed in an edge region.
The method of claim 1, wherein a first portion of the plurality of first elongated fins and a first portion of the plurality of second elongated fins disposed in a center region of the semiconductor device has a length smaller than a second portion of the plurality of first elongated fins and a second portion of the plurality of second elongated fins disposed in an edge region.
The method of claim 1, wherein each of the first distance and the second distance is non-uniform, varying from a small distance in an edge region of the semiconductor substrate to a large distance in a center region of the semiconductor substrate.
The method of claim 1, wherein: a ratio between a fin width and a pitch between two adjacent fins is in a range between about 0.08 and 0.13; and a ratio between a fin length and the pitch between two adjacent fins is in a range between 5 and 25.
The method of claim 1, wherein a ratio between a fin length and a fin width is >50:1.
The method of claim 1, wherein each fin in the first row of fins and the second row of fins has a length in a range between 10 µm and 60 µm, and a width in a range between 0.15 µm and 0.7 µm.
A method of fabricating a semiconductor device, comprising: providing a substrate structure comprising: a semiconductor substrate having a first conductivity type; a drift layer of the first conductivity type coupled to the semiconductor substrate; a fin array comprising a plurality of rows of fins on the drift layer, the plurality of rows of fins including a first row of fins and a second row of fins; and a space between the first row of fins and the second row of fins; and providing a gate layer of a second conductivity type opposite the first conductivity type on the drift layer; wherein: the first row of fins comprising a plurality of first elongated fins arranged in parallel to each other along a first row direction and separated by a first distance, and the second row of fins comprising a plurality of second elongated fins arranged in parallel to each other along a second row direction and separated by a second distance, wherein each of the first distance and the second distance is non-uniform varying from a small distance in an edge region of the semiconductor substrate to a large distance in a center region of the semiconductor substrate to improve uniformity of the gate layer and to reduce channel length variation; the gate layer is adjacent to each of the plurality of first elongated fins and each of the plurality of second elongated fins; and the plurality of first elongated fins and the plurality of second elongated fins are configured to provide a vertical conducting channel for the semiconductor device.
The method of claim 15, wherein the plurality of first elongated fins and the plurality of second elongated fins are offset from each other by an amount equal to the space.
The method of claim 15, wherein the plurality of first elongated fins and the plurality of second elongated fins are arranged in a plurality of columns, a first portion of the plurality of first elongated fins and a first portion of the plurality of second elongated fins in a first column having a length different than a length of a second portion of the plurality of first elongated fins and a second portion of the plurality of second elongated fins in a second column adjacent to the first column.
A method of fabricating a semiconductor device, the method comprising: providing a substrate structure comprising: a semiconductor substrate of a first conductivity type, 20 a drift layer coupled to the semiconductor substrate, and a fin array coupled to the drift layer and surrounded by a recess region, wherein: the fin array comprises a first row of fins and a second row of fins parallel to each other and separated from each other by a space; the first row of fins comprising a plurality of first elongated fins extending parallel to each other in a first direction and arranged with a first distance between each other; the second row of fins comprising a plurality of second elongated fins extending parallel to each other in a second direction parallel to the first direction; and the plurality of first elongated fins and the plurality of second elongated fins are arranged in a plurality of columns; and providing a gate layer of a second conductivity type opposite to the first conductivity type adjacent to each fin in the first row of fins and the second row of fins; wherein: a first portion of the plurality of first elongated fins and a first portion of the plurality of second elongated fins in a first column comprise a length different than a length of a second portion of the plurality of first elongated fins and a second portion of the plurality of second elongated fins in a second column adjacent to the first column to improve uniformity of the gate layer and to reduce channel length variation; and the plurality of first elongated fins and the plurality of second elongated fins are configured to provide a vertical conducting channel for the semiconductor device. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
vertical fin-based FET (FinFET) semiconductor device
Materials described outside the worked examples.
semiconductor substrate (first conductivity type)
gate layer (second conductivity type, epitaxially regrown)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 7B shows growth thickness variations on an 800 nm regrowth wafer according to an embodiment of the present disclosure;
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 550–650 nm | — |
Thickness |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 12
Related documents with shared materials, methods, properties, or citations.
Patent
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US 12,520,513 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified cross-sectional view illustrating a semiconductor device according to an embodiment of the present disclosure;
FIGS. 2A-2D are simplified cross-sectional views illus- trating the fabrication of a semiconductor device including a plurality of semiconductor fins surrounding …
FIG. 3 is a simplified cross-sectional view illustrating variations of the regrown gates along sidewalls of the semiconductor fins;
FIGS. 4A-4G show results of regrowth profiles on respec- tive 200 nm, 400 nm, 500 nm, 550 nm, 600 nm, 650 nm, and 800 nm regrowth wafers according to an …
FIG. 5 is a plan view of a fin pattern layout for explaining the terms that are used in the present disclosure;
FIG. 6 is a plan view of a fin pattern layout illustrating semiconductor fins having shorter lengths according to an embodiment of the present disclosure;
FIG. 7B shows growth thickness variations on an 800 nm regrowth wafer according to an embodiment of the present disclosure;
FIG. 8B shows growth thickness variations on an 800 nm regrowth wafer based on FIB data according to an embodi- 5 ment of the present disclosure;
FIGS. 9A-9D are Nomarski-contrast micrograph images illustrating the effect of different fin lengths of an 800 nm regrowth wafer according to an embodiment of …
FIGS. 10A and 10B are high-resolution Nomarski-con- trast micrograph images illustrating the effect of different fin lengths for a 25 µm fin and a 1000 µm fin on …
FIGS. 11A-11D are Nomarski-contrast micrograph images illustrating and the variation (standard deviation sigma, range) of 25 µm, 50 µm, 100 µm, and 1000 µm fin …
FIG. 12 is an oblique view SEM image of a 0.3 µm×25 µm (width×length) fin array with a 2 µm pitch on a 500 nm regrowth wafer according to an embodiment of the …
FIG. 13 is a plan view of a fin pattern layout illustrating semiconductor fins having short lengths according to an embodiment of the present disclosure;
FIG. 14 is a plan view of a fin pattern layout illustrating semiconductor fins having short lengths according to 30 another embodiment of the present disclosure;
FIG. 15 is a plan view of a fin pattern layout illustrating semiconductor fins having short lengths according to yet another embodiment of the present …
FIG. 16 is a simplified flowchart illustrating a method of 35 fabricating a semiconductor device having a fin array according to an embodiment of the present …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of fabricating a semiconductor device, the method comprising: providing a substrate structure comprising a semiconduc-tor substrate of a first conductivity type, a drift layer on the semiconductor substrate, and a fin array on the drift layer and surrounded by a recess region, wherein the fin array comprises a first row of fins and a second row of fins parallel to each other and separated from each other by a space, the first row of fins comprising a plurality of first elongated fins extending parallel to each other in a first direction and arranged with a first distance between each other, and the second row of fins com-prising a plurality of second elongated fins extending parallel to each other in a second direction parallel to the first direction and arranged with a second distance between each other; and epitaxially regrowing a gate layer of a second conductiv-ity type opposite the first conductivity type on the drift layer and filling the recess region, the gate layer sur-rounding the first row of fins and the second row of fins; wherein: the second distance is equal to the first distance and the space between the first row of fins and the second row of fins is equal to the first distance to improve uniformity of the gate layer the gate layer and to reduce channel length variation; and the plurality of first elongated fins and the plurality of 30 second elongated fins are configured to provide a vertical conducting channel for the semiconductor device.
The method of claim 1, further comprising: forming a plurality of source contacts, each coupled to an upper surface of each fin of the fin array; forming one or more gate contacts on the gate layer; and forming a drain contact coupled to the semiconductor substrate.
The method of claim 1, wherein providing the substrate structure comprises: providing the semiconductor substrate; epitaxially growing the drift layer on the semiconductor substrate; epitaxially growing a semiconductor layer having the first conductivity type on the drift layer; forming a metal layer on the semiconductor layer; forming a patterned hard mask layer on the metal layer; and etching the metal layer and the semiconductor layer using the patterned hard mask layer as a mask to form the fin array and the recess region surrounding the fin array.
The method of claim 1, wherein the gate layer has an upper surface substantially flush with an upper surface of the fin array.
The method of claim 1, wherein the plurality of first elongated fins and the plurality of second elongated fins are offset from each other by an amount equal to the space.
The method of claim 1, wherein the method further comprises forming a metal layer on the gate layer.
The method of claim 1, wherein the plurality of first elongated fins and the plurality of second elongated fins have equal length.
The method of claim 1, wherein the plurality of first elongated fins and the plurality of second elongated fins are arranged in a plurality of columns, a first portion of the plurality of first elongated fins and a first portion of the B₂ plurality of second elongated fins in a first column having a length different than a length of a second portion of the plurality of first elongated fins and a second portion of the plurality of second elongated fins in a second column adjacent to the first column.
The method of claim 1, wherein a first portion of the plurality of first elongated fins and a first portion of the plurality of second elongated fins disposed in a center region of the semiconductor device has a length greater than a second portion of the plurality of first elongated fins and a second portion of the plurality of second elongated fins disposed in an edge region.
The method of claim 1, wherein a first portion of the plurality of first elongated fins and a first portion of the plurality of second elongated fins disposed in a center region of the semiconductor device has a length smaller than a second portion of the plurality of first elongated fins and a second portion of the plurality of second elongated fins disposed in an edge region.
The method of claim 1, wherein each of the first distance and the second distance is non-uniform, varying from a small distance in an edge region of the semiconductor substrate to a large distance in a center region of the semiconductor substrate.
The method of claim 1, wherein: a ratio between a fin width and a pitch between two adjacent fins is in a range between about 0.08 and 0.13; and a ratio between a fin length and the pitch between two adjacent fins is in a range between 5 and 25.
The method of claim 1, wherein a ratio between a fin length and a fin width is >50:1.
The method of claim 1, wherein each fin in the first row of fins and the second row of fins has a length in a range between 10 µm and 60 µm, and a width in a range between 0.15 µm and 0.7 µm.
A method of fabricating a semiconductor device, comprising: providing a substrate structure comprising: a semiconductor substrate having a first conductivity type; a drift layer of the first conductivity type coupled to the semiconductor substrate; a fin array comprising a plurality of rows of fins on the drift layer, the plurality of rows of fins including a first row of fins and a second row of fins; and a space between the first row of fins and the second row of fins; and providing a gate layer of a second conductivity type opposite the first conductivity type on the drift layer; wherein: the first row of fins comprising a plurality of first elongated fins arranged in parallel to each other along a first row direction and separated by a first distance, and the second row of fins comprising a plurality of second elongated fins arranged in parallel to each other along a second row direction and separated by a second distance, wherein each of the first distance and the second distance is non-uniform varying from a small distance in an edge region of the semiconductor substrate to a large distance in a center region of the semiconductor substrate to improve uniformity of the gate layer and to reduce channel length variation; the gate layer is adjacent to each of the plurality of first elongated fins and each of the plurality of second elongated fins; and the plurality of first elongated fins and the plurality of second elongated fins are configured to provide a vertical conducting channel for the semiconductor device.
The method of claim 15, wherein the plurality of first elongated fins and the plurality of second elongated fins are offset from each other by an amount equal to the space.
The method of claim 15, wherein the plurality of first elongated fins and the plurality of second elongated fins are arranged in a plurality of columns, a first portion of the plurality of first elongated fins and a first portion of the plurality of second elongated fins in a first column having a length different than a length of a second portion of the plurality of first elongated fins and a second portion of the plurality of second elongated fins in a second column adjacent to the first column.
A method of fabricating a semiconductor device, the method comprising: providing a substrate structure comprising: a semiconductor substrate of a first conductivity type, 20 a drift layer coupled to the semiconductor substrate, and a fin array coupled to the drift layer and surrounded by a recess region, wherein: the fin array comprises a first row of fins and a second row of fins parallel to each other and separated from each other by a space; the first row of fins comprising a plurality of first elongated fins extending parallel to each other in a first direction and arranged with a first distance between each other; the second row of fins comprising a plurality of second elongated fins extending parallel to each other in a second direction parallel to the first direction; and the plurality of first elongated fins and the plurality of second elongated fins are arranged in a plurality of columns; and providing a gate layer of a second conductivity type opposite to the first conductivity type adjacent to each fin in the first row of fins and the second row of fins; wherein: a first portion of the plurality of first elongated fins and a first portion of the plurality of second elongated fins in a first column comprise a length different than a length of a second portion of the plurality of first elongated fins and a second portion of the plurality of second elongated fins in a second column adjacent to the first column to improve uniformity of the gate layer and to reduce channel length variation; and the plurality of first elongated fins and the plurality of second elongated fins are configured to provide a vertical conducting channel for the semiconductor device. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
vertical fin-based FET (FinFET) semiconductor device
Materials described outside the worked examples.
semiconductor substrate (first conductivity type)
gate layer (second conductivity type, epitaxially regrown)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 7B shows growth thickness variations on an 800 nm regrowth wafer according to an embodiment of the present disclosure;
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 550–650 nm | — |
Thickness |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 12
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
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US 12,520,513 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified cross-sectional view illustrating a semiconductor device according to an embodiment of the present disclosure;
FIGS. 2A-2D are simplified cross-sectional views illus- trating the fabrication of a semiconductor device including a plurality of semiconductor fins surrounding …
FIG. 3 is a simplified cross-sectional view illustrating variations of the regrown gates along sidewalls of the semiconductor fins;
FIGS. 4A-4G show results of regrowth profiles on respec- tive 200 nm, 400 nm, 500 nm, 550 nm, 600 nm, 650 nm, and 800 nm regrowth wafers according to an …
FIG. 5 is a plan view of a fin pattern layout for explaining the terms that are used in the present disclosure;
FIG. 6 is a plan view of a fin pattern layout illustrating semiconductor fins having shorter lengths according to an embodiment of the present disclosure;
FIG. 7B shows growth thickness variations on an 800 nm regrowth wafer according to an embodiment of the present disclosure;
FIG. 8B shows growth thickness variations on an 800 nm regrowth wafer based on FIB data according to an embodi- 5 ment of the present disclosure;
FIGS. 9A-9D are Nomarski-contrast micrograph images illustrating the effect of different fin lengths of an 800 nm regrowth wafer according to an embodiment of …
FIGS. 10A and 10B are high-resolution Nomarski-con- trast micrograph images illustrating the effect of different fin lengths for a 25 µm fin and a 1000 µm fin on …
FIGS. 11A-11D are Nomarski-contrast micrograph images illustrating and the variation (standard deviation sigma, range) of 25 µm, 50 µm, 100 µm, and 1000 µm fin …
FIG. 12 is an oblique view SEM image of a 0.3 µm×25 µm (width×length) fin array with a 2 µm pitch on a 500 nm regrowth wafer according to an embodiment of the …
FIG. 13 is a plan view of a fin pattern layout illustrating semiconductor fins having short lengths according to an embodiment of the present disclosure;
FIG. 14 is a plan view of a fin pattern layout illustrating semiconductor fins having short lengths according to 30 another embodiment of the present disclosure;
FIG. 15 is a plan view of a fin pattern layout illustrating semiconductor fins having short lengths according to yet another embodiment of the present …
FIG. 16 is a simplified flowchart illustrating a method of 35 fabricating a semiconductor device having a fin array according to an embodiment of the present …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of fabricating a semiconductor device, the method comprising: providing a substrate structure comprising a semiconduc-tor substrate of a first conductivity type, a drift layer on the semiconductor substrate, and a fin array on the drift layer and surrounded by a recess region, wherein the fin array comprises a first row of fins and a second row of fins parallel to each other and separated from each other by a space, the first row of fins comprising a plurality of first elongated fins extending parallel to each other in a first direction and arranged with a first distance between each other, and the second row of fins com-prising a plurality of second elongated fins extending parallel to each other in a second direction parallel to the first direction and arranged with a second distance between each other; and epitaxially regrowing a gate layer of a second conductiv-ity type opposite the first conductivity type on the drift layer and filling the recess region, the gate layer sur-rounding the first row of fins and the second row of fins; wherein: the second distance is equal to the first distance and the space between the first row of fins and the second row of fins is equal to the first distance to improve uniformity of the gate layer the gate layer and to reduce channel length variation; and the plurality of first elongated fins and the plurality of 30 second elongated fins are configured to provide a vertical conducting channel for the semiconductor device.
The method of claim 1, further comprising: forming a plurality of source contacts, each coupled to an upper surface of each fin of the fin array; forming one or more gate contacts on the gate layer; and forming a drain contact coupled to the semiconductor substrate.
The method of claim 1, wherein providing the substrate structure comprises: providing the semiconductor substrate; epitaxially growing the drift layer on the semiconductor substrate; epitaxially growing a semiconductor layer having the first conductivity type on the drift layer; forming a metal layer on the semiconductor layer; forming a patterned hard mask layer on the metal layer; and etching the metal layer and the semiconductor layer using the patterned hard mask layer as a mask to form the fin array and the recess region surrounding the fin array.
The method of claim 1, wherein the gate layer has an upper surface substantially flush with an upper surface of the fin array.
The method of claim 1, wherein the plurality of first elongated fins and the plurality of second elongated fins are offset from each other by an amount equal to the space.
The method of claim 1, wherein the method further comprises forming a metal layer on the gate layer.
The method of claim 1, wherein the plurality of first elongated fins and the plurality of second elongated fins have equal length.
The method of claim 1, wherein the plurality of first elongated fins and the plurality of second elongated fins are arranged in a plurality of columns, a first portion of the plurality of first elongated fins and a first portion of the B₂ plurality of second elongated fins in a first column having a length different than a length of a second portion of the plurality of first elongated fins and a second portion of the plurality of second elongated fins in a second column adjacent to the first column.
The method of claim 1, wherein a first portion of the plurality of first elongated fins and a first portion of the plurality of second elongated fins disposed in a center region of the semiconductor device has a length greater than a second portion of the plurality of first elongated fins and a second portion of the plurality of second elongated fins disposed in an edge region.
The method of claim 1, wherein a first portion of the plurality of first elongated fins and a first portion of the plurality of second elongated fins disposed in a center region of the semiconductor device has a length smaller than a second portion of the plurality of first elongated fins and a second portion of the plurality of second elongated fins disposed in an edge region.
The method of claim 1, wherein each of the first distance and the second distance is non-uniform, varying from a small distance in an edge region of the semiconductor substrate to a large distance in a center region of the semiconductor substrate.
The method of claim 1, wherein: a ratio between a fin width and a pitch between two adjacent fins is in a range between about 0.08 and 0.13; and a ratio between a fin length and the pitch between two adjacent fins is in a range between 5 and 25.
The method of claim 1, wherein a ratio between a fin length and a fin width is >50:1.
The method of claim 1, wherein each fin in the first row of fins and the second row of fins has a length in a range between 10 µm and 60 µm, and a width in a range between 0.15 µm and 0.7 µm.
A method of fabricating a semiconductor device, comprising: providing a substrate structure comprising: a semiconductor substrate having a first conductivity type; a drift layer of the first conductivity type coupled to the semiconductor substrate; a fin array comprising a plurality of rows of fins on the drift layer, the plurality of rows of fins including a first row of fins and a second row of fins; and a space between the first row of fins and the second row of fins; and providing a gate layer of a second conductivity type opposite the first conductivity type on the drift layer; wherein: the first row of fins comprising a plurality of first elongated fins arranged in parallel to each other along a first row direction and separated by a first distance, and the second row of fins comprising a plurality of second elongated fins arranged in parallel to each other along a second row direction and separated by a second distance, wherein each of the first distance and the second distance is non-uniform varying from a small distance in an edge region of the semiconductor substrate to a large distance in a center region of the semiconductor substrate to improve uniformity of the gate layer and to reduce channel length variation; the gate layer is adjacent to each of the plurality of first elongated fins and each of the plurality of second elongated fins; and the plurality of first elongated fins and the plurality of second elongated fins are configured to provide a vertical conducting channel for the semiconductor device.
The method of claim 15, wherein the plurality of first elongated fins and the plurality of second elongated fins are offset from each other by an amount equal to the space.
The method of claim 15, wherein the plurality of first elongated fins and the plurality of second elongated fins are arranged in a plurality of columns, a first portion of the plurality of first elongated fins and a first portion of the plurality of second elongated fins in a first column having a length different than a length of a second portion of the plurality of first elongated fins and a second portion of the plurality of second elongated fins in a second column adjacent to the first column.
A method of fabricating a semiconductor device, the method comprising: providing a substrate structure comprising: a semiconductor substrate of a first conductivity type, 20 a drift layer coupled to the semiconductor substrate, and a fin array coupled to the drift layer and surrounded by a recess region, wherein: the fin array comprises a first row of fins and a second row of fins parallel to each other and separated from each other by a space; the first row of fins comprising a plurality of first elongated fins extending parallel to each other in a first direction and arranged with a first distance between each other; the second row of fins comprising a plurality of second elongated fins extending parallel to each other in a second direction parallel to the first direction; and the plurality of first elongated fins and the plurality of second elongated fins are arranged in a plurality of columns; and providing a gate layer of a second conductivity type opposite to the first conductivity type adjacent to each fin in the first row of fins and the second row of fins; wherein: a first portion of the plurality of first elongated fins and a first portion of the plurality of second elongated fins in a first column comprise a length different than a length of a second portion of the plurality of first elongated fins and a second portion of the plurality of second elongated fins in a second column adjacent to the first column to improve uniformity of the gate layer and to reduce channel length variation; and the plurality of first elongated fins and the plurality of second elongated fins are configured to provide a vertical conducting channel for the semiconductor device. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
vertical fin-based FET (FinFET) semiconductor device
Materials described outside the worked examples.
semiconductor substrate (first conductivity type)
gate layer (second conductivity type, epitaxially regrown)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 7B shows growth thickness variations on an 800 nm regrowth wafer according to an embodiment of the present disclosure;
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 550–650 nm | — |
Thickness |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 12
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,520,513 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified cross-sectional view illustrating a semiconductor device according to an embodiment of the present disclosure;
FIGS. 2A-2D are simplified cross-sectional views illus- trating the fabrication of a semiconductor device including a plurality of semiconductor fins surrounding …
FIG. 3 is a simplified cross-sectional view illustrating variations of the regrown gates along sidewalls of the semiconductor fins;
FIGS. 4A-4G show results of regrowth profiles on respec- tive 200 nm, 400 nm, 500 nm, 550 nm, 600 nm, 650 nm, and 800 nm regrowth wafers according to an …
FIG. 5 is a plan view of a fin pattern layout for explaining the terms that are used in the present disclosure;
FIG. 6 is a plan view of a fin pattern layout illustrating semiconductor fins having shorter lengths according to an embodiment of the present disclosure;
FIG. 7B shows growth thickness variations on an 800 nm regrowth wafer according to an embodiment of the present disclosure;
FIG. 8B shows growth thickness variations on an 800 nm regrowth wafer based on FIB data according to an embodi- 5 ment of the present disclosure;
FIGS. 9A-9D are Nomarski-contrast micrograph images illustrating the effect of different fin lengths of an 800 nm regrowth wafer according to an embodiment of …
FIGS. 10A and 10B are high-resolution Nomarski-con- trast micrograph images illustrating the effect of different fin lengths for a 25 µm fin and a 1000 µm fin on …
FIGS. 11A-11D are Nomarski-contrast micrograph images illustrating and the variation (standard deviation sigma, range) of 25 µm, 50 µm, 100 µm, and 1000 µm fin …
FIG. 12 is an oblique view SEM image of a 0.3 µm×25 µm (width×length) fin array with a 2 µm pitch on a 500 nm regrowth wafer according to an embodiment of the …
FIG. 13 is a plan view of a fin pattern layout illustrating semiconductor fins having short lengths according to an embodiment of the present disclosure;
FIG. 14 is a plan view of a fin pattern layout illustrating semiconductor fins having short lengths according to 30 another embodiment of the present disclosure;
FIG. 15 is a plan view of a fin pattern layout illustrating semiconductor fins having short lengths according to yet another embodiment of the present …
FIG. 16 is a simplified flowchart illustrating a method of 35 fabricating a semiconductor device having a fin array according to an embodiment of the present …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of fabricating a semiconductor device, the method comprising: providing a substrate structure comprising a semiconduc-tor substrate of a first conductivity type, a drift layer on the semiconductor substrate, and a fin array on the drift layer and surrounded by a recess region, wherein the fin array comprises a first row of fins and a second row of fins parallel to each other and separated from each other by a space, the first row of fins comprising a plurality of first elongated fins extending parallel to each other in a first direction and arranged with a first distance between each other, and the second row of fins com-prising a plurality of second elongated fins extending parallel to each other in a second direction parallel to the first direction and arranged with a second distance between each other; and epitaxially regrowing a gate layer of a second conductiv-ity type opposite the first conductivity type on the drift layer and filling the recess region, the gate layer sur-rounding the first row of fins and the second row of fins; wherein: the second distance is equal to the first distance and the space between the first row of fins and the second row of fins is equal to the first distance to improve uniformity of the gate layer the gate layer and to reduce channel length variation; and the plurality of first elongated fins and the plurality of 30 second elongated fins are configured to provide a vertical conducting channel for the semiconductor device.
The method of claim 1, further comprising: forming a plurality of source contacts, each coupled to an upper surface of each fin of the fin array; forming one or more gate contacts on the gate layer; and forming a drain contact coupled to the semiconductor substrate.
The method of claim 1, wherein providing the substrate structure comprises: providing the semiconductor substrate; epitaxially growing the drift layer on the semiconductor substrate; epitaxially growing a semiconductor layer having the first conductivity type on the drift layer; forming a metal layer on the semiconductor layer; forming a patterned hard mask layer on the metal layer; and etching the metal layer and the semiconductor layer using the patterned hard mask layer as a mask to form the fin array and the recess region surrounding the fin array.
The method of claim 1, wherein the gate layer has an upper surface substantially flush with an upper surface of the fin array.
The method of claim 1, wherein the plurality of first elongated fins and the plurality of second elongated fins are offset from each other by an amount equal to the space.
The method of claim 1, wherein the method further comprises forming a metal layer on the gate layer.
The method of claim 1, wherein the plurality of first elongated fins and the plurality of second elongated fins have equal length.
The method of claim 1, wherein the plurality of first elongated fins and the plurality of second elongated fins are arranged in a plurality of columns, a first portion of the plurality of first elongated fins and a first portion of the B₂ plurality of second elongated fins in a first column having a length different than a length of a second portion of the plurality of first elongated fins and a second portion of the plurality of second elongated fins in a second column adjacent to the first column.
The method of claim 1, wherein a first portion of the plurality of first elongated fins and a first portion of the plurality of second elongated fins disposed in a center region of the semiconductor device has a length greater than a second portion of the plurality of first elongated fins and a second portion of the plurality of second elongated fins disposed in an edge region.
The method of claim 1, wherein a first portion of the plurality of first elongated fins and a first portion of the plurality of second elongated fins disposed in a center region of the semiconductor device has a length smaller than a second portion of the plurality of first elongated fins and a second portion of the plurality of second elongated fins disposed in an edge region.
The method of claim 1, wherein each of the first distance and the second distance is non-uniform, varying from a small distance in an edge region of the semiconductor substrate to a large distance in a center region of the semiconductor substrate.
The method of claim 1, wherein: a ratio between a fin width and a pitch between two adjacent fins is in a range between about 0.08 and 0.13; and a ratio between a fin length and the pitch between two adjacent fins is in a range between 5 and 25.
The method of claim 1, wherein a ratio between a fin length and a fin width is >50:1.
The method of claim 1, wherein each fin in the first row of fins and the second row of fins has a length in a range between 10 µm and 60 µm, and a width in a range between 0.15 µm and 0.7 µm.
A method of fabricating a semiconductor device, comprising: providing a substrate structure comprising: a semiconductor substrate having a first conductivity type; a drift layer of the first conductivity type coupled to the semiconductor substrate; a fin array comprising a plurality of rows of fins on the drift layer, the plurality of rows of fins including a first row of fins and a second row of fins; and a space between the first row of fins and the second row of fins; and providing a gate layer of a second conductivity type opposite the first conductivity type on the drift layer; wherein: the first row of fins comprising a plurality of first elongated fins arranged in parallel to each other along a first row direction and separated by a first distance, and the second row of fins comprising a plurality of second elongated fins arranged in parallel to each other along a second row direction and separated by a second distance, wherein each of the first distance and the second distance is non-uniform varying from a small distance in an edge region of the semiconductor substrate to a large distance in a center region of the semiconductor substrate to improve uniformity of the gate layer and to reduce channel length variation; the gate layer is adjacent to each of the plurality of first elongated fins and each of the plurality of second elongated fins; and the plurality of first elongated fins and the plurality of second elongated fins are configured to provide a vertical conducting channel for the semiconductor device.
The method of claim 15, wherein the plurality of first elongated fins and the plurality of second elongated fins are offset from each other by an amount equal to the space.
The method of claim 15, wherein the plurality of first elongated fins and the plurality of second elongated fins are arranged in a plurality of columns, a first portion of the plurality of first elongated fins and a first portion of the plurality of second elongated fins in a first column having a length different than a length of a second portion of the plurality of first elongated fins and a second portion of the plurality of second elongated fins in a second column adjacent to the first column.
A method of fabricating a semiconductor device, the method comprising: providing a substrate structure comprising: a semiconductor substrate of a first conductivity type, 20 a drift layer coupled to the semiconductor substrate, and a fin array coupled to the drift layer and surrounded by a recess region, wherein: the fin array comprises a first row of fins and a second row of fins parallel to each other and separated from each other by a space; the first row of fins comprising a plurality of first elongated fins extending parallel to each other in a first direction and arranged with a first distance between each other; the second row of fins comprising a plurality of second elongated fins extending parallel to each other in a second direction parallel to the first direction; and the plurality of first elongated fins and the plurality of second elongated fins are arranged in a plurality of columns; and providing a gate layer of a second conductivity type opposite to the first conductivity type adjacent to each fin in the first row of fins and the second row of fins; wherein: a first portion of the plurality of first elongated fins and a first portion of the plurality of second elongated fins in a first column comprise a length different than a length of a second portion of the plurality of first elongated fins and a second portion of the plurality of second elongated fins in a second column adjacent to the first column to improve uniformity of the gate layer and to reduce channel length variation; and the plurality of first elongated fins and the plurality of second elongated fins are configured to provide a vertical conducting channel for the semiconductor device. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
vertical fin-based FET (FinFET) semiconductor device
Materials described outside the worked examples.
semiconductor substrate (first conductivity type)
gate layer (second conductivity type, epitaxially regrown)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 7B shows growth thickness variations on an 800 nm regrowth wafer according to an embodiment of the present disclosure;
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 550–650 nm | — |
Thickness |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 12
Related documents with shared materials, methods, properties, or citations.
drift layer (first conductivity type)
gallium nitride
GaN
FIG. 8B shows growth thickness variations on an 800 nm regrowth wafer based on FIB data according to an embodi- 5 ment of the present disclosure;
FIG. 12 is an oblique view SEM image of a 0.3 µm×25 µm (width×length) fin array with a 2 µm pitch on a 500 nm regrowth wafer according to an embodiment of the …
| — |
Thickness | 50–180 nm | — |
Thickness | 120–540 nm | — |
Thickness | 120–460 nm | — |
Thickness | 450–650 nm | — |
Thickness | 0.15–0.3 µm | — |
Thickness | 10–100 µm | — |
Thickness | 0.2–0.7 µm | — |
Thickness | 25–500 µm | — |
Thickness | 1.9–10 µm | — |
Temperature | 850–1050 °C | — |
Thickness | 0.7–0.8 µm | — |
Thickness | 0–1200 µm | — |
Thickness | 25–1000 µm | — |
Thickness | ≤ 30 nm | — |
Thickness | ≤ 1 µm | — |
Thickness | ≤ 2.5 µm | — |
Thickness | ≤ 2 µm | — |
Thickness | ≤ 50 µm | — |
Thickness | ≥ 1 µm | — |
Thickness | 10–60 µm | — |
Thickness | 0.15–0.7 µm | — |
Cited non-patent literature · 1
drift layer (first conductivity type)
gallium nitride
GaN
FIG. 8B shows growth thickness variations on an 800 nm regrowth wafer based on FIB data according to an embodi- 5 ment of the present disclosure;
FIG. 12 is an oblique view SEM image of a 0.3 µm×25 µm (width×length) fin array with a 2 µm pitch on a 500 nm regrowth wafer according to an embodiment of the …
| — |
Thickness | 50–180 nm | — |
Thickness | 120–540 nm | — |
Thickness | 120–460 nm | — |
Thickness | 450–650 nm | — |
Thickness | 0.15–0.3 µm | — |
Thickness | 10–100 µm | — |
Thickness | 0.2–0.7 µm | — |
Thickness | 25–500 µm | — |
Thickness | 1.9–10 µm | — |
Temperature | 850–1050 °C | — |
Thickness | 0.7–0.8 µm | — |
Thickness | 0–1200 µm | — |
Thickness | 25–1000 µm | — |
Thickness | ≤ 30 nm | — |
Thickness | ≤ 1 µm | — |
Thickness | ≤ 2.5 µm | — |
Thickness | ≤ 2 µm | — |
Thickness | ≤ 50 µm | — |
Thickness | ≥ 1 µm | — |
Thickness | 10–60 µm | — |
Thickness | 0.15–0.7 µm | — |
Cited non-patent literature · 1
drift layer (first conductivity type)
gallium nitride
GaN
FIG. 8B shows growth thickness variations on an 800 nm regrowth wafer based on FIB data according to an embodi- 5 ment of the present disclosure;
FIG. 12 is an oblique view SEM image of a 0.3 µm×25 µm (width×length) fin array with a 2 µm pitch on a 500 nm regrowth wafer according to an embodiment of the …
| — |
Thickness | 50–180 nm | — |
Thickness | 120–540 nm | — |
Thickness | 120–460 nm | — |
Thickness | 450–650 nm | — |
Thickness | 0.15–0.3 µm | — |
Thickness | 10–100 µm | — |
Thickness | 0.2–0.7 µm | — |
Thickness | 25–500 µm | — |
Thickness | 1.9–10 µm | — |
Temperature | 850–1050 °C | — |
Thickness | 0.7–0.8 µm | — |
Thickness | 0–1200 µm | — |
Thickness | 25–1000 µm | — |
Thickness | ≤ 30 nm | — |
Thickness | ≤ 1 µm | — |
Thickness | ≤ 2.5 µm | — |
Thickness | ≤ 2 µm | — |
Thickness | ≤ 50 µm | — |
Thickness | ≥ 1 µm | — |
Thickness | 10–60 µm | — |
Thickness | 0.15–0.7 µm | — |
Cited non-patent literature · 1
drift layer (first conductivity type)
gallium nitride
GaN
FIG. 8B shows growth thickness variations on an 800 nm regrowth wafer based on FIB data according to an embodi- 5 ment of the present disclosure;
FIG. 12 is an oblique view SEM image of a 0.3 µm×25 µm (width×length) fin array with a 2 µm pitch on a 500 nm regrowth wafer according to an embodiment of the …
| — |
Thickness | 50–180 nm | — |
Thickness | 120–540 nm | — |
Thickness | 120–460 nm | — |
Thickness | 450–650 nm | — |
Thickness | 0.15–0.3 µm | — |
Thickness | 10–100 µm | — |
Thickness | 0.2–0.7 µm | — |
Thickness | 25–500 µm | — |
Thickness | 1.9–10 µm | — |
Temperature | 850–1050 °C | — |
Thickness | 0.7–0.8 µm | — |
Thickness | 0–1200 µm | — |
Thickness | 25–1000 µm | — |
Thickness | ≤ 30 nm | — |
Thickness | ≤ 1 µm | — |
Thickness | ≤ 2.5 µm | — |
Thickness | ≤ 2 µm | — |
Thickness | ≤ 50 µm | — |
Thickness | ≥ 1 µm | — |
Thickness | 10–60 µm | — |
Thickness | 0.15–0.7 µm | — |
Cited non-patent literature · 1
