Patent
US 9,252,247Apparatus and Method for Reducing the Interface Resistance in GaN Heterojunction FETs
Miroslav Micovic
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 9,252,247Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 A shows an HFET as known in the art
Figure 1 B shows an HFET embody in g the technology
Figure 1 C shows an alternative embodiment of the technology where the exposure of the ba mer 20 also th in s the bar ri er layer outside the gate region
Figure 2 shows a schematic of the present technology and identify in g the in terface in question
Figures 3A-3F illustrates a method of construct in g the present technology
Figure 4 shows the range of bar ri er layer thickness and composition consistent with the present technology 25
Figure 5A shows the bandgap of four structures illustrat in g the advantages of the present technology 090602 -5- 5/7/2010 1
Figure 5B shows the charge density in the 2DEG at the in terface between the Ba rri er layer and the figures use similar numbers for the same components of the t echnology For example Barrier layer 130 in figure 1 is the same as Barrier layer 330 in figure 3 5
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
Amendments to the Claims Please amend the claims as follows. This listing of claims will replace all prior versions of claims in the application: Claims 1-12 are cancelled.
The method of claim 1 7 further comprising a step of disposing a cap layer on the barrier layer after exposing a portion of the barrier layer.
A method of reducing the interface resistance in an HFET device, the method comprising: forming a device comprising a substrate, a channel layer, a barrier layer, a gate and a gate yeg? ? re_ n exposing a portion of the barrier layer in the gate region to form a ledge; ~wg m a dopedcap layer on the channel layer and tb>&xpoe ahe ledge of the barrier layer Iq.;.,;a diitdoecig i t,.,,d;gas woa i;ere, thc forming a gate, source and drain on the device.
(O ri ginal) The method of claim 13 further comprising: thinning the channel layer outside the gate region.
The method of claim 13 further comprising: cleaning the exposed ledge of the barrier layer.
The method of claim 13 further comprising: wherein the cleaning of the exposed ledge is accomplished with hydrogen.
The method of claim 13, wherein the doped cap layer comprises SVG 14151979.06-05-2015.IAO₃VG₅BPXXIFW1.CLM.1.svg 0.12 0.52 Black and white
The method of claim 13, wherein the doped cap layer comprises a material that engineers the charge density below the exposed ledge of the barrier layer.
The method of claim 13, wherein the doped cap layer on the channel layer and the exposed ledge of the ba rri er layer are connected.
The method of claim 13, wherein the doped cap layer is formed on a top surface of the ledge of the barrier layer. -5-
A method of reducing the interface resistance in an HFET device, the method comprising: forming a device comprising a substrate, a channel layer, a barrier layer, a gate and a gate e gwron; exposing a portion of the barrier layer in the gate region to form a ledge; engineering a charge density below the exposed ledge of the barrier layer such that the charge density below the exposed ledge of the ba rri er layer is -3- greater than the charge density not below the exposed ledge of the ba rrier layer; forming a gate, source and drain on the device whereby engineering the charge density below the exposed ledge of the barrier layer is defined to mean selecting the materials, composition and thicknesses of the barrier layer.
The method of claim 17 further comprising a step of cleaning the exposed ledge of the barrier layer before engineering the charge density below the exposed ledge of the barrier layer.
The method of claim 17 wherein the channel layer comprises GaN and the barrier layer comprises AlGaN.
The method of claim 17 wherein the step of engineering the charge density below the exposed ledge of the barrier layer further comprises regrowing a cap layer on the exposed ledge of the ba rri er layer.
Layer stacks claimed or described, ordered top of device to substrate.
HFET (Heterojunction Field Effect Transistor)
Materials described outside the worked examples.
n+GaN cap layer
GaN
AlGaN barrier layer
AlGaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 4 shows the range of bar ri er layer thickness and composition consistent with the present technology 25
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
n+GaN cap layer doping concentration | ≥ 70000000000000000000 cm⁻³ | GaN |
regrown cap layer doping concentration (sheet) |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,252,247Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 A shows an HFET as known in the art
Figure 1 B shows an HFET embody in g the technology
Figure 1 C shows an alternative embodiment of the technology where the exposure of the ba mer 20 also th in s the bar ri er layer outside the gate region
Figure 2 shows a schematic of the present technology and identify in g the in terface in question
Figures 3A-3F illustrates a method of construct in g the present technology
Figure 4 shows the range of bar ri er layer thickness and composition consistent with the present technology 25
Figure 5A shows the bandgap of four structures illustrat in g the advantages of the present technology 090602 -5- 5/7/2010 1
Figure 5B shows the charge density in the 2DEG at the in terface between the Ba rri er layer and the figures use similar numbers for the same components of the t echnology For example Barrier layer 130 in figure 1 is the same as Barrier layer 330 in figure 3 5
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
Amendments to the Claims Please amend the claims as follows. This listing of claims will replace all prior versions of claims in the application: Claims 1-12 are cancelled.
The method of claim 1 7 further comprising a step of disposing a cap layer on the barrier layer after exposing a portion of the barrier layer.
A method of reducing the interface resistance in an HFET device, the method comprising: forming a device comprising a substrate, a channel layer, a barrier layer, a gate and a gate yeg? ? re_ n exposing a portion of the barrier layer in the gate region to form a ledge; ~wg m a dopedcap layer on the channel layer and tb>&xpoe ahe ledge of the barrier layer Iq.;.,;a diitdoecig i t,.,,d;gas woa i;ere, thc forming a gate, source and drain on the device.
(O ri ginal) The method of claim 13 further comprising: thinning the channel layer outside the gate region.
The method of claim 13 further comprising: cleaning the exposed ledge of the barrier layer.
The method of claim 13 further comprising: wherein the cleaning of the exposed ledge is accomplished with hydrogen.
The method of claim 13, wherein the doped cap layer comprises SVG 14151979.06-05-2015.IAO₃VG₅BPXXIFW1.CLM.1.svg 0.12 0.52 Black and white
The method of claim 13, wherein the doped cap layer comprises a material that engineers the charge density below the exposed ledge of the barrier layer.
The method of claim 13, wherein the doped cap layer on the channel layer and the exposed ledge of the ba rri er layer are connected.
The method of claim 13, wherein the doped cap layer is formed on a top surface of the ledge of the barrier layer. -5-
A method of reducing the interface resistance in an HFET device, the method comprising: forming a device comprising a substrate, a channel layer, a barrier layer, a gate and a gate e gwron; exposing a portion of the barrier layer in the gate region to form a ledge; engineering a charge density below the exposed ledge of the barrier layer such that the charge density below the exposed ledge of the ba rri er layer is -3- greater than the charge density not below the exposed ledge of the ba rrier layer; forming a gate, source and drain on the device whereby engineering the charge density below the exposed ledge of the barrier layer is defined to mean selecting the materials, composition and thicknesses of the barrier layer.
The method of claim 17 further comprising a step of cleaning the exposed ledge of the barrier layer before engineering the charge density below the exposed ledge of the barrier layer.
The method of claim 17 wherein the channel layer comprises GaN and the barrier layer comprises AlGaN.
The method of claim 17 wherein the step of engineering the charge density below the exposed ledge of the barrier layer further comprises regrowing a cap layer on the exposed ledge of the ba rri er layer.
Layer stacks claimed or described, ordered top of device to substrate.
HFET (Heterojunction Field Effect Transistor)
Materials described outside the worked examples.
n+GaN cap layer
GaN
AlGaN barrier layer
AlGaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 4 shows the range of bar ri er layer thickness and composition consistent with the present technology 25
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
n+GaN cap layer doping concentration | ≥ 70000000000000000000 cm⁻³ | GaN |
regrown cap layer doping concentration (sheet) |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,252,247Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 A shows an HFET as known in the art
Figure 1 B shows an HFET embody in g the technology
Figure 1 C shows an alternative embodiment of the technology where the exposure of the ba mer 20 also th in s the bar ri er layer outside the gate region
Figure 2 shows a schematic of the present technology and identify in g the in terface in question
Figures 3A-3F illustrates a method of construct in g the present technology
Figure 4 shows the range of bar ri er layer thickness and composition consistent with the present technology 25
Figure 5A shows the bandgap of four structures illustrat in g the advantages of the present technology 090602 -5- 5/7/2010 1
Figure 5B shows the charge density in the 2DEG at the in terface between the Ba rri er layer and the figures use similar numbers for the same components of the t echnology For example Barrier layer 130 in figure 1 is the same as Barrier layer 330 in figure 3 5
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
Amendments to the Claims Please amend the claims as follows. This listing of claims will replace all prior versions of claims in the application: Claims 1-12 are cancelled.
The method of claim 1 7 further comprising a step of disposing a cap layer on the barrier layer after exposing a portion of the barrier layer.
A method of reducing the interface resistance in an HFET device, the method comprising: forming a device comprising a substrate, a channel layer, a barrier layer, a gate and a gate yeg? ? re_ n exposing a portion of the barrier layer in the gate region to form a ledge; ~wg m a dopedcap layer on the channel layer and tb>&xpoe ahe ledge of the barrier layer Iq.;.,;a diitdoecig i t,.,,d;gas woa i;ere, thc forming a gate, source and drain on the device.
(O ri ginal) The method of claim 13 further comprising: thinning the channel layer outside the gate region.
The method of claim 13 further comprising: cleaning the exposed ledge of the barrier layer.
The method of claim 13 further comprising: wherein the cleaning of the exposed ledge is accomplished with hydrogen.
The method of claim 13, wherein the doped cap layer comprises SVG 14151979.06-05-2015.IAO₃VG₅BPXXIFW1.CLM.1.svg 0.12 0.52 Black and white
The method of claim 13, wherein the doped cap layer comprises a material that engineers the charge density below the exposed ledge of the barrier layer.
The method of claim 13, wherein the doped cap layer on the channel layer and the exposed ledge of the ba rri er layer are connected.
The method of claim 13, wherein the doped cap layer is formed on a top surface of the ledge of the barrier layer. -5-
A method of reducing the interface resistance in an HFET device, the method comprising: forming a device comprising a substrate, a channel layer, a barrier layer, a gate and a gate e gwron; exposing a portion of the barrier layer in the gate region to form a ledge; engineering a charge density below the exposed ledge of the barrier layer such that the charge density below the exposed ledge of the ba rri er layer is -3- greater than the charge density not below the exposed ledge of the ba rrier layer; forming a gate, source and drain on the device whereby engineering the charge density below the exposed ledge of the barrier layer is defined to mean selecting the materials, composition and thicknesses of the barrier layer.
The method of claim 17 further comprising a step of cleaning the exposed ledge of the barrier layer before engineering the charge density below the exposed ledge of the barrier layer.
The method of claim 17 wherein the channel layer comprises GaN and the barrier layer comprises AlGaN.
The method of claim 17 wherein the step of engineering the charge density below the exposed ledge of the barrier layer further comprises regrowing a cap layer on the exposed ledge of the ba rri er layer.
Layer stacks claimed or described, ordered top of device to substrate.
HFET (Heterojunction Field Effect Transistor)
Materials described outside the worked examples.
n+GaN cap layer
GaN
AlGaN barrier layer
AlGaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 4 shows the range of bar ri er layer thickness and composition consistent with the present technology 25
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
n+GaN cap layer doping concentration | ≥ 70000000000000000000 cm⁻³ | GaN |
regrown cap layer doping concentration (sheet) |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,252,247Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 A shows an HFET as known in the art
Figure 1 B shows an HFET embody in g the technology
Figure 1 C shows an alternative embodiment of the technology where the exposure of the ba mer 20 also th in s the bar ri er layer outside the gate region
Figure 2 shows a schematic of the present technology and identify in g the in terface in question
Figures 3A-3F illustrates a method of construct in g the present technology
Figure 4 shows the range of bar ri er layer thickness and composition consistent with the present technology 25
Figure 5A shows the bandgap of four structures illustrat in g the advantages of the present technology 090602 -5- 5/7/2010 1
Figure 5B shows the charge density in the 2DEG at the in terface between the Ba rri er layer and the figures use similar numbers for the same components of the t echnology For example Barrier layer 130 in figure 1 is the same as Barrier layer 330 in figure 3 5
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
Amendments to the Claims Please amend the claims as follows. This listing of claims will replace all prior versions of claims in the application: Claims 1-12 are cancelled.
The method of claim 1 7 further comprising a step of disposing a cap layer on the barrier layer after exposing a portion of the barrier layer.
A method of reducing the interface resistance in an HFET device, the method comprising: forming a device comprising a substrate, a channel layer, a barrier layer, a gate and a gate yeg? ? re_ n exposing a portion of the barrier layer in the gate region to form a ledge; ~wg m a dopedcap layer on the channel layer and tb>&xpoe ahe ledge of the barrier layer Iq.;.,;a diitdoecig i t,.,,d;gas woa i;ere, thc forming a gate, source and drain on the device.
(O ri ginal) The method of claim 13 further comprising: thinning the channel layer outside the gate region.
The method of claim 13 further comprising: cleaning the exposed ledge of the barrier layer.
The method of claim 13 further comprising: wherein the cleaning of the exposed ledge is accomplished with hydrogen.
The method of claim 13, wherein the doped cap layer comprises SVG 14151979.06-05-2015.IAO₃VG₅BPXXIFW1.CLM.1.svg 0.12 0.52 Black and white
The method of claim 13, wherein the doped cap layer comprises a material that engineers the charge density below the exposed ledge of the barrier layer.
The method of claim 13, wherein the doped cap layer on the channel layer and the exposed ledge of the ba rri er layer are connected.
The method of claim 13, wherein the doped cap layer is formed on a top surface of the ledge of the barrier layer. -5-
A method of reducing the interface resistance in an HFET device, the method comprising: forming a device comprising a substrate, a channel layer, a barrier layer, a gate and a gate e gwron; exposing a portion of the barrier layer in the gate region to form a ledge; engineering a charge density below the exposed ledge of the barrier layer such that the charge density below the exposed ledge of the ba rri er layer is -3- greater than the charge density not below the exposed ledge of the ba rrier layer; forming a gate, source and drain on the device whereby engineering the charge density below the exposed ledge of the barrier layer is defined to mean selecting the materials, composition and thicknesses of the barrier layer.
The method of claim 17 further comprising a step of cleaning the exposed ledge of the barrier layer before engineering the charge density below the exposed ledge of the barrier layer.
The method of claim 17 wherein the channel layer comprises GaN and the barrier layer comprises AlGaN.
The method of claim 17 wherein the step of engineering the charge density below the exposed ledge of the barrier layer further comprises regrowing a cap layer on the exposed ledge of the ba rri er layer.
Layer stacks claimed or described, ordered top of device to substrate.
HFET (Heterojunction Field Effect Transistor)
Materials described outside the worked examples.
n+GaN cap layer
GaN
AlGaN barrier layer
AlGaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 4 shows the range of bar ri er layer thickness and composition consistent with the present technology 25
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
n+GaN cap layer doping concentration | ≥ 70000000000000000000 cm⁻³ | GaN |
regrown cap layer doping concentration (sheet) |
Related documents with shared materials, methods, properties, or citations.
hydrogen
H₂
AlxGa₁-xN barrier layer
AlxGa₁-xN
Figure 5A shows the bandgap of four structures illustrat in g the advantages of the present technology 090602 -5- 5/7/2010 1
GaN |
exposed ledge width of barrier layer | 20–500 nm | AlGaN |
Thickness | 20–500 nm | — |
Thickness | 20–100 nm | — |
Thickness | 5–25 nm | — |
Thickness | 100–500 nm | — |
Thickness | 0–100 nm | — |
Thickness | 0–500 nm | — |
hydrogen
H₂
AlxGa₁-xN barrier layer
AlxGa₁-xN
Figure 5A shows the bandgap of four structures illustrat in g the advantages of the present technology 090602 -5- 5/7/2010 1
GaN |
exposed ledge width of barrier layer | 20–500 nm | AlGaN |
Thickness | 20–500 nm | — |
Thickness | 20–100 nm | — |
Thickness | 5–25 nm | — |
Thickness | 100–500 nm | — |
Thickness | 0–100 nm | — |
Thickness | 0–500 nm | — |
hydrogen
H₂
AlxGa₁-xN barrier layer
AlxGa₁-xN
Figure 5A shows the bandgap of four structures illustrat in g the advantages of the present technology 090602 -5- 5/7/2010 1
GaN |
exposed ledge width of barrier layer | 20–500 nm | AlGaN |
Thickness | 20–500 nm | — |
Thickness | 20–100 nm | — |
Thickness | 5–25 nm | — |
Thickness | 100–500 nm | — |
Thickness | 0–100 nm | — |
Thickness | 0–500 nm | — |
hydrogen
H₂
AlxGa₁-xN barrier layer
AlxGa₁-xN
Figure 5A shows the bandgap of four structures illustrat in g the advantages of the present technology 090602 -5- 5/7/2010 1
GaN |
exposed ledge width of barrier layer | 20–500 nm | AlGaN |
Thickness | 20–500 nm | — |
Thickness | 20–100 nm | — |
Thickness | 5–25 nm | — |
Thickness | 100–500 nm | — |
Thickness | 0–100 nm | — |
Thickness | 0–500 nm | — |