Patent
US 8,638,614NON-VOLATILE MEMORY DEVICE AND MOSFET USING GRAPHENE GATE ELECTRODE
Byung Jin Cho, Jong Kyung Park
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 8,638,614Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A non-volatile memory device, comprising: a tunnel oxide for tunneling charges, a data storage layer, a blocking oxide, a gate electrode made of graphene and a metal electrode for capping, which are sequentially formed on a channel region between the source/drain electrodes of a substrate.
The non-volatile memory device according to claim 1, wherein the gate electrode made of graphene serves to lower a tunneling current in j ected into the data storage layer from the gate electrode during an erasing operation, and serves to prevent charges in j ected into the data storage layer from being discharged to the gate electrode to improve data retention characteristics of the non-volatile memory device during program operation.
The non-volatile memory device according to claim 1, wherein the gate electrode is made of P-type doped graphene.
The non-volatile memory device according to claim 1, wherein the gate electrode is formed to a thickness of 1-10 nm.
The non-volatile memory device according to claim 1, wherein the metal electrode is disposed over an entire region of the gate electrode.
The non-volatile memory device according to claim 1, wherein the metal electrode is disposed over a part of a center region of the gate electrode. Page 4 Serial No. 13/342,282 Response to Non-Final Office Action
The non-volatile memory device according to claim 1, wherein the metal electrode is formed to a thickness of 3-200 nm.
The non-volatile memory device according to claim 1, wherein the metal electrode is made of aluminum (A l), nickel (N i), platinum (Pt), gold (Au), copper (Cu), chromium (Cr), ruthenium (Ru), cobalt (Co), lead (Pd), silicon (S i), tungsten (W) or a combination thereof.
The non-volatile memory device according to claim 1, wherein the blocking oxide is formed of a S 10 2 film, an A l20 3 film or a combination thereof.
The non-volatile memory device according to claim 1, wherein the blocking oxide is formed to a thickness of 6-15 nm. 11. The non-volatile memory device according to claim 1, wherein the data storage layer is a charge trap layer which traps charges into a deep level trap site and is formed of a S i 3N₄ film.
The non-volatile memory device according to claim 1, wherein the data storage layer is a charge storage layer which stores charges in a conduction band and is formed of a polysilicon film.
The non-volatile memory device according to claim 1, wherein the data storage layer is formed to a thickness of 1-10 nm.
The non-volatile memory device according to claim 1, wherein the tunnel oxide is formed of a S 10 2 film. Page 5 Serial No. 13/342,282 Response to Non-Final Office Action
The non-volatile memory device according to claim 1, wherein the tunnel oxide is formed to a thickness of 1-10 nm.
A Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET), comprising: a gate oxide, a gate electrode made of graphene and a metal electrode for capping, which are sequentially formed on a channel region between the source/drain electrodes of a substrate.
The MOSFET according to claim 16, wherein the gate oxide is made of S 10 2 layer, S i ON layer, A l 203 layer, Hf O 2 layer, Hf ON layer, HfS i ON layer, HfLaON layer, Zr O 2 layer, ZrON layer, ZrS i ON layer, ZrLaON layer, La₂ 0 3 layer, Gd₂ 0 3 layer or a combination thereof.
The MOSFET according to claim 16, wherein the gate oxide is formed to a thickness of 1-20 nm.
Layer stacks claimed or described, ordered top of device to substrate.
non-volatile memory device
Materials described outside the worked examples.
graphene
data storage layer
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1–10 nm | — |
Thickness | 3–200 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,638,614Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A non-volatile memory device, comprising: a tunnel oxide for tunneling charges, a data storage layer, a blocking oxide, a gate electrode made of graphene and a metal electrode for capping, which are sequentially formed on a channel region between the source/drain electrodes of a substrate.
The non-volatile memory device according to claim 1, wherein the gate electrode made of graphene serves to lower a tunneling current in j ected into the data storage layer from the gate electrode during an erasing operation, and serves to prevent charges in j ected into the data storage layer from being discharged to the gate electrode to improve data retention characteristics of the non-volatile memory device during program operation.
The non-volatile memory device according to claim 1, wherein the gate electrode is made of P-type doped graphene.
The non-volatile memory device according to claim 1, wherein the gate electrode is formed to a thickness of 1-10 nm.
The non-volatile memory device according to claim 1, wherein the metal electrode is disposed over an entire region of the gate electrode.
The non-volatile memory device according to claim 1, wherein the metal electrode is disposed over a part of a center region of the gate electrode. Page 4 Serial No. 13/342,282 Response to Non-Final Office Action
The non-volatile memory device according to claim 1, wherein the metal electrode is formed to a thickness of 3-200 nm.
The non-volatile memory device according to claim 1, wherein the metal electrode is made of aluminum (A l), nickel (N i), platinum (Pt), gold (Au), copper (Cu), chromium (Cr), ruthenium (Ru), cobalt (Co), lead (Pd), silicon (S i), tungsten (W) or a combination thereof.
The non-volatile memory device according to claim 1, wherein the blocking oxide is formed of a S 10 2 film, an A l20 3 film or a combination thereof.
The non-volatile memory device according to claim 1, wherein the blocking oxide is formed to a thickness of 6-15 nm. 11. The non-volatile memory device according to claim 1, wherein the data storage layer is a charge trap layer which traps charges into a deep level trap site and is formed of a S i 3N₄ film.
The non-volatile memory device according to claim 1, wherein the data storage layer is a charge storage layer which stores charges in a conduction band and is formed of a polysilicon film.
The non-volatile memory device according to claim 1, wherein the data storage layer is formed to a thickness of 1-10 nm.
The non-volatile memory device according to claim 1, wherein the tunnel oxide is formed of a S 10 2 film. Page 5 Serial No. 13/342,282 Response to Non-Final Office Action
The non-volatile memory device according to claim 1, wherein the tunnel oxide is formed to a thickness of 1-10 nm.
A Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET), comprising: a gate oxide, a gate electrode made of graphene and a metal electrode for capping, which are sequentially formed on a channel region between the source/drain electrodes of a substrate.
The MOSFET according to claim 16, wherein the gate oxide is made of S 10 2 layer, S i ON layer, A l 203 layer, Hf O 2 layer, Hf ON layer, HfS i ON layer, HfLaON layer, Zr O 2 layer, ZrON layer, ZrS i ON layer, ZrLaON layer, La₂ 0 3 layer, Gd₂ 0 3 layer or a combination thereof.
The MOSFET according to claim 16, wherein the gate oxide is formed to a thickness of 1-20 nm.
Layer stacks claimed or described, ordered top of device to substrate.
non-volatile memory device
Materials described outside the worked examples.
graphene
data storage layer
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1–10 nm | — |
Thickness | 3–200 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,638,614Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A non-volatile memory device, comprising: a tunnel oxide for tunneling charges, a data storage layer, a blocking oxide, a gate electrode made of graphene and a metal electrode for capping, which are sequentially formed on a channel region between the source/drain electrodes of a substrate.
The non-volatile memory device according to claim 1, wherein the gate electrode made of graphene serves to lower a tunneling current in j ected into the data storage layer from the gate electrode during an erasing operation, and serves to prevent charges in j ected into the data storage layer from being discharged to the gate electrode to improve data retention characteristics of the non-volatile memory device during program operation.
The non-volatile memory device according to claim 1, wherein the gate electrode is made of P-type doped graphene.
The non-volatile memory device according to claim 1, wherein the gate electrode is formed to a thickness of 1-10 nm.
The non-volatile memory device according to claim 1, wherein the metal electrode is disposed over an entire region of the gate electrode.
The non-volatile memory device according to claim 1, wherein the metal electrode is disposed over a part of a center region of the gate electrode. Page 4 Serial No. 13/342,282 Response to Non-Final Office Action
The non-volatile memory device according to claim 1, wherein the metal electrode is formed to a thickness of 3-200 nm.
The non-volatile memory device according to claim 1, wherein the metal electrode is made of aluminum (A l), nickel (N i), platinum (Pt), gold (Au), copper (Cu), chromium (Cr), ruthenium (Ru), cobalt (Co), lead (Pd), silicon (S i), tungsten (W) or a combination thereof.
The non-volatile memory device according to claim 1, wherein the blocking oxide is formed of a S 10 2 film, an A l20 3 film or a combination thereof.
The non-volatile memory device according to claim 1, wherein the blocking oxide is formed to a thickness of 6-15 nm. 11. The non-volatile memory device according to claim 1, wherein the data storage layer is a charge trap layer which traps charges into a deep level trap site and is formed of a S i 3N₄ film.
The non-volatile memory device according to claim 1, wherein the data storage layer is a charge storage layer which stores charges in a conduction band and is formed of a polysilicon film.
The non-volatile memory device according to claim 1, wherein the data storage layer is formed to a thickness of 1-10 nm.
The non-volatile memory device according to claim 1, wherein the tunnel oxide is formed of a S 10 2 film. Page 5 Serial No. 13/342,282 Response to Non-Final Office Action
The non-volatile memory device according to claim 1, wherein the tunnel oxide is formed to a thickness of 1-10 nm.
A Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET), comprising: a gate oxide, a gate electrode made of graphene and a metal electrode for capping, which are sequentially formed on a channel region between the source/drain electrodes of a substrate.
The MOSFET according to claim 16, wherein the gate oxide is made of S 10 2 layer, S i ON layer, A l 203 layer, Hf O 2 layer, Hf ON layer, HfS i ON layer, HfLaON layer, Zr O 2 layer, ZrON layer, ZrS i ON layer, ZrLaON layer, La₂ 0 3 layer, Gd₂ 0 3 layer or a combination thereof.
The MOSFET according to claim 16, wherein the gate oxide is formed to a thickness of 1-20 nm.
Layer stacks claimed or described, ordered top of device to substrate.
non-volatile memory device
Materials described outside the worked examples.
graphene
data storage layer
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1–10 nm | — |
Thickness | 3–200 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,638,614Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A non-volatile memory device, comprising: a tunnel oxide for tunneling charges, a data storage layer, a blocking oxide, a gate electrode made of graphene and a metal electrode for capping, which are sequentially formed on a channel region between the source/drain electrodes of a substrate.
The non-volatile memory device according to claim 1, wherein the gate electrode made of graphene serves to lower a tunneling current in j ected into the data storage layer from the gate electrode during an erasing operation, and serves to prevent charges in j ected into the data storage layer from being discharged to the gate electrode to improve data retention characteristics of the non-volatile memory device during program operation.
The non-volatile memory device according to claim 1, wherein the gate electrode is made of P-type doped graphene.
The non-volatile memory device according to claim 1, wherein the gate electrode is formed to a thickness of 1-10 nm.
The non-volatile memory device according to claim 1, wherein the metal electrode is disposed over an entire region of the gate electrode.
The non-volatile memory device according to claim 1, wherein the metal electrode is disposed over a part of a center region of the gate electrode. Page 4 Serial No. 13/342,282 Response to Non-Final Office Action
The non-volatile memory device according to claim 1, wherein the metal electrode is formed to a thickness of 3-200 nm.
The non-volatile memory device according to claim 1, wherein the metal electrode is made of aluminum (A l), nickel (N i), platinum (Pt), gold (Au), copper (Cu), chromium (Cr), ruthenium (Ru), cobalt (Co), lead (Pd), silicon (S i), tungsten (W) or a combination thereof.
The non-volatile memory device according to claim 1, wherein the blocking oxide is formed of a S 10 2 film, an A l20 3 film or a combination thereof.
The non-volatile memory device according to claim 1, wherein the blocking oxide is formed to a thickness of 6-15 nm. 11. The non-volatile memory device according to claim 1, wherein the data storage layer is a charge trap layer which traps charges into a deep level trap site and is formed of a S i 3N₄ film.
The non-volatile memory device according to claim 1, wherein the data storage layer is a charge storage layer which stores charges in a conduction band and is formed of a polysilicon film.
The non-volatile memory device according to claim 1, wherein the data storage layer is formed to a thickness of 1-10 nm.
The non-volatile memory device according to claim 1, wherein the tunnel oxide is formed of a S 10 2 film. Page 5 Serial No. 13/342,282 Response to Non-Final Office Action
The non-volatile memory device according to claim 1, wherein the tunnel oxide is formed to a thickness of 1-10 nm.
A Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET), comprising: a gate oxide, a gate electrode made of graphene and a metal electrode for capping, which are sequentially formed on a channel region between the source/drain electrodes of a substrate.
The MOSFET according to claim 16, wherein the gate oxide is made of S 10 2 layer, S i ON layer, A l 203 layer, Hf O 2 layer, Hf ON layer, HfS i ON layer, HfLaON layer, Zr O 2 layer, ZrON layer, ZrS i ON layer, ZrLaON layer, La₂ 0 3 layer, Gd₂ 0 3 layer or a combination thereof.
The MOSFET according to claim 16, wherein the gate oxide is formed to a thickness of 1-20 nm.
Layer stacks claimed or described, ordered top of device to substrate.
non-volatile memory device
Materials described outside the worked examples.
graphene
data storage layer
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1–10 nm | — |
Thickness | 3–200 nm |
Related documents with shared materials, methods, properties, or citations.
MOSFET
blocking oxide
metal electrode
P-type doped graphene
SiO₂
Al₂O₃
Si₃N₄
polysilicon
gate oxide
| — |
Thickness | 6–15 nm | — |
Thickness | 1–20 nm | — |
GRAPHENE SENSOR
MOSFET
blocking oxide
metal electrode
P-type doped graphene
SiO₂
Al₂O₃
Si₃N₄
polysilicon
gate oxide
| — |
Thickness | 6–15 nm | — |
Thickness | 1–20 nm | — |
GRAPHENE SENSOR
MOSFET
blocking oxide
metal electrode
P-type doped graphene
SiO₂
Al₂O₃
Si₃N₄
polysilicon
gate oxide
| — |
Thickness | 6–15 nm | — |
Thickness | 1–20 nm | — |
GRAPHENE SENSOR
MOSFET
blocking oxide
metal electrode
P-type doped graphene
SiO₂
Al₂O₃
Si₃N₄
polysilicon
gate oxide
| — |
Thickness | 6–15 nm | — |
Thickness | 1–20 nm | — |
GRAPHENE SENSOR