Patent
Atlas literature
Patent
US 9,093,395Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified schematic diagram illustrating a conventional Schottky barrier diode; [0008]
FIG. 2 is a simplified schematic diagram illustrating a conventional p-n junction diode; 5 [0009]
FIG. 3 is a simplified schematic diagram illustrating a conventional vertical junction field effect transistor; [0010]
FIG. 4 is a simplified schematic diagram illustrating a Schottky barrier diode with reduced defects according to an embodiment of the present invention; [0011]
FIG. 5 is a simplified schematic diagram illustrating a p-n junction diode with reduced 10 defects according to an embodiment of the present invention; [0012]
FIG. 6 is a simplified schematic diagram illustrating a vertical junction field effect transistor with reduced defects according to an embodiment of the present …
FIG. 7 is a simplified flowchart illustrating a method of fabricating an electronic structure with reduced defects according to an embodiment of the present …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A diode comprising: a substrate characterized by a first dislocation density and a first conductivity type; a first contact coupled to the substrate; a masking layer having a predetermined thickness and coupled to the semiconductor substrate, wherein the masking layer comprises a plurality of continuous sections and a plurality of openings exposing the substrate, wherein the openings are disposed between the continuous sections; an epitaxial layer greater than 5 p m thick coupled to the substrate and the masking layer, wherein the epitaxial layer comprises: a first set of regions overlying the plurality of openings and characterized by a second dislocation density; and a second set of regions overlying the set of continuous sections and characterized by a third dislocation density less than the first dislocation density and the second dislocation density; and a plurality of second contacts coupled to the epitaxial la y er, wherein each of the second contacts overlies a continuous section of the masking la v er, and wherein each continuous section of the masking la v er is overlied by more than one second contact.
The diode of claim 1 wherein the substrate comprises a GaN substrate and the first dislocation density is higher than 1 x 10 5 cm 2.
The diode of claim 1 wherein the first conductivity type comprises an n-type. Page 2 of 9 SVG 13225345.11-03-2014.I₂₂₇₈SEUPXXIFW3.CLM3397090.1.300.159.2249.242.svg 0.277 6.497 Graph Black and white Response to Office Action of
The diode of claim 1 wherein the epitaxial layer comprises one or more GaN-based layers.
The diode of claim 1 wherein the masking layer comprises a patterned oxide layer.
The diode of claim 1 wherein the plurality of openings are characterized by a lateral width of between 2 p m and 10 pm.
The diode of claim 1 wherein the second dislocation density is substantially equal to the first dislocation density.
The diode of claim 1 wherein the second contact overlies the second set of regions of the epitaxial layer.
The diode of claim 1 further comprising a coalescence boundary disposed in the second set of regions of the epitaxial layer.
The diode of claim 1 further comprising a second epitaxial layer of a second conductivity type opposite to the first conductivity type disposed between the epitaxial layer and the second contact.
The diode of claim 1 further wherein the second contact comprises a Schottky contact.
A vertical junction FET comprising: Page 3 of 9 SVG 13225345.11-03-2014.I₂₂₇₈SEUPXXIFW3.CLM3397091.1.300.159.2249.242.svg 0.277 6.497 Graph Black and white Response to Office Action of a substrate characterized by a first dislocation density and a first conductivity type; a first contact coupled to the substrate; a masking layer having a predetermined thickness and coupled to the semiconductor substrate, wherein the masking layer comprises a plurality of continuous sections of the predetermined thickness and a plurality of openings exposing the substrate, wherein the openings are disposed between the continuous sections; an epitaxial layer coupled to the substrate and the masking layer, wherein the epitaxial layer comprises: a first set of regions overlying the plurality of openings and characterized by a second dislocation density; and a second set of regions overlying the set of continuous sections and characterized by a third dislocation density less than the first dislocation density and the second dislocation density; a plurality of gate regions coupled to the epitaxial layer and defining one or more current flow channels; one or more second contacts coupled to the epitaxial layer, each of the one or more second contacts being adjacent one of the one or more current flow channels, wherein each of the second contacts overlies a corresponding one of the continuous sections of the masking layer, and wherein each continuous section of the masking la y er is overlied by more than one second contact; and a plurality of third contacts, each of the plurality of third contacts being coupled to one of the plurality of gate regions.
The vertical junction FET of claim 15 wherein the substrate comprises a I II -nitride substrate
The vertical junction FET of claim 15 wherein the masking layer comprises a patterned oxide layer.
The vertical junction FET of claim 15 wherein the plurality of openings are characterized by a lateral width of between 2 p m and 10 pm.
The vertical junction FET of claim 15 wherein the second dislocation density is substantially equal to the first dislocation density.
The vertical junction FET of claim 15 wherein each of the one or more current flow channels are disposed between sets of the plurality of gate regions and the one or more second contacts overlie the one or more current flow channels.
The vertical junction FET of claim 15 wherein the first contact comprises a drain, the one or more second contacts comprise sources, and the plurality of third contacts comprise gates.
The vertical junction FET of claim 15 further comprising a regrowth interface between the plurality of gate regions and the epitaxial layer. 24.-32..
canceled
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canceled
Layer stacks claimed or described, ordered top of device to substrate.
diode
vertical junction FET
Materials described outside the worked examples.
semiconductor substrate
epitaxial layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3 is a simplified schematic diagram illustrating a conventional vertical junction field effect transistor; [0010]
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,093,395Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified schematic diagram illustrating a conventional Schottky barrier diode; [0008]
FIG. 2 is a simplified schematic diagram illustrating a conventional p-n junction diode; 5 [0009]
FIG. 3 is a simplified schematic diagram illustrating a conventional vertical junction field effect transistor; [0010]
FIG. 4 is a simplified schematic diagram illustrating a Schottky barrier diode with reduced defects according to an embodiment of the present invention; [0011]
FIG. 5 is a simplified schematic diagram illustrating a p-n junction diode with reduced 10 defects according to an embodiment of the present invention; [0012]
FIG. 6 is a simplified schematic diagram illustrating a vertical junction field effect transistor with reduced defects according to an embodiment of the present …
FIG. 7 is a simplified flowchart illustrating a method of fabricating an electronic structure with reduced defects according to an embodiment of the present …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A diode comprising: a substrate characterized by a first dislocation density and a first conductivity type; a first contact coupled to the substrate; a masking layer having a predetermined thickness and coupled to the semiconductor substrate, wherein the masking layer comprises a plurality of continuous sections and a plurality of openings exposing the substrate, wherein the openings are disposed between the continuous sections; an epitaxial layer greater than 5 p m thick coupled to the substrate and the masking layer, wherein the epitaxial layer comprises: a first set of regions overlying the plurality of openings and characterized by a second dislocation density; and a second set of regions overlying the set of continuous sections and characterized by a third dislocation density less than the first dislocation density and the second dislocation density; and a plurality of second contacts coupled to the epitaxial la y er, wherein each of the second contacts overlies a continuous section of the masking la v er, and wherein each continuous section of the masking la v er is overlied by more than one second contact.
The diode of claim 1 wherein the substrate comprises a GaN substrate and the first dislocation density is higher than 1 x 10 5 cm 2.
The diode of claim 1 wherein the first conductivity type comprises an n-type. Page 2 of 9 SVG 13225345.11-03-2014.I₂₂₇₈SEUPXXIFW3.CLM3397090.1.300.159.2249.242.svg 0.277 6.497 Graph Black and white Response to Office Action of
The diode of claim 1 wherein the epitaxial layer comprises one or more GaN-based layers.
The diode of claim 1 wherein the masking layer comprises a patterned oxide layer.
The diode of claim 1 wherein the plurality of openings are characterized by a lateral width of between 2 p m and 10 pm.
The diode of claim 1 wherein the second dislocation density is substantially equal to the first dislocation density.
The diode of claim 1 wherein the second contact overlies the second set of regions of the epitaxial layer.
The diode of claim 1 further comprising a coalescence boundary disposed in the second set of regions of the epitaxial layer.
The diode of claim 1 further comprising a second epitaxial layer of a second conductivity type opposite to the first conductivity type disposed between the epitaxial layer and the second contact.
The diode of claim 1 further wherein the second contact comprises a Schottky contact.
A vertical junction FET comprising: Page 3 of 9 SVG 13225345.11-03-2014.I₂₂₇₈SEUPXXIFW3.CLM3397091.1.300.159.2249.242.svg 0.277 6.497 Graph Black and white Response to Office Action of a substrate characterized by a first dislocation density and a first conductivity type; a first contact coupled to the substrate; a masking layer having a predetermined thickness and coupled to the semiconductor substrate, wherein the masking layer comprises a plurality of continuous sections of the predetermined thickness and a plurality of openings exposing the substrate, wherein the openings are disposed between the continuous sections; an epitaxial layer coupled to the substrate and the masking layer, wherein the epitaxial layer comprises: a first set of regions overlying the plurality of openings and characterized by a second dislocation density; and a second set of regions overlying the set of continuous sections and characterized by a third dislocation density less than the first dislocation density and the second dislocation density; a plurality of gate regions coupled to the epitaxial layer and defining one or more current flow channels; one or more second contacts coupled to the epitaxial layer, each of the one or more second contacts being adjacent one of the one or more current flow channels, wherein each of the second contacts overlies a corresponding one of the continuous sections of the masking layer, and wherein each continuous section of the masking la y er is overlied by more than one second contact; and a plurality of third contacts, each of the plurality of third contacts being coupled to one of the plurality of gate regions.
The vertical junction FET of claim 15 wherein the substrate comprises a I II -nitride substrate
The vertical junction FET of claim 15 wherein the masking layer comprises a patterned oxide layer.
The vertical junction FET of claim 15 wherein the plurality of openings are characterized by a lateral width of between 2 p m and 10 pm.
The vertical junction FET of claim 15 wherein the second dislocation density is substantially equal to the first dislocation density.
The vertical junction FET of claim 15 wherein each of the one or more current flow channels are disposed between sets of the plurality of gate regions and the one or more second contacts overlie the one or more current flow channels.
The vertical junction FET of claim 15 wherein the first contact comprises a drain, the one or more second contacts comprise sources, and the plurality of third contacts comprise gates.
The vertical junction FET of claim 15 further comprising a regrowth interface between the plurality of gate regions and the epitaxial layer. 24.-32..
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
Layer stacks claimed or described, ordered top of device to substrate.
diode
vertical junction FET
Materials described outside the worked examples.
semiconductor substrate
epitaxial layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3 is a simplified schematic diagram illustrating a conventional vertical junction field effect transistor; [0010]
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,093,395Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified schematic diagram illustrating a conventional Schottky barrier diode; [0008]
FIG. 2 is a simplified schematic diagram illustrating a conventional p-n junction diode; 5 [0009]
FIG. 3 is a simplified schematic diagram illustrating a conventional vertical junction field effect transistor; [0010]
FIG. 4 is a simplified schematic diagram illustrating a Schottky barrier diode with reduced defects according to an embodiment of the present invention; [0011]
FIG. 5 is a simplified schematic diagram illustrating a p-n junction diode with reduced 10 defects according to an embodiment of the present invention; [0012]
FIG. 6 is a simplified schematic diagram illustrating a vertical junction field effect transistor with reduced defects according to an embodiment of the present …
FIG. 7 is a simplified flowchart illustrating a method of fabricating an electronic structure with reduced defects according to an embodiment of the present …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A diode comprising: a substrate characterized by a first dislocation density and a first conductivity type; a first contact coupled to the substrate; a masking layer having a predetermined thickness and coupled to the semiconductor substrate, wherein the masking layer comprises a plurality of continuous sections and a plurality of openings exposing the substrate, wherein the openings are disposed between the continuous sections; an epitaxial layer greater than 5 p m thick coupled to the substrate and the masking layer, wherein the epitaxial layer comprises: a first set of regions overlying the plurality of openings and characterized by a second dislocation density; and a second set of regions overlying the set of continuous sections and characterized by a third dislocation density less than the first dislocation density and the second dislocation density; and a plurality of second contacts coupled to the epitaxial la y er, wherein each of the second contacts overlies a continuous section of the masking la v er, and wherein each continuous section of the masking la v er is overlied by more than one second contact.
The diode of claim 1 wherein the substrate comprises a GaN substrate and the first dislocation density is higher than 1 x 10 5 cm 2.
The diode of claim 1 wherein the first conductivity type comprises an n-type. Page 2 of 9 SVG 13225345.11-03-2014.I₂₂₇₈SEUPXXIFW3.CLM3397090.1.300.159.2249.242.svg 0.277 6.497 Graph Black and white Response to Office Action of
The diode of claim 1 wherein the epitaxial layer comprises one or more GaN-based layers.
The diode of claim 1 wherein the masking layer comprises a patterned oxide layer.
The diode of claim 1 wherein the plurality of openings are characterized by a lateral width of between 2 p m and 10 pm.
The diode of claim 1 wherein the second dislocation density is substantially equal to the first dislocation density.
The diode of claim 1 wherein the second contact overlies the second set of regions of the epitaxial layer.
The diode of claim 1 further comprising a coalescence boundary disposed in the second set of regions of the epitaxial layer.
The diode of claim 1 further comprising a second epitaxial layer of a second conductivity type opposite to the first conductivity type disposed between the epitaxial layer and the second contact.
The diode of claim 1 further wherein the second contact comprises a Schottky contact.
A vertical junction FET comprising: Page 3 of 9 SVG 13225345.11-03-2014.I₂₂₇₈SEUPXXIFW3.CLM3397091.1.300.159.2249.242.svg 0.277 6.497 Graph Black and white Response to Office Action of a substrate characterized by a first dislocation density and a first conductivity type; a first contact coupled to the substrate; a masking layer having a predetermined thickness and coupled to the semiconductor substrate, wherein the masking layer comprises a plurality of continuous sections of the predetermined thickness and a plurality of openings exposing the substrate, wherein the openings are disposed between the continuous sections; an epitaxial layer coupled to the substrate and the masking layer, wherein the epitaxial layer comprises: a first set of regions overlying the plurality of openings and characterized by a second dislocation density; and a second set of regions overlying the set of continuous sections and characterized by a third dislocation density less than the first dislocation density and the second dislocation density; a plurality of gate regions coupled to the epitaxial layer and defining one or more current flow channels; one or more second contacts coupled to the epitaxial layer, each of the one or more second contacts being adjacent one of the one or more current flow channels, wherein each of the second contacts overlies a corresponding one of the continuous sections of the masking layer, and wherein each continuous section of the masking la y er is overlied by more than one second contact; and a plurality of third contacts, each of the plurality of third contacts being coupled to one of the plurality of gate regions.
The vertical junction FET of claim 15 wherein the substrate comprises a I II -nitride substrate
The vertical junction FET of claim 15 wherein the masking layer comprises a patterned oxide layer.
The vertical junction FET of claim 15 wherein the plurality of openings are characterized by a lateral width of between 2 p m and 10 pm.
The vertical junction FET of claim 15 wherein the second dislocation density is substantially equal to the first dislocation density.
The vertical junction FET of claim 15 wherein each of the one or more current flow channels are disposed between sets of the plurality of gate regions and the one or more second contacts overlie the one or more current flow channels.
The vertical junction FET of claim 15 wherein the first contact comprises a drain, the one or more second contacts comprise sources, and the plurality of third contacts comprise gates.
The vertical junction FET of claim 15 further comprising a regrowth interface between the plurality of gate regions and the epitaxial layer. 24.-32..
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
Layer stacks claimed or described, ordered top of device to substrate.
diode
vertical junction FET
Materials described outside the worked examples.
semiconductor substrate
epitaxial layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3 is a simplified schematic diagram illustrating a conventional vertical junction field effect transistor; [0010]
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,093,395Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified schematic diagram illustrating a conventional Schottky barrier diode; [0008]
FIG. 2 is a simplified schematic diagram illustrating a conventional p-n junction diode; 5 [0009]
FIG. 3 is a simplified schematic diagram illustrating a conventional vertical junction field effect transistor; [0010]
FIG. 4 is a simplified schematic diagram illustrating a Schottky barrier diode with reduced defects according to an embodiment of the present invention; [0011]
FIG. 5 is a simplified schematic diagram illustrating a p-n junction diode with reduced 10 defects according to an embodiment of the present invention; [0012]
FIG. 6 is a simplified schematic diagram illustrating a vertical junction field effect transistor with reduced defects according to an embodiment of the present …
FIG. 7 is a simplified flowchart illustrating a method of fabricating an electronic structure with reduced defects according to an embodiment of the present …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A diode comprising: a substrate characterized by a first dislocation density and a first conductivity type; a first contact coupled to the substrate; a masking layer having a predetermined thickness and coupled to the semiconductor substrate, wherein the masking layer comprises a plurality of continuous sections and a plurality of openings exposing the substrate, wherein the openings are disposed between the continuous sections; an epitaxial layer greater than 5 p m thick coupled to the substrate and the masking layer, wherein the epitaxial layer comprises: a first set of regions overlying the plurality of openings and characterized by a second dislocation density; and a second set of regions overlying the set of continuous sections and characterized by a third dislocation density less than the first dislocation density and the second dislocation density; and a plurality of second contacts coupled to the epitaxial la y er, wherein each of the second contacts overlies a continuous section of the masking la v er, and wherein each continuous section of the masking la v er is overlied by more than one second contact.
The diode of claim 1 wherein the substrate comprises a GaN substrate and the first dislocation density is higher than 1 x 10 5 cm 2.
The diode of claim 1 wherein the first conductivity type comprises an n-type. Page 2 of 9 SVG 13225345.11-03-2014.I₂₂₇₈SEUPXXIFW3.CLM3397090.1.300.159.2249.242.svg 0.277 6.497 Graph Black and white Response to Office Action of
The diode of claim 1 wherein the epitaxial layer comprises one or more GaN-based layers.
The diode of claim 1 wherein the masking layer comprises a patterned oxide layer.
The diode of claim 1 wherein the plurality of openings are characterized by a lateral width of between 2 p m and 10 pm.
The diode of claim 1 wherein the second dislocation density is substantially equal to the first dislocation density.
The diode of claim 1 wherein the second contact overlies the second set of regions of the epitaxial layer.
The diode of claim 1 further comprising a coalescence boundary disposed in the second set of regions of the epitaxial layer.
The diode of claim 1 further comprising a second epitaxial layer of a second conductivity type opposite to the first conductivity type disposed between the epitaxial layer and the second contact.
The diode of claim 1 further wherein the second contact comprises a Schottky contact.
A vertical junction FET comprising: Page 3 of 9 SVG 13225345.11-03-2014.I₂₂₇₈SEUPXXIFW3.CLM3397091.1.300.159.2249.242.svg 0.277 6.497 Graph Black and white Response to Office Action of a substrate characterized by a first dislocation density and a first conductivity type; a first contact coupled to the substrate; a masking layer having a predetermined thickness and coupled to the semiconductor substrate, wherein the masking layer comprises a plurality of continuous sections of the predetermined thickness and a plurality of openings exposing the substrate, wherein the openings are disposed between the continuous sections; an epitaxial layer coupled to the substrate and the masking layer, wherein the epitaxial layer comprises: a first set of regions overlying the plurality of openings and characterized by a second dislocation density; and a second set of regions overlying the set of continuous sections and characterized by a third dislocation density less than the first dislocation density and the second dislocation density; a plurality of gate regions coupled to the epitaxial layer and defining one or more current flow channels; one or more second contacts coupled to the epitaxial layer, each of the one or more second contacts being adjacent one of the one or more current flow channels, wherein each of the second contacts overlies a corresponding one of the continuous sections of the masking layer, and wherein each continuous section of the masking la y er is overlied by more than one second contact; and a plurality of third contacts, each of the plurality of third contacts being coupled to one of the plurality of gate regions.
The vertical junction FET of claim 15 wherein the substrate comprises a I II -nitride substrate
The vertical junction FET of claim 15 wherein the masking layer comprises a patterned oxide layer.
The vertical junction FET of claim 15 wherein the plurality of openings are characterized by a lateral width of between 2 p m and 10 pm.
The vertical junction FET of claim 15 wherein the second dislocation density is substantially equal to the first dislocation density.
The vertical junction FET of claim 15 wherein each of the one or more current flow channels are disposed between sets of the plurality of gate regions and the one or more second contacts overlie the one or more current flow channels.
The vertical junction FET of claim 15 wherein the first contact comprises a drain, the one or more second contacts comprise sources, and the plurality of third contacts comprise gates.
The vertical junction FET of claim 15 further comprising a regrowth interface between the plurality of gate regions and the epitaxial layer. 24.-32..
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
Layer stacks claimed or described, ordered top of device to substrate.
diode
vertical junction FET
Materials described outside the worked examples.
semiconductor substrate
epitaxial layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3 is a simplified schematic diagram illustrating a conventional vertical junction field effect transistor; [0010]
Related documents with shared materials, methods, properties, or citations.
GaN substrate
GaN
GaN-based epitaxial layer
patterned oxide masking layer
III-nitride substrate
FIG. 6 is a simplified schematic diagram illustrating a vertical junction field effect transistor with reduced defects according to an embodiment of the present …
FIG. 7 is a simplified flowchart illustrating a method of fabricating an electronic structure with reduced defects according to an embodiment of the present …
GaN substrate
GaN
GaN-based epitaxial layer
patterned oxide masking layer
III-nitride substrate
FIG. 6 is a simplified schematic diagram illustrating a vertical junction field effect transistor with reduced defects according to an embodiment of the present …
FIG. 7 is a simplified flowchart illustrating a method of fabricating an electronic structure with reduced defects according to an embodiment of the present …
GaN substrate
GaN
GaN-based epitaxial layer
patterned oxide masking layer
III-nitride substrate
FIG. 6 is a simplified schematic diagram illustrating a vertical junction field effect transistor with reduced defects according to an embodiment of the present …
FIG. 7 is a simplified flowchart illustrating a method of fabricating an electronic structure with reduced defects according to an embodiment of the present …
GaN substrate
GaN
GaN-based epitaxial layer
patterned oxide masking layer
III-nitride substrate
FIG. 6 is a simplified schematic diagram illustrating a vertical junction field effect transistor with reduced defects according to an embodiment of the present …
FIG. 7 is a simplified flowchart illustrating a method of fabricating an electronic structure with reduced defects according to an embodiment of the present …
