P-GAN HIGH-ELECTRON-MOBILITY TRANSISTOR | Matter42 Literature
Patent
Atlas literature
Patent
US 12,218,230 B2
P-GAN HIGH-ELECTRON-MOBILITY TRANSISTOR
Ting-Chang Chang, Mao-Chou Tai, Yu-Xuan Wang, Wei-Chen Huang et al.
NATIONAL SUN YAT-SEN UNIVERSITY, Kaohsiung (TW)·Feb. 4, 2025·US
Drawings
Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1
FIG. 1 is a schematic diagram of a stacked structure according to a preferred embodiment of the present inven- tion.
FIG. 2
performance graph
FIG. 2 is a graph showing the relationship between the gate current and gate voltage of transistors in a preferred embodiment of the present invention and in …
Claims
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
Field of the Invention The present invention relates to an electronic device and, more particularly, to a p-GaN high-electron-mobility tran-sistor (HEMT) that can reduce gate leakage.
The p-GaN high-electron-mobility transistor as claimed in claim 1, wherein the first doped layer and the third doped layer are a p-GaN layer, and the second doped layer is a p+-GaN layer.
The p-GaN high-electron-mobility transistor as claimed in claim 1, wherein the first doped layer, the second doped layer and the third doped layer are formed by introducing a dopant during a deposition process, with the dopant being any one of alkaline earth metals. ∗ ∗ ∗ ∗ ∗
2
Independent
Description of the Related Art In response to the rapid development of technologies such as electric cars, base stations, and radio frequency commu-nication, the new generation of semiconductor devices needs to meet the requirements of high-power conversion, high-rate transmission, high bandwidth and low energy consump-tion. GaN has the characteristics of wide band gap, high breakdown voltage, high electron saturation velocity and good thermostability, and is accordingly an ideal semicon-ductor material. A high-electron-mobility transistor (HEMT) with GaN as the main material is a depletion-mode compo-nent that is conducted when no gate bias is applied, which poses a risk to safety in circuit application. Therefore, the GaN layer is doped in the conventional GaN-based HEMT to form a p-GaN layer, thus making the HEMT become an enhanced-mode element that capable of switching on or off by driving a gate. In order to effectively increase the energy band for enhancement, the conventional p-GaN HEMT will be highly doped to form a p+-GaN layer. However, in testing of reliability of the p+-GaN HEMT such as high temperature gate bias (HTGB) test and high temperature reverse bias (HTRB) test, as a result of an ohmic contact of the metal gate to the highly doped p+-GaN layer, hole tunneling occurs at the metal-semiconductor interface, resulting in severe leak-age current. In addition, due to the reverse bias, an extremely thin depletion region is formed between the highly doped p+-GaN layer and the AlGaN layer, causing direct tunneling of electrons, forming leakage current. Both of the foregoing tunnelings will cause the failure of transistor components. In light of the above, it is necessary to improve the conventional p-GaN HEMT. What is claimed is:
Device structures
Layer stacks claimed or described, ordered top of device to substrate.
p-GaN high-electron-mobility transistor (HEMT)
GaNthird doped layer low doping
GaNsecond doped layer high doping
GaNfirst doped layer low doping
AlGaNsupply layer
GaNchannel
Sisubstrate
Materials
Materials described outside the worked examples.
GaN channel layer
GaN
Channel Layer
First Doped Layer Low ConcentrationSecond Doped Layer High Concentration
AlGaN supply layer
AlGaN
Supply Layer
Characterization
Measurements and analyses referenced in the patent, with their drawing references.
fet electrical
Fet Electrical
FIG. 2 is a graph showing the relationship between the gate current and gate voltage of transistors in a preferred embodiment of the present invention and in …
Ting-Chang Chang, Mao-Chou Tai, Yu-Xuan Wang, Wei-Chen Huang et al.
NATIONAL SUN YAT-SEN UNIVERSITY, Kaohsiung (TW)·Feb. 4, 2025·US
Drawings
Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1
FIG. 1 is a schematic diagram of a stacked structure according to a preferred embodiment of the present inven- tion.
FIG. 2
performance graph
FIG. 2 is a graph showing the relationship between the gate current and gate voltage of transistors in a preferred embodiment of the present invention and in …
Claims
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
Field of the Invention The present invention relates to an electronic device and, more particularly, to a p-GaN high-electron-mobility tran-sistor (HEMT) that can reduce gate leakage.
The p-GaN high-electron-mobility transistor as claimed in claim 1, wherein the first doped layer and the third doped layer are a p-GaN layer, and the second doped layer is a p+-GaN layer.
The p-GaN high-electron-mobility transistor as claimed in claim 1, wherein the first doped layer, the second doped layer and the third doped layer are formed by introducing a dopant during a deposition process, with the dopant being any one of alkaline earth metals. ∗ ∗ ∗ ∗ ∗
2
Independent
Description of the Related Art In response to the rapid development of technologies such as electric cars, base stations, and radio frequency commu-nication, the new generation of semiconductor devices needs to meet the requirements of high-power conversion, high-rate transmission, high bandwidth and low energy consump-tion. GaN has the characteristics of wide band gap, high breakdown voltage, high electron saturation velocity and good thermostability, and is accordingly an ideal semicon-ductor material. A high-electron-mobility transistor (HEMT) with GaN as the main material is a depletion-mode compo-nent that is conducted when no gate bias is applied, which poses a risk to safety in circuit application. Therefore, the GaN layer is doped in the conventional GaN-based HEMT to form a p-GaN layer, thus making the HEMT become an enhanced-mode element that capable of switching on or off by driving a gate. In order to effectively increase the energy band for enhancement, the conventional p-GaN HEMT will be highly doped to form a p+-GaN layer. However, in testing of reliability of the p+-GaN HEMT such as high temperature gate bias (HTGB) test and high temperature reverse bias (HTRB) test, as a result of an ohmic contact of the metal gate to the highly doped p+-GaN layer, hole tunneling occurs at the metal-semiconductor interface, resulting in severe leak-age current. In addition, due to the reverse bias, an extremely thin depletion region is formed between the highly doped p+-GaN layer and the AlGaN layer, causing direct tunneling of electrons, forming leakage current. Both of the foregoing tunnelings will cause the failure of transistor components. In light of the above, it is necessary to improve the conventional p-GaN HEMT. What is claimed is:
Device structures
Layer stacks claimed or described, ordered top of device to substrate.
p-GaN high-electron-mobility transistor (HEMT)
GaNthird doped layer low doping
GaNsecond doped layer high doping
GaNfirst doped layer low doping
AlGaNsupply layer
GaNchannel
Sisubstrate
Materials
Materials described outside the worked examples.
GaN channel layer
GaN
Channel Layer
First Doped Layer Low ConcentrationSecond Doped Layer High Concentration
AlGaN supply layer
AlGaN
Supply Layer
Characterization
Measurements and analyses referenced in the patent, with their drawing references.
fet electrical
Fet Electrical
FIG. 2 is a graph showing the relationship between the gate current and gate voltage of transistors in a preferred embodiment of the present invention and in …
Ting-Chang Chang, Mao-Chou Tai, Yu-Xuan Wang, Wei-Chen Huang et al.
NATIONAL SUN YAT-SEN UNIVERSITY, Kaohsiung (TW)·Feb. 4, 2025·US
Drawings
Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1
FIG. 1 is a schematic diagram of a stacked structure according to a preferred embodiment of the present inven- tion.
FIG. 2
performance graph
FIG. 2 is a graph showing the relationship between the gate current and gate voltage of transistors in a preferred embodiment of the present invention and in …
Claims
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
Field of the Invention The present invention relates to an electronic device and, more particularly, to a p-GaN high-electron-mobility tran-sistor (HEMT) that can reduce gate leakage.
The p-GaN high-electron-mobility transistor as claimed in claim 1, wherein the first doped layer and the third doped layer are a p-GaN layer, and the second doped layer is a p+-GaN layer.
The p-GaN high-electron-mobility transistor as claimed in claim 1, wherein the first doped layer, the second doped layer and the third doped layer are formed by introducing a dopant during a deposition process, with the dopant being any one of alkaline earth metals. ∗ ∗ ∗ ∗ ∗
2
Independent
Description of the Related Art In response to the rapid development of technologies such as electric cars, base stations, and radio frequency commu-nication, the new generation of semiconductor devices needs to meet the requirements of high-power conversion, high-rate transmission, high bandwidth and low energy consump-tion. GaN has the characteristics of wide band gap, high breakdown voltage, high electron saturation velocity and good thermostability, and is accordingly an ideal semicon-ductor material. A high-electron-mobility transistor (HEMT) with GaN as the main material is a depletion-mode compo-nent that is conducted when no gate bias is applied, which poses a risk to safety in circuit application. Therefore, the GaN layer is doped in the conventional GaN-based HEMT to form a p-GaN layer, thus making the HEMT become an enhanced-mode element that capable of switching on or off by driving a gate. In order to effectively increase the energy band for enhancement, the conventional p-GaN HEMT will be highly doped to form a p+-GaN layer. However, in testing of reliability of the p+-GaN HEMT such as high temperature gate bias (HTGB) test and high temperature reverse bias (HTRB) test, as a result of an ohmic contact of the metal gate to the highly doped p+-GaN layer, hole tunneling occurs at the metal-semiconductor interface, resulting in severe leak-age current. In addition, due to the reverse bias, an extremely thin depletion region is formed between the highly doped p+-GaN layer and the AlGaN layer, causing direct tunneling of electrons, forming leakage current. Both of the foregoing tunnelings will cause the failure of transistor components. In light of the above, it is necessary to improve the conventional p-GaN HEMT. What is claimed is:
Device structures
Layer stacks claimed or described, ordered top of device to substrate.
p-GaN high-electron-mobility transistor (HEMT)
GaNthird doped layer low doping
GaNsecond doped layer high doping
GaNfirst doped layer low doping
AlGaNsupply layer
GaNchannel
Sisubstrate
Materials
Materials described outside the worked examples.
GaN channel layer
GaN
Channel Layer
First Doped Layer Low ConcentrationSecond Doped Layer High Concentration
AlGaN supply layer
AlGaN
Supply Layer
Characterization
Measurements and analyses referenced in the patent, with their drawing references.
fet electrical
Fet Electrical
FIG. 2 is a graph showing the relationship between the gate current and gate voltage of transistors in a preferred embodiment of the present invention and in …
Ting-Chang Chang, Mao-Chou Tai, Yu-Xuan Wang, Wei-Chen Huang et al.
NATIONAL SUN YAT-SEN UNIVERSITY, Kaohsiung (TW)·Feb. 4, 2025·US
Drawings
Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1
FIG. 1 is a schematic diagram of a stacked structure according to a preferred embodiment of the present inven- tion.
FIG. 2
performance graph
FIG. 2 is a graph showing the relationship between the gate current and gate voltage of transistors in a preferred embodiment of the present invention and in …
Claims
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
Field of the Invention The present invention relates to an electronic device and, more particularly, to a p-GaN high-electron-mobility tran-sistor (HEMT) that can reduce gate leakage.
The p-GaN high-electron-mobility transistor as claimed in claim 1, wherein the first doped layer and the third doped layer are a p-GaN layer, and the second doped layer is a p+-GaN layer.
The p-GaN high-electron-mobility transistor as claimed in claim 1, wherein the first doped layer, the second doped layer and the third doped layer are formed by introducing a dopant during a deposition process, with the dopant being any one of alkaline earth metals. ∗ ∗ ∗ ∗ ∗
2
Independent
Description of the Related Art In response to the rapid development of technologies such as electric cars, base stations, and radio frequency commu-nication, the new generation of semiconductor devices needs to meet the requirements of high-power conversion, high-rate transmission, high bandwidth and low energy consump-tion. GaN has the characteristics of wide band gap, high breakdown voltage, high electron saturation velocity and good thermostability, and is accordingly an ideal semicon-ductor material. A high-electron-mobility transistor (HEMT) with GaN as the main material is a depletion-mode compo-nent that is conducted when no gate bias is applied, which poses a risk to safety in circuit application. Therefore, the GaN layer is doped in the conventional GaN-based HEMT to form a p-GaN layer, thus making the HEMT become an enhanced-mode element that capable of switching on or off by driving a gate. In order to effectively increase the energy band for enhancement, the conventional p-GaN HEMT will be highly doped to form a p+-GaN layer. However, in testing of reliability of the p+-GaN HEMT such as high temperature gate bias (HTGB) test and high temperature reverse bias (HTRB) test, as a result of an ohmic contact of the metal gate to the highly doped p+-GaN layer, hole tunneling occurs at the metal-semiconductor interface, resulting in severe leak-age current. In addition, due to the reverse bias, an extremely thin depletion region is formed between the highly doped p+-GaN layer and the AlGaN layer, causing direct tunneling of electrons, forming leakage current. Both of the foregoing tunnelings will cause the failure of transistor components. In light of the above, it is necessary to improve the conventional p-GaN HEMT. What is claimed is:
Device structures
Layer stacks claimed or described, ordered top of device to substrate.
p-GaN high-electron-mobility transistor (HEMT)
GaNthird doped layer low doping
GaNsecond doped layer high doping
GaNfirst doped layer low doping
AlGaNsupply layer
GaNchannel
Sisubstrate
Materials
Materials described outside the worked examples.
GaN channel layer
GaN
Channel Layer
First Doped Layer Low ConcentrationSecond Doped Layer High Concentration
AlGaN supply layer
AlGaN
Supply Layer
Characterization
Measurements and analyses referenced in the patent, with their drawing references.
fet electrical
Fet Electrical
FIG. 2 is a graph showing the relationship between the gate current and gate voltage of transistors in a preferred embodiment of the present invention and in …
FIG. 2 is a graph showing the relationship between the gate current and gate voltage of transistors in a preferred embodiment of the present invention and in …
FIG. 2 is a graph showing the relationship between the gate current and gate voltage of transistors in a preferred embodiment of the present invention and in …
FIG. 2 is a graph showing the relationship between the gate current and gate voltage of transistors in a preferred embodiment of the present invention and in …
FIG. 2 is a graph showing the relationship between the gate current and gate voltage of transistors in a preferred embodiment of the present invention and in …