Patent
US 7,816,764METHOD OF CONTROLLING STRESS IN GALLIUM NITRIDE FILMS DEPOSITED ON SUBSTRATES
HUGUES MARCHAND, BRENDAN JUDE MORAN
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
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US 7,816,764Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic cross-sectional view illustrating the structure of the layers fabricated according to the general principles of this invention; [00 16]
FIG. 2 is an optical micrograph showing the surface morphology of a graded layer (Al N to GaN) deposited on a Si(111) substrate according to the present …
FIG. 3 is a cross-section view based on a transmission electron micrograph (TEM) illustrating the microstructure of a graded layer (A l N to GaN) deposited on …
FIG. 4 is a plan-view micrograph based on an atomic force microscopy (AFM) scan illustrating the surface morphology of a graded layer (A l N to GaN) deposited …
FIG. 5 is a simplified process flow diagram illustrating the sequence in which precursor chemicals are introduced in the growth chamber according to one example …
FIG. 6 is a schematic cross-sectional view illustrating the layers used to fabricate a field- effect transistor (FET) device according to one example of the …
FIG. 7 is a set of characteristic curves illustrating the performance of a field-effect transistor (FET) fabricated according to one example of the present …
FIG. 8 is an optical micrograph showing the surface morphology of a graded layer (Al N to GaN) deposited on a 6H-SiC substrate according to the present …
FIG. 9 is an optical micrograph showing the surface morphology of a GaN layer deposited on a 6H-SiC substrate according to a comparative example in the case …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor structure, comprising: a silicon substrate; and a single crystal group-I II nitride graded layer on the silicon substrate, wherein at room temperature the graded layer has a varying composition of a continuous grade from an initial composition to a final composition and a net compressive stress.
The semiconductor structure of claim 1, further comprising a device layer on a side of the single crystal group-I II nitride graded layer opposite to the silicon substrate.
-2- G&C 30794.79-US-C 1 9. The semiconductor structure of claim 1, wherein the continuous grade varies linearly.
The semiconductor structure of claim 1, wherein the continuous grade varies at a greater rate at a region proximate to the silicon substrate than distal from the substrate.
The semiconductor structure of claim 1, wherein the continuous grade varies at a slower rate at a region proximate to the silicon substrate than distal from the substrate.
The semiconductor structure of claim 1, wherein: a surface of the group-I II nitride graded layer has a dislocation density that is higher in a portion of the graded layer that is proximate to the silicon substrate than in a portion of the graded layer that is distal from the silicon substrate; and the structure further comprises a layer of GaN on an opposite side of the graded layer from the silicon substrate.
The semiconductor structure of claim 1, wherein: a surface of the group-I II nitride graded layer has a dislocation density that is between [[109-1010 cm⁻²]] 1 09-10 10 cm 2; and the structure further comprises a layer of GaN on an opposite side of the graded layer from the silicon substrate.
The semiconductor structure of claim 1, wherein: the graded layer has a total thickness of about 1 micron; and the structure further comprises layer of GaN on an opposite side of the graded gallium nitride layer from the silicon substrate.
The semiconductor structure of claim 1, wherein: the graded layer has a total thickness of about 1 micron; -3- G&C 30794.79-US-C 1 a portion of the layer closest to the silicon substrate is AlGaN and a portion of the layer furthest from the silicon substrate has less aluminum than the portion closest to the silicon substrate; and the grade is limited to between 20 to 80 % of the thickness of the layer.
The semiconductor structure of claim 1, wherein the graded layer is free of cracks.
A semiconductor structure, comprising: a silicon substrate; a single crystal group-I II nitride graded layer on the silicon substrate, wherein the graded layer has a varying composition of a continuous grade from an initial composition to a final composition and a net compressive stress; and a group-I II nitride device layer on a side of the graded layer opposite to the silicon substrate.
The semiconductor structure of claim 17, wherein the device layer includes at least a portion that is GaN.
The semiconductor structure of claim 17, wherein: the graded layer is free of cracks; and the device layer includes a plurality of layers and a transistor is formed in the plurality of layers.
The semiconductor structure of claim 17, wherein: the graded layer is free of cracks; and the device layer includes a plurality of layers and a diode is formed in the plurality of layers.
Layer stacks claimed or described, ordered top of device to substrate.
GaN-on-silicon semiconductor structure with graded nitride buffer
transistor formed in group-III nitride device layer on silicon
Materials described outside the worked examples.
silicon substrate
Si
single crystal group-III nitride graded layer
AlGaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3 is a cross-section view based on a transmission electron micrograph (TEM) illustrating the microstructure of a graded layer (A l N to GaN) deposited on …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
net stress in graded layer at room temperature | compressive | single crystal group-III nitride graded layer |
dislocation density range in graded nitride layer surface (claim 13) |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 7,816,764Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic cross-sectional view illustrating the structure of the layers fabricated according to the general principles of this invention; [00 16]
FIG. 2 is an optical micrograph showing the surface morphology of a graded layer (Al N to GaN) deposited on a Si(111) substrate according to the present …
FIG. 3 is a cross-section view based on a transmission electron micrograph (TEM) illustrating the microstructure of a graded layer (A l N to GaN) deposited on …
FIG. 4 is a plan-view micrograph based on an atomic force microscopy (AFM) scan illustrating the surface morphology of a graded layer (A l N to GaN) deposited …
FIG. 5 is a simplified process flow diagram illustrating the sequence in which precursor chemicals are introduced in the growth chamber according to one example …
FIG. 6 is a schematic cross-sectional view illustrating the layers used to fabricate a field- effect transistor (FET) device according to one example of the …
FIG. 7 is a set of characteristic curves illustrating the performance of a field-effect transistor (FET) fabricated according to one example of the present …
FIG. 8 is an optical micrograph showing the surface morphology of a graded layer (Al N to GaN) deposited on a 6H-SiC substrate according to the present …
FIG. 9 is an optical micrograph showing the surface morphology of a GaN layer deposited on a 6H-SiC substrate according to a comparative example in the case …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor structure, comprising: a silicon substrate; and a single crystal group-I II nitride graded layer on the silicon substrate, wherein at room temperature the graded layer has a varying composition of a continuous grade from an initial composition to a final composition and a net compressive stress.
The semiconductor structure of claim 1, further comprising a device layer on a side of the single crystal group-I II nitride graded layer opposite to the silicon substrate.
-2- G&C 30794.79-US-C 1 9. The semiconductor structure of claim 1, wherein the continuous grade varies linearly.
The semiconductor structure of claim 1, wherein the continuous grade varies at a greater rate at a region proximate to the silicon substrate than distal from the substrate.
The semiconductor structure of claim 1, wherein the continuous grade varies at a slower rate at a region proximate to the silicon substrate than distal from the substrate.
The semiconductor structure of claim 1, wherein: a surface of the group-I II nitride graded layer has a dislocation density that is higher in a portion of the graded layer that is proximate to the silicon substrate than in a portion of the graded layer that is distal from the silicon substrate; and the structure further comprises a layer of GaN on an opposite side of the graded layer from the silicon substrate.
The semiconductor structure of claim 1, wherein: a surface of the group-I II nitride graded layer has a dislocation density that is between [[109-1010 cm⁻²]] 1 09-10 10 cm 2; and the structure further comprises a layer of GaN on an opposite side of the graded layer from the silicon substrate.
The semiconductor structure of claim 1, wherein: the graded layer has a total thickness of about 1 micron; and the structure further comprises layer of GaN on an opposite side of the graded gallium nitride layer from the silicon substrate.
The semiconductor structure of claim 1, wherein: the graded layer has a total thickness of about 1 micron; -3- G&C 30794.79-US-C 1 a portion of the layer closest to the silicon substrate is AlGaN and a portion of the layer furthest from the silicon substrate has less aluminum than the portion closest to the silicon substrate; and the grade is limited to between 20 to 80 % of the thickness of the layer.
The semiconductor structure of claim 1, wherein the graded layer is free of cracks.
A semiconductor structure, comprising: a silicon substrate; a single crystal group-I II nitride graded layer on the silicon substrate, wherein the graded layer has a varying composition of a continuous grade from an initial composition to a final composition and a net compressive stress; and a group-I II nitride device layer on a side of the graded layer opposite to the silicon substrate.
The semiconductor structure of claim 17, wherein the device layer includes at least a portion that is GaN.
The semiconductor structure of claim 17, wherein: the graded layer is free of cracks; and the device layer includes a plurality of layers and a transistor is formed in the plurality of layers.
The semiconductor structure of claim 17, wherein: the graded layer is free of cracks; and the device layer includes a plurality of layers and a diode is formed in the plurality of layers.
Layer stacks claimed or described, ordered top of device to substrate.
GaN-on-silicon semiconductor structure with graded nitride buffer
transistor formed in group-III nitride device layer on silicon
Materials described outside the worked examples.
silicon substrate
Si
single crystal group-III nitride graded layer
AlGaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3 is a cross-section view based on a transmission electron micrograph (TEM) illustrating the microstructure of a graded layer (A l N to GaN) deposited on …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
net stress in graded layer at room temperature | compressive | single crystal group-III nitride graded layer |
dislocation density range in graded nitride layer surface (claim 13) |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 7,816,764Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic cross-sectional view illustrating the structure of the layers fabricated according to the general principles of this invention; [00 16]
FIG. 2 is an optical micrograph showing the surface morphology of a graded layer (Al N to GaN) deposited on a Si(111) substrate according to the present …
FIG. 3 is a cross-section view based on a transmission electron micrograph (TEM) illustrating the microstructure of a graded layer (A l N to GaN) deposited on …
FIG. 4 is a plan-view micrograph based on an atomic force microscopy (AFM) scan illustrating the surface morphology of a graded layer (A l N to GaN) deposited …
FIG. 5 is a simplified process flow diagram illustrating the sequence in which precursor chemicals are introduced in the growth chamber according to one example …
FIG. 6 is a schematic cross-sectional view illustrating the layers used to fabricate a field- effect transistor (FET) device according to one example of the …
FIG. 7 is a set of characteristic curves illustrating the performance of a field-effect transistor (FET) fabricated according to one example of the present …
FIG. 8 is an optical micrograph showing the surface morphology of a graded layer (Al N to GaN) deposited on a 6H-SiC substrate according to the present …
FIG. 9 is an optical micrograph showing the surface morphology of a GaN layer deposited on a 6H-SiC substrate according to a comparative example in the case …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor structure, comprising: a silicon substrate; and a single crystal group-I II nitride graded layer on the silicon substrate, wherein at room temperature the graded layer has a varying composition of a continuous grade from an initial composition to a final composition and a net compressive stress.
The semiconductor structure of claim 1, further comprising a device layer on a side of the single crystal group-I II nitride graded layer opposite to the silicon substrate.
-2- G&C 30794.79-US-C 1 9. The semiconductor structure of claim 1, wherein the continuous grade varies linearly.
The semiconductor structure of claim 1, wherein the continuous grade varies at a greater rate at a region proximate to the silicon substrate than distal from the substrate.
The semiconductor structure of claim 1, wherein the continuous grade varies at a slower rate at a region proximate to the silicon substrate than distal from the substrate.
The semiconductor structure of claim 1, wherein: a surface of the group-I II nitride graded layer has a dislocation density that is higher in a portion of the graded layer that is proximate to the silicon substrate than in a portion of the graded layer that is distal from the silicon substrate; and the structure further comprises a layer of GaN on an opposite side of the graded layer from the silicon substrate.
The semiconductor structure of claim 1, wherein: a surface of the group-I II nitride graded layer has a dislocation density that is between [[109-1010 cm⁻²]] 1 09-10 10 cm 2; and the structure further comprises a layer of GaN on an opposite side of the graded layer from the silicon substrate.
The semiconductor structure of claim 1, wherein: the graded layer has a total thickness of about 1 micron; and the structure further comprises layer of GaN on an opposite side of the graded gallium nitride layer from the silicon substrate.
The semiconductor structure of claim 1, wherein: the graded layer has a total thickness of about 1 micron; -3- G&C 30794.79-US-C 1 a portion of the layer closest to the silicon substrate is AlGaN and a portion of the layer furthest from the silicon substrate has less aluminum than the portion closest to the silicon substrate; and the grade is limited to between 20 to 80 % of the thickness of the layer.
The semiconductor structure of claim 1, wherein the graded layer is free of cracks.
A semiconductor structure, comprising: a silicon substrate; a single crystal group-I II nitride graded layer on the silicon substrate, wherein the graded layer has a varying composition of a continuous grade from an initial composition to a final composition and a net compressive stress; and a group-I II nitride device layer on a side of the graded layer opposite to the silicon substrate.
The semiconductor structure of claim 17, wherein the device layer includes at least a portion that is GaN.
The semiconductor structure of claim 17, wherein: the graded layer is free of cracks; and the device layer includes a plurality of layers and a transistor is formed in the plurality of layers.
The semiconductor structure of claim 17, wherein: the graded layer is free of cracks; and the device layer includes a plurality of layers and a diode is formed in the plurality of layers.
Layer stacks claimed or described, ordered top of device to substrate.
GaN-on-silicon semiconductor structure with graded nitride buffer
transistor formed in group-III nitride device layer on silicon
Materials described outside the worked examples.
silicon substrate
Si
single crystal group-III nitride graded layer
AlGaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3 is a cross-section view based on a transmission electron micrograph (TEM) illustrating the microstructure of a graded layer (A l N to GaN) deposited on …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
net stress in graded layer at room temperature | compressive | single crystal group-III nitride graded layer |
dislocation density range in graded nitride layer surface (claim 13) |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 7,816,764Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic cross-sectional view illustrating the structure of the layers fabricated according to the general principles of this invention; [00 16]
FIG. 2 is an optical micrograph showing the surface morphology of a graded layer (Al N to GaN) deposited on a Si(111) substrate according to the present …
FIG. 3 is a cross-section view based on a transmission electron micrograph (TEM) illustrating the microstructure of a graded layer (A l N to GaN) deposited on …
FIG. 4 is a plan-view micrograph based on an atomic force microscopy (AFM) scan illustrating the surface morphology of a graded layer (A l N to GaN) deposited …
FIG. 5 is a simplified process flow diagram illustrating the sequence in which precursor chemicals are introduced in the growth chamber according to one example …
FIG. 6 is a schematic cross-sectional view illustrating the layers used to fabricate a field- effect transistor (FET) device according to one example of the …
FIG. 7 is a set of characteristic curves illustrating the performance of a field-effect transistor (FET) fabricated according to one example of the present …
FIG. 8 is an optical micrograph showing the surface morphology of a graded layer (Al N to GaN) deposited on a 6H-SiC substrate according to the present …
FIG. 9 is an optical micrograph showing the surface morphology of a GaN layer deposited on a 6H-SiC substrate according to a comparative example in the case …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor structure, comprising: a silicon substrate; and a single crystal group-I II nitride graded layer on the silicon substrate, wherein at room temperature the graded layer has a varying composition of a continuous grade from an initial composition to a final composition and a net compressive stress.
The semiconductor structure of claim 1, further comprising a device layer on a side of the single crystal group-I II nitride graded layer opposite to the silicon substrate.
-2- G&C 30794.79-US-C 1 9. The semiconductor structure of claim 1, wherein the continuous grade varies linearly.
The semiconductor structure of claim 1, wherein the continuous grade varies at a greater rate at a region proximate to the silicon substrate than distal from the substrate.
The semiconductor structure of claim 1, wherein the continuous grade varies at a slower rate at a region proximate to the silicon substrate than distal from the substrate.
The semiconductor structure of claim 1, wherein: a surface of the group-I II nitride graded layer has a dislocation density that is higher in a portion of the graded layer that is proximate to the silicon substrate than in a portion of the graded layer that is distal from the silicon substrate; and the structure further comprises a layer of GaN on an opposite side of the graded layer from the silicon substrate.
The semiconductor structure of claim 1, wherein: a surface of the group-I II nitride graded layer has a dislocation density that is between [[109-1010 cm⁻²]] 1 09-10 10 cm 2; and the structure further comprises a layer of GaN on an opposite side of the graded layer from the silicon substrate.
The semiconductor structure of claim 1, wherein: the graded layer has a total thickness of about 1 micron; and the structure further comprises layer of GaN on an opposite side of the graded gallium nitride layer from the silicon substrate.
The semiconductor structure of claim 1, wherein: the graded layer has a total thickness of about 1 micron; -3- G&C 30794.79-US-C 1 a portion of the layer closest to the silicon substrate is AlGaN and a portion of the layer furthest from the silicon substrate has less aluminum than the portion closest to the silicon substrate; and the grade is limited to between 20 to 80 % of the thickness of the layer.
The semiconductor structure of claim 1, wherein the graded layer is free of cracks.
A semiconductor structure, comprising: a silicon substrate; a single crystal group-I II nitride graded layer on the silicon substrate, wherein the graded layer has a varying composition of a continuous grade from an initial composition to a final composition and a net compressive stress; and a group-I II nitride device layer on a side of the graded layer opposite to the silicon substrate.
The semiconductor structure of claim 17, wherein the device layer includes at least a portion that is GaN.
The semiconductor structure of claim 17, wherein: the graded layer is free of cracks; and the device layer includes a plurality of layers and a transistor is formed in the plurality of layers.
The semiconductor structure of claim 17, wherein: the graded layer is free of cracks; and the device layer includes a plurality of layers and a diode is formed in the plurality of layers.
Layer stacks claimed or described, ordered top of device to substrate.
GaN-on-silicon semiconductor structure with graded nitride buffer
transistor formed in group-III nitride device layer on silicon
Materials described outside the worked examples.
silicon substrate
Si
single crystal group-III nitride graded layer
AlGaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3 is a cross-section view based on a transmission electron micrograph (TEM) illustrating the microstructure of a graded layer (A l N to GaN) deposited on …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
net stress in graded layer at room temperature | compressive | single crystal group-III nitride graded layer |
dislocation density range in graded nitride layer surface (claim 13) |
Related documents with shared materials, methods, properties, or citations.
diode formed in group-III nitride device layer on silicon
GaN
AlN
Al0.5Ga0.5N
Al0.2Ga0.8N
FIG. 4 is a plan-view micrograph based on an atomic force microscopy (AFM) scan illustrating the surface morphology of a graded layer (A l N to GaN) deposited …
FIG. 6 is a schematic cross-sectional view illustrating the layers used to fabricate a field- effect transistor (FET) device according to one example of the …
FIG. 7 is a set of characteristic curves illustrating the performance of a field-effect transistor (FET) fabricated according to one example of the present …
FIG. 7 is a set of characteristic curves illustrating the performance of a field-effect transistor (FET) fabricated according to one example of the present …
single crystal group-III nitride graded layer |
total graded layer thickness (claim 14, 15) | ~1 micron | single crystal group-III nitride graded layer |
GaN film cracking threshold tensile stress (background) | ~400 MPa | GaN |
typical threading dislocation density for GaN on Si(111) with AlN buffer (background) | 3e9 cm⁻² | GaN |
Pressure | ≤ 950 MPa | — |
Thickness | ≥ 10 cm | — |
Thickness | 109–1010 cm | — |
Thickness | ≥ 5 µm | — |
diode formed in group-III nitride device layer on silicon
GaN
AlN
Al0.5Ga0.5N
Al0.2Ga0.8N
FIG. 4 is a plan-view micrograph based on an atomic force microscopy (AFM) scan illustrating the surface morphology of a graded layer (A l N to GaN) deposited …
FIG. 6 is a schematic cross-sectional view illustrating the layers used to fabricate a field- effect transistor (FET) device according to one example of the …
FIG. 7 is a set of characteristic curves illustrating the performance of a field-effect transistor (FET) fabricated according to one example of the present …
FIG. 7 is a set of characteristic curves illustrating the performance of a field-effect transistor (FET) fabricated according to one example of the present …
single crystal group-III nitride graded layer |
total graded layer thickness (claim 14, 15) | ~1 micron | single crystal group-III nitride graded layer |
GaN film cracking threshold tensile stress (background) | ~400 MPa | GaN |
typical threading dislocation density for GaN on Si(111) with AlN buffer (background) | 3e9 cm⁻² | GaN |
Pressure | ≤ 950 MPa | — |
Thickness | ≥ 10 cm | — |
Thickness | 109–1010 cm | — |
Thickness | ≥ 5 µm | — |
diode formed in group-III nitride device layer on silicon
GaN
AlN
Al0.5Ga0.5N
Al0.2Ga0.8N
FIG. 4 is a plan-view micrograph based on an atomic force microscopy (AFM) scan illustrating the surface morphology of a graded layer (A l N to GaN) deposited …
FIG. 6 is a schematic cross-sectional view illustrating the layers used to fabricate a field- effect transistor (FET) device according to one example of the …
FIG. 7 is a set of characteristic curves illustrating the performance of a field-effect transistor (FET) fabricated according to one example of the present …
FIG. 7 is a set of characteristic curves illustrating the performance of a field-effect transistor (FET) fabricated according to one example of the present …
single crystal group-III nitride graded layer |
total graded layer thickness (claim 14, 15) | ~1 micron | single crystal group-III nitride graded layer |
GaN film cracking threshold tensile stress (background) | ~400 MPa | GaN |
typical threading dislocation density for GaN on Si(111) with AlN buffer (background) | 3e9 cm⁻² | GaN |
Pressure | ≤ 950 MPa | — |
Thickness | ≥ 10 cm | — |
Thickness | 109–1010 cm | — |
Thickness | ≥ 5 µm | — |
diode formed in group-III nitride device layer on silicon
GaN
AlN
Al0.5Ga0.5N
Al0.2Ga0.8N
FIG. 4 is a plan-view micrograph based on an atomic force microscopy (AFM) scan illustrating the surface morphology of a graded layer (A l N to GaN) deposited …
FIG. 6 is a schematic cross-sectional view illustrating the layers used to fabricate a field- effect transistor (FET) device according to one example of the …
FIG. 7 is a set of characteristic curves illustrating the performance of a field-effect transistor (FET) fabricated according to one example of the present …
FIG. 7 is a set of characteristic curves illustrating the performance of a field-effect transistor (FET) fabricated according to one example of the present …
single crystal group-III nitride graded layer |
total graded layer thickness (claim 14, 15) | ~1 micron | single crystal group-III nitride graded layer |
GaN film cracking threshold tensile stress (background) | ~400 MPa | GaN |
typical threading dislocation density for GaN on Si(111) with AlN buffer (background) | 3e9 cm⁻² | GaN |
Pressure | ≤ 950 MPa | — |
Thickness | ≥ 10 cm | — |
Thickness | 109–1010 cm | — |
Thickness | ≥ 5 µm | — |