Patent
US 10,529,820METHOD FOR GALLIUM NITRIDE ON DIAMOND SEMICONDUCTOR WAFER PRODUCTION
Kanin Chu, Pane Chane Chao, Carlton T. Creamer
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 10,529,820Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A GaN on Diamond wafer, the system comprising: a diamond layer; a first layer of GaN bonded on said diamond layer at a low temperature, wherein said low temperature is below 400 degrees Celsius, said first layer of GaN being substantially free of a nucleation layer; a second GaN layer disposed on said first GaN layer; an AlGaN layer disposed on said second GaN layer, opposite said first GaN layer; and source, gate, drain, and passivation transistor elements disposed on said AlGaN layer; [[and]] a handling wafer disposed on said source, gate, drain, and passivation transistor elements; wherein said handling wafer is removed from said source, gate, drain, and passivation transistor elements following said bonding of said layer of GaN on said diamond layer; and at least one of passive components and transmission lines fabricated directly on said diamond layer, mitigating coefficient of thermal expansion mismatch [[;1.. Currently amended
The wafer of claim 1 wherein said second GaN layer is not greater than 0.2 p m thick. Previously presented
The wafer of claim 1 wherein coefficient of thermal expansion mismatch between said GaN layer and said diamond layer is minimized. Previously presented
The wafer of claim 1, further comprising GaN devices disposed on said layer of GaN prior to the bonding of said GaN layer to said diamond layer. Previously presented
(New) The method of claim 1, wherein said low temperature is below 150 degrees Celsius. New
Canceled
A method for manufacturing a GaN on Diamond device, the method comprising: providing a substrate; disposing a first GaN layer, using a low temperature polymer-based adhesive, on said substrate, having a nucleation layer disposed between said substrate and said first GaN layer; disposing a second GaN layer on said first GaN layer; disposing an AlGaN layer on said second GaN layer; disposing source, gate, drain, and passivation transistor ele m ents on said AlGaN layer; affixing said source, gate, drain, and passivation transistor elements to a handling wafer; removing said substrate and substantially all said nucleation layer; and bonding said GaN layer to a diamond layer [[.]]; and fabricating passive components and transmission lines directly on said diamond layer, thereby mitigating coefficient of thermal expansion mismatch. Currently amended
The method of claim 6 wherein said substrate material comprises Si. Previously presented
The method of claim 6 further comprising thinning said GaN layer prior to bonding said GaN device to said diamond layer. Previously presented
The method of claim 6, wherein: said substrate layer is about 600 m thick; said A l N nucleation layer is 200-2000 A; said first GaN layer is 1-3 m thick; said second GaN layer is 0.2-1.0 m thick; said AlGaN layer is 100-300 A thick; and said Diamond layer is 50-500 m thick. Previously presented
The method of claim 6 further comprising annealing said GaN layer bonded to said diamond layer. Previously presented
(Original) The method of claim 6 further comprising removing not more than 90% of said GaN layer. Original
(Previously Presented) The method of claim 6 wherein said step of rem oving said substrate and said substantially all said nucleation layer comprises mechanical removal. Previously presented
(Currently Amended) The method of claim 6, wherein said step of rem oving said substrate and said substantially all said nucleation layer further comprises etching and or mechanical polishing. Currently amended
(Previously Presented) The method of claim 6 wherein said handling wafer is attached to said GaN device with polymer-based adhesive. Previously presented
(Original) The method of claim 6 further comprising removing said handling wafer. Original
(Previously Presented) The method of claim 6 further comprising smoothing said diamond layer before bonding said GaN layer to said diamond substrate. Previously presented
(Previously Presented) The method of claim 6, wherein: said substrate layer is 600 m thick; said A l N nucleation layer is 500 A thick; said first GaN layer is 1.5 m thick; said second GaN layer is 0.2 m thick; said AlGaN layer is 190 A thick; said Diamond layer is 100 m thick; said Diamond layer is polished to a roughness of 0.5-3.0 nm RMS; and said first GaN layer is polished to less than 1 nm roughness. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
GaN-on-Diamond HEMT wafer
Materials described outside the worked examples.
diamond
C
GaN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
AlN nucleation layer thickness (claim range) | 200–2000 Angstrom | AlN |
first GaN layer thickness (claim range) | 1–3 um |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,529,820Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A GaN on Diamond wafer, the system comprising: a diamond layer; a first layer of GaN bonded on said diamond layer at a low temperature, wherein said low temperature is below 400 degrees Celsius, said first layer of GaN being substantially free of a nucleation layer; a second GaN layer disposed on said first GaN layer; an AlGaN layer disposed on said second GaN layer, opposite said first GaN layer; and source, gate, drain, and passivation transistor elements disposed on said AlGaN layer; [[and]] a handling wafer disposed on said source, gate, drain, and passivation transistor elements; wherein said handling wafer is removed from said source, gate, drain, and passivation transistor elements following said bonding of said layer of GaN on said diamond layer; and at least one of passive components and transmission lines fabricated directly on said diamond layer, mitigating coefficient of thermal expansion mismatch [[;1.. Currently amended
The wafer of claim 1 wherein said second GaN layer is not greater than 0.2 p m thick. Previously presented
The wafer of claim 1 wherein coefficient of thermal expansion mismatch between said GaN layer and said diamond layer is minimized. Previously presented
The wafer of claim 1, further comprising GaN devices disposed on said layer of GaN prior to the bonding of said GaN layer to said diamond layer. Previously presented
(New) The method of claim 1, wherein said low temperature is below 150 degrees Celsius. New
Canceled
A method for manufacturing a GaN on Diamond device, the method comprising: providing a substrate; disposing a first GaN layer, using a low temperature polymer-based adhesive, on said substrate, having a nucleation layer disposed between said substrate and said first GaN layer; disposing a second GaN layer on said first GaN layer; disposing an AlGaN layer on said second GaN layer; disposing source, gate, drain, and passivation transistor ele m ents on said AlGaN layer; affixing said source, gate, drain, and passivation transistor elements to a handling wafer; removing said substrate and substantially all said nucleation layer; and bonding said GaN layer to a diamond layer [[.]]; and fabricating passive components and transmission lines directly on said diamond layer, thereby mitigating coefficient of thermal expansion mismatch. Currently amended
The method of claim 6 wherein said substrate material comprises Si. Previously presented
The method of claim 6 further comprising thinning said GaN layer prior to bonding said GaN device to said diamond layer. Previously presented
The method of claim 6, wherein: said substrate layer is about 600 m thick; said A l N nucleation layer is 200-2000 A; said first GaN layer is 1-3 m thick; said second GaN layer is 0.2-1.0 m thick; said AlGaN layer is 100-300 A thick; and said Diamond layer is 50-500 m thick. Previously presented
The method of claim 6 further comprising annealing said GaN layer bonded to said diamond layer. Previously presented
(Original) The method of claim 6 further comprising removing not more than 90% of said GaN layer. Original
(Previously Presented) The method of claim 6 wherein said step of rem oving said substrate and said substantially all said nucleation layer comprises mechanical removal. Previously presented
(Currently Amended) The method of claim 6, wherein said step of rem oving said substrate and said substantially all said nucleation layer further comprises etching and or mechanical polishing. Currently amended
(Previously Presented) The method of claim 6 wherein said handling wafer is attached to said GaN device with polymer-based adhesive. Previously presented
(Original) The method of claim 6 further comprising removing said handling wafer. Original
(Previously Presented) The method of claim 6 further comprising smoothing said diamond layer before bonding said GaN layer to said diamond substrate. Previously presented
(Previously Presented) The method of claim 6, wherein: said substrate layer is 600 m thick; said A l N nucleation layer is 500 A thick; said first GaN layer is 1.5 m thick; said second GaN layer is 0.2 m thick; said AlGaN layer is 190 A thick; said Diamond layer is 100 m thick; said Diamond layer is polished to a roughness of 0.5-3.0 nm RMS; and said first GaN layer is polished to less than 1 nm roughness. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
GaN-on-Diamond HEMT wafer
Materials described outside the worked examples.
diamond
C
GaN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
AlN nucleation layer thickness (claim range) | 200–2000 Angstrom | AlN |
first GaN layer thickness (claim range) | 1–3 um |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,529,820Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A GaN on Diamond wafer, the system comprising: a diamond layer; a first layer of GaN bonded on said diamond layer at a low temperature, wherein said low temperature is below 400 degrees Celsius, said first layer of GaN being substantially free of a nucleation layer; a second GaN layer disposed on said first GaN layer; an AlGaN layer disposed on said second GaN layer, opposite said first GaN layer; and source, gate, drain, and passivation transistor elements disposed on said AlGaN layer; [[and]] a handling wafer disposed on said source, gate, drain, and passivation transistor elements; wherein said handling wafer is removed from said source, gate, drain, and passivation transistor elements following said bonding of said layer of GaN on said diamond layer; and at least one of passive components and transmission lines fabricated directly on said diamond layer, mitigating coefficient of thermal expansion mismatch [[;1.. Currently amended
The wafer of claim 1 wherein said second GaN layer is not greater than 0.2 p m thick. Previously presented
The wafer of claim 1 wherein coefficient of thermal expansion mismatch between said GaN layer and said diamond layer is minimized. Previously presented
The wafer of claim 1, further comprising GaN devices disposed on said layer of GaN prior to the bonding of said GaN layer to said diamond layer. Previously presented
(New) The method of claim 1, wherein said low temperature is below 150 degrees Celsius. New
Canceled
A method for manufacturing a GaN on Diamond device, the method comprising: providing a substrate; disposing a first GaN layer, using a low temperature polymer-based adhesive, on said substrate, having a nucleation layer disposed between said substrate and said first GaN layer; disposing a second GaN layer on said first GaN layer; disposing an AlGaN layer on said second GaN layer; disposing source, gate, drain, and passivation transistor ele m ents on said AlGaN layer; affixing said source, gate, drain, and passivation transistor elements to a handling wafer; removing said substrate and substantially all said nucleation layer; and bonding said GaN layer to a diamond layer [[.]]; and fabricating passive components and transmission lines directly on said diamond layer, thereby mitigating coefficient of thermal expansion mismatch. Currently amended
The method of claim 6 wherein said substrate material comprises Si. Previously presented
The method of claim 6 further comprising thinning said GaN layer prior to bonding said GaN device to said diamond layer. Previously presented
The method of claim 6, wherein: said substrate layer is about 600 m thick; said A l N nucleation layer is 200-2000 A; said first GaN layer is 1-3 m thick; said second GaN layer is 0.2-1.0 m thick; said AlGaN layer is 100-300 A thick; and said Diamond layer is 50-500 m thick. Previously presented
The method of claim 6 further comprising annealing said GaN layer bonded to said diamond layer. Previously presented
(Original) The method of claim 6 further comprising removing not more than 90% of said GaN layer. Original
(Previously Presented) The method of claim 6 wherein said step of rem oving said substrate and said substantially all said nucleation layer comprises mechanical removal. Previously presented
(Currently Amended) The method of claim 6, wherein said step of rem oving said substrate and said substantially all said nucleation layer further comprises etching and or mechanical polishing. Currently amended
(Previously Presented) The method of claim 6 wherein said handling wafer is attached to said GaN device with polymer-based adhesive. Previously presented
(Original) The method of claim 6 further comprising removing said handling wafer. Original
(Previously Presented) The method of claim 6 further comprising smoothing said diamond layer before bonding said GaN layer to said diamond substrate. Previously presented
(Previously Presented) The method of claim 6, wherein: said substrate layer is 600 m thick; said A l N nucleation layer is 500 A thick; said first GaN layer is 1.5 m thick; said second GaN layer is 0.2 m thick; said AlGaN layer is 190 A thick; said Diamond layer is 100 m thick; said Diamond layer is polished to a roughness of 0.5-3.0 nm RMS; and said first GaN layer is polished to less than 1 nm roughness. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
GaN-on-Diamond HEMT wafer
Materials described outside the worked examples.
diamond
C
GaN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
AlN nucleation layer thickness (claim range) | 200–2000 Angstrom | AlN |
first GaN layer thickness (claim range) | 1–3 um |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,529,820Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A GaN on Diamond wafer, the system comprising: a diamond layer; a first layer of GaN bonded on said diamond layer at a low temperature, wherein said low temperature is below 400 degrees Celsius, said first layer of GaN being substantially free of a nucleation layer; a second GaN layer disposed on said first GaN layer; an AlGaN layer disposed on said second GaN layer, opposite said first GaN layer; and source, gate, drain, and passivation transistor elements disposed on said AlGaN layer; [[and]] a handling wafer disposed on said source, gate, drain, and passivation transistor elements; wherein said handling wafer is removed from said source, gate, drain, and passivation transistor elements following said bonding of said layer of GaN on said diamond layer; and at least one of passive components and transmission lines fabricated directly on said diamond layer, mitigating coefficient of thermal expansion mismatch [[;1.. Currently amended
The wafer of claim 1 wherein said second GaN layer is not greater than 0.2 p m thick. Previously presented
The wafer of claim 1 wherein coefficient of thermal expansion mismatch between said GaN layer and said diamond layer is minimized. Previously presented
The wafer of claim 1, further comprising GaN devices disposed on said layer of GaN prior to the bonding of said GaN layer to said diamond layer. Previously presented
(New) The method of claim 1, wherein said low temperature is below 150 degrees Celsius. New
Canceled
A method for manufacturing a GaN on Diamond device, the method comprising: providing a substrate; disposing a first GaN layer, using a low temperature polymer-based adhesive, on said substrate, having a nucleation layer disposed between said substrate and said first GaN layer; disposing a second GaN layer on said first GaN layer; disposing an AlGaN layer on said second GaN layer; disposing source, gate, drain, and passivation transistor ele m ents on said AlGaN layer; affixing said source, gate, drain, and passivation transistor elements to a handling wafer; removing said substrate and substantially all said nucleation layer; and bonding said GaN layer to a diamond layer [[.]]; and fabricating passive components and transmission lines directly on said diamond layer, thereby mitigating coefficient of thermal expansion mismatch. Currently amended
The method of claim 6 wherein said substrate material comprises Si. Previously presented
The method of claim 6 further comprising thinning said GaN layer prior to bonding said GaN device to said diamond layer. Previously presented
The method of claim 6, wherein: said substrate layer is about 600 m thick; said A l N nucleation layer is 200-2000 A; said first GaN layer is 1-3 m thick; said second GaN layer is 0.2-1.0 m thick; said AlGaN layer is 100-300 A thick; and said Diamond layer is 50-500 m thick. Previously presented
The method of claim 6 further comprising annealing said GaN layer bonded to said diamond layer. Previously presented
(Original) The method of claim 6 further comprising removing not more than 90% of said GaN layer. Original
(Previously Presented) The method of claim 6 wherein said step of rem oving said substrate and said substantially all said nucleation layer comprises mechanical removal. Previously presented
(Currently Amended) The method of claim 6, wherein said step of rem oving said substrate and said substantially all said nucleation layer further comprises etching and or mechanical polishing. Currently amended
(Previously Presented) The method of claim 6 wherein said handling wafer is attached to said GaN device with polymer-based adhesive. Previously presented
(Original) The method of claim 6 further comprising removing said handling wafer. Original
(Previously Presented) The method of claim 6 further comprising smoothing said diamond layer before bonding said GaN layer to said diamond substrate. Previously presented
(Previously Presented) The method of claim 6, wherein: said substrate layer is 600 m thick; said A l N nucleation layer is 500 A thick; said first GaN layer is 1.5 m thick; said second GaN layer is 0.2 m thick; said AlGaN layer is 190 A thick; said Diamond layer is 100 m thick; said Diamond layer is polished to a roughness of 0.5-3.0 nm RMS; and said first GaN layer is polished to less than 1 nm roughness. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
GaN-on-Diamond HEMT wafer
Materials described outside the worked examples.
diamond
C
GaN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
AlN nucleation layer thickness (claim range) | 200–2000 Angstrom | AlN |
first GaN layer thickness (claim range) | 1–3 um |
Related documents with shared materials, methods, properties, or citations.
AlGaN
AlN nucleation layer
AlN
substrate
silicon substrate
Si
AlInN etch stop
AlInN
polymer-based adhesive
second GaN layer thickness (claim range) | 0.2–1 um | GaN |
AlGaN layer thickness (claim range) | 100–300 Angstrom | AlGaN |
Diamond layer thickness (claim range) | 50–500 um | C |
Diamond layer polished roughness (claim 20) | 0.5–3 nm RMS | C |
First GaN layer polished roughness (claim 20) | ≤ 1 nm RMS | GaN |
Thickness | 0.5–3 nm | — |
— | 1000–2500 W | — |
Temperature | ≤ 150 °C | — |
Temperature | ≤ 500 °C | — |
Thickness | ≤ 1 nm | — |
AlGaN
AlN nucleation layer
AlN
substrate
silicon substrate
Si
AlInN etch stop
AlInN
polymer-based adhesive
second GaN layer thickness (claim range) | 0.2–1 um | GaN |
AlGaN layer thickness (claim range) | 100–300 Angstrom | AlGaN |
Diamond layer thickness (claim range) | 50–500 um | C |
Diamond layer polished roughness (claim 20) | 0.5–3 nm RMS | C |
First GaN layer polished roughness (claim 20) | ≤ 1 nm RMS | GaN |
Thickness | 0.5–3 nm | — |
— | 1000–2500 W | — |
Temperature | ≤ 150 °C | — |
Temperature | ≤ 500 °C | — |
Thickness | ≤ 1 nm | — |
AlGaN
AlN nucleation layer
AlN
substrate
silicon substrate
Si
AlInN etch stop
AlInN
polymer-based adhesive
second GaN layer thickness (claim range) | 0.2–1 um | GaN |
AlGaN layer thickness (claim range) | 100–300 Angstrom | AlGaN |
Diamond layer thickness (claim range) | 50–500 um | C |
Diamond layer polished roughness (claim 20) | 0.5–3 nm RMS | C |
First GaN layer polished roughness (claim 20) | ≤ 1 nm RMS | GaN |
Thickness | 0.5–3 nm | — |
— | 1000–2500 W | — |
Temperature | ≤ 150 °C | — |
Temperature | ≤ 500 °C | — |
Thickness | ≤ 1 nm | — |
AlGaN
AlN nucleation layer
AlN
substrate
silicon substrate
Si
AlInN etch stop
AlInN
polymer-based adhesive
second GaN layer thickness (claim range) | 0.2–1 um | GaN |
AlGaN layer thickness (claim range) | 100–300 Angstrom | AlGaN |
Diamond layer thickness (claim range) | 50–500 um | C |
Diamond layer polished roughness (claim 20) | 0.5–3 nm RMS | C |
First GaN layer polished roughness (claim 20) | ≤ 1 nm RMS | GaN |
Thickness | 0.5–3 nm | — |
— | 1000–2500 W | — |
Temperature | ≤ 150 °C | — |
Temperature | ≤ 500 °C | — |
Thickness | ≤ 1 nm | — |