Patent
US 10,256,294VERTICAL GALLIUM NITRIDE POWER FIELD-EFFECT TRANSISTOR WITH A FIELD PLATE STRUCTURE
Subrahmanyam V. Pilla
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 10,256,294Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 shows a conventional vertical gallium nitride power FET with a thick region formed of pi p-type graded AIGaN. 15
Figure 2 shows an exemplary vertical gallium nitride power FET with a field plate structure, which includes a thin layer formed of pi p-type graded AIGaN and a thin layer formed of p-type GaN.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
The GaN power FET of claim 1 further comprising a conducting layer between the gate dielectric region and the channel region, wherein the conducting layer is formed of AlGaN. Original
The GaN power FET of claim 2 wherein a thickness of the conducting layer is between 5 nms and 10 nms. Original
The GaN power FET of claim 1 wherein the drift region is formed of GaN and essentially free of aluminum content. Previously presented
The GaN power FET of claim 4 wherein a thickness of the drift region is between 5 p ms and 9 p ms. Original
The GaN power FET of claim 1 wherein the drift region is formed of graded AlGaN, where a percentage of aluminum in the graded AlGaN of the drift region decreases from no more than 5% to 0% from a top to a bottom of the drift region. Original
The GaN power FET of claim 1 wherein the recess of the drift region has a depth between nms and 200 nms. Original
The GaN power FET of claim 1 wherein a thickness of the upper layer of the field plate structure is between 50 nms and 300 nms Original
The GaN power FET of claim 1 wherein a thickness of the upper layer of the field plate structure is between 175 nms and 225 nms. Original
The GaN power FET of claim 1 wherein a thickness of the lower layer of the field plate structure is no more than 125 nms. Original
The GaN power FET of claim 1 wherein the percentage of the aluminum in the graded AlGaN of the lower layer decreases from no more than 20% to 0% from the bottom to the top of the lower layer. Original
The GaN power FET of claim 1 wherein the channel region has tapered side walls such that a width of the channel region decreases from an upper portion to a lower portion of the channel region. Original
The GaN power FET of claim 12 wherein an angle formed between the tapered side walls and a vertical plane that is orthogonal to a plane in which the conductive substrate resides is between 15 degrees and 45 degrees. Original
The GaN power FET of claim 12 wherein an angle formed between the tapered side walls and a vertical plane that is orthogonal to a plane in which the conductive substrate resides is between 23 degrees and 28 degrees. Original
The GaN power FET of claim 1 wherein the conductive substrate, the drift region, and the channel region are doped with an n-type dopant, and the upper layer and the lower layer of the field plate structure are doped with a p-type dopant. Original
The GaN power FET of claim 15 wherein a density of the p-type dopant within the lower layer is greater than a density of the p-type dopant within the upper layer. Original
The GaN power FET of claim 15 wherein a density of the n-type dopant within the channel region is no more than 5x10 16/cm 3 SVG 15053715.05-29-2018.JHS₄₃₈ZLRXEAPX0.CLM.2.svg 0.44 5.95 Black and white * a conductive substrate; * a drift region residing over a top surface of the conductive substrate and having a recess; * a field plate structure residing over the drift region and comprising a lower layer formed of graded indium gallium nitride (InGaN) over the drift region, and an upper layer formed of non-graded GaN and essentially free of indium content over the lower layer, wherein-0 the lower layer and the upper layer are doped with a same polarity of dopants; 0 the lower layer and the upper layer have different dopant densities; and 0 a percentage of indium in the InGaN of the lower layer decreases from no more than 33% to 0% from a bottom to a top of the lower layer; * a channel region extending vertically through the field plate structure and into the recess, wherein surr ounded by the upper layer and the lower layer region over the channel region; * a gate contact over the upper layer of the field plate structure; * conductive substrate; and ohmic contact regions of the field plate structure, wherein the source plate structure are doped with different polarities the channel region is formed of GaN and directly of the field plate structure; * a gate dielectric over the gate dielectric region; * source contacts a drain contact over a bottom surface of the and source contact regions within the upper layer contact regions and the upper layer of the field of dopants. Original
Layer stacks claimed or described, ordered top of device to substrate.
vertical GaN power FET with AlGaN/GaN field plate structure
vertical GaN power FET with InGaN/GaN field plate structure
Materials described outside the worked examples.
p-type GaN (upper layer of field plate structure)
GaN
AlGaN conducting layer
AlGaN
Measurements and analyses referenced in the patent, with their drawing references.
Figure 1 shows a conventional vertical gallium nitride power FET with a thick region formed of pi p-type graded AIGaN. 15
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
breakdown voltage target | ≥ 1000 | — |
Thickness | ≤ 125 nm |
Related documents with shared materials, methods, properties, or citations.
METHOD AND APPARATUS TO MODEL AND MONITOR TIME DEPENDENT DIELECTRIC BREAKDOWN IN MULTI-FIELD PLATE GALLIUM NITRIDE DEVICES
FOLDED CHANNEL GALLIUM NITRIDE BASED FIELD-EFFECT TRANSISTOR AND METHOD OF MANUFACTURING THE SAME
Patent
Atlas literature
Patent
US 10,256,294Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 shows a conventional vertical gallium nitride power FET with a thick region formed of pi p-type graded AIGaN. 15
Figure 2 shows an exemplary vertical gallium nitride power FET with a field plate structure, which includes a thin layer formed of pi p-type graded AIGaN and a thin layer formed of p-type GaN.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
The GaN power FET of claim 1 further comprising a conducting layer between the gate dielectric region and the channel region, wherein the conducting layer is formed of AlGaN. Original
The GaN power FET of claim 2 wherein a thickness of the conducting layer is between 5 nms and 10 nms. Original
The GaN power FET of claim 1 wherein the drift region is formed of GaN and essentially free of aluminum content. Previously presented
The GaN power FET of claim 4 wherein a thickness of the drift region is between 5 p ms and 9 p ms. Original
The GaN power FET of claim 1 wherein the drift region is formed of graded AlGaN, where a percentage of aluminum in the graded AlGaN of the drift region decreases from no more than 5% to 0% from a top to a bottom of the drift region. Original
The GaN power FET of claim 1 wherein the recess of the drift region has a depth between nms and 200 nms. Original
The GaN power FET of claim 1 wherein a thickness of the upper layer of the field plate structure is between 50 nms and 300 nms Original
The GaN power FET of claim 1 wherein a thickness of the upper layer of the field plate structure is between 175 nms and 225 nms. Original
The GaN power FET of claim 1 wherein a thickness of the lower layer of the field plate structure is no more than 125 nms. Original
The GaN power FET of claim 1 wherein the percentage of the aluminum in the graded AlGaN of the lower layer decreases from no more than 20% to 0% from the bottom to the top of the lower layer. Original
The GaN power FET of claim 1 wherein the channel region has tapered side walls such that a width of the channel region decreases from an upper portion to a lower portion of the channel region. Original
The GaN power FET of claim 12 wherein an angle formed between the tapered side walls and a vertical plane that is orthogonal to a plane in which the conductive substrate resides is between 15 degrees and 45 degrees. Original
The GaN power FET of claim 12 wherein an angle formed between the tapered side walls and a vertical plane that is orthogonal to a plane in which the conductive substrate resides is between 23 degrees and 28 degrees. Original
The GaN power FET of claim 1 wherein the conductive substrate, the drift region, and the channel region are doped with an n-type dopant, and the upper layer and the lower layer of the field plate structure are doped with a p-type dopant. Original
The GaN power FET of claim 15 wherein a density of the p-type dopant within the lower layer is greater than a density of the p-type dopant within the upper layer. Original
The GaN power FET of claim 15 wherein a density of the n-type dopant within the channel region is no more than 5x10 16/cm 3 SVG 15053715.05-29-2018.JHS₄₃₈ZLRXEAPX0.CLM.2.svg 0.44 5.95 Black and white * a conductive substrate; * a drift region residing over a top surface of the conductive substrate and having a recess; * a field plate structure residing over the drift region and comprising a lower layer formed of graded indium gallium nitride (InGaN) over the drift region, and an upper layer formed of non-graded GaN and essentially free of indium content over the lower layer, wherein-0 the lower layer and the upper layer are doped with a same polarity of dopants; 0 the lower layer and the upper layer have different dopant densities; and 0 a percentage of indium in the InGaN of the lower layer decreases from no more than 33% to 0% from a bottom to a top of the lower layer; * a channel region extending vertically through the field plate structure and into the recess, wherein surr ounded by the upper layer and the lower layer region over the channel region; * a gate contact over the upper layer of the field plate structure; * conductive substrate; and ohmic contact regions of the field plate structure, wherein the source plate structure are doped with different polarities the channel region is formed of GaN and directly of the field plate structure; * a gate dielectric over the gate dielectric region; * source contacts a drain contact over a bottom surface of the and source contact regions within the upper layer contact regions and the upper layer of the field of dopants. Original
Layer stacks claimed or described, ordered top of device to substrate.
vertical GaN power FET with AlGaN/GaN field plate structure
vertical GaN power FET with InGaN/GaN field plate structure
Materials described outside the worked examples.
p-type GaN (upper layer of field plate structure)
GaN
AlGaN conducting layer
AlGaN
Measurements and analyses referenced in the patent, with their drawing references.
Figure 1 shows a conventional vertical gallium nitride power FET with a thick region formed of pi p-type graded AIGaN. 15
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
breakdown voltage target | ≥ 1000 | — |
Thickness | ≤ 125 nm |
Related documents with shared materials, methods, properties, or citations.
METHOD AND APPARATUS TO MODEL AND MONITOR TIME DEPENDENT DIELECTRIC BREAKDOWN IN MULTI-FIELD PLATE GALLIUM NITRIDE DEVICES
FOLDED CHANNEL GALLIUM NITRIDE BASED FIELD-EFFECT TRANSISTOR AND METHOD OF MANUFACTURING THE SAME
Patent
Atlas literature
Patent
US 10,256,294Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 shows a conventional vertical gallium nitride power FET with a thick region formed of pi p-type graded AIGaN. 15
Figure 2 shows an exemplary vertical gallium nitride power FET with a field plate structure, which includes a thin layer formed of pi p-type graded AIGaN and a thin layer formed of p-type GaN.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
The GaN power FET of claim 1 further comprising a conducting layer between the gate dielectric region and the channel region, wherein the conducting layer is formed of AlGaN. Original
The GaN power FET of claim 2 wherein a thickness of the conducting layer is between 5 nms and 10 nms. Original
The GaN power FET of claim 1 wherein the drift region is formed of GaN and essentially free of aluminum content. Previously presented
The GaN power FET of claim 4 wherein a thickness of the drift region is between 5 p ms and 9 p ms. Original
The GaN power FET of claim 1 wherein the drift region is formed of graded AlGaN, where a percentage of aluminum in the graded AlGaN of the drift region decreases from no more than 5% to 0% from a top to a bottom of the drift region. Original
The GaN power FET of claim 1 wherein the recess of the drift region has a depth between nms and 200 nms. Original
The GaN power FET of claim 1 wherein a thickness of the upper layer of the field plate structure is between 50 nms and 300 nms Original
The GaN power FET of claim 1 wherein a thickness of the upper layer of the field plate structure is between 175 nms and 225 nms. Original
The GaN power FET of claim 1 wherein a thickness of the lower layer of the field plate structure is no more than 125 nms. Original
The GaN power FET of claim 1 wherein the percentage of the aluminum in the graded AlGaN of the lower layer decreases from no more than 20% to 0% from the bottom to the top of the lower layer. Original
The GaN power FET of claim 1 wherein the channel region has tapered side walls such that a width of the channel region decreases from an upper portion to a lower portion of the channel region. Original
The GaN power FET of claim 12 wherein an angle formed between the tapered side walls and a vertical plane that is orthogonal to a plane in which the conductive substrate resides is between 15 degrees and 45 degrees. Original
The GaN power FET of claim 12 wherein an angle formed between the tapered side walls and a vertical plane that is orthogonal to a plane in which the conductive substrate resides is between 23 degrees and 28 degrees. Original
The GaN power FET of claim 1 wherein the conductive substrate, the drift region, and the channel region are doped with an n-type dopant, and the upper layer and the lower layer of the field plate structure are doped with a p-type dopant. Original
The GaN power FET of claim 15 wherein a density of the p-type dopant within the lower layer is greater than a density of the p-type dopant within the upper layer. Original
The GaN power FET of claim 15 wherein a density of the n-type dopant within the channel region is no more than 5x10 16/cm 3 SVG 15053715.05-29-2018.JHS₄₃₈ZLRXEAPX0.CLM.2.svg 0.44 5.95 Black and white * a conductive substrate; * a drift region residing over a top surface of the conductive substrate and having a recess; * a field plate structure residing over the drift region and comprising a lower layer formed of graded indium gallium nitride (InGaN) over the drift region, and an upper layer formed of non-graded GaN and essentially free of indium content over the lower layer, wherein-0 the lower layer and the upper layer are doped with a same polarity of dopants; 0 the lower layer and the upper layer have different dopant densities; and 0 a percentage of indium in the InGaN of the lower layer decreases from no more than 33% to 0% from a bottom to a top of the lower layer; * a channel region extending vertically through the field plate structure and into the recess, wherein surr ounded by the upper layer and the lower layer region over the channel region; * a gate contact over the upper layer of the field plate structure; * conductive substrate; and ohmic contact regions of the field plate structure, wherein the source plate structure are doped with different polarities the channel region is formed of GaN and directly of the field plate structure; * a gate dielectric over the gate dielectric region; * source contacts a drain contact over a bottom surface of the and source contact regions within the upper layer contact regions and the upper layer of the field of dopants. Original
Layer stacks claimed or described, ordered top of device to substrate.
vertical GaN power FET with AlGaN/GaN field plate structure
vertical GaN power FET with InGaN/GaN field plate structure
Materials described outside the worked examples.
p-type GaN (upper layer of field plate structure)
GaN
AlGaN conducting layer
AlGaN
Measurements and analyses referenced in the patent, with their drawing references.
Figure 1 shows a conventional vertical gallium nitride power FET with a thick region formed of pi p-type graded AIGaN. 15
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
breakdown voltage target | ≥ 1000 | — |
Thickness | ≤ 125 nm |
Related documents with shared materials, methods, properties, or citations.
METHOD AND APPARATUS TO MODEL AND MONITOR TIME DEPENDENT DIELECTRIC BREAKDOWN IN MULTI-FIELD PLATE GALLIUM NITRIDE DEVICES
FOLDED CHANNEL GALLIUM NITRIDE BASED FIELD-EFFECT TRANSISTOR AND METHOD OF MANUFACTURING THE SAME
Patent
Atlas literature
Patent
US 10,256,294Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 shows a conventional vertical gallium nitride power FET with a thick region formed of pi p-type graded AIGaN. 15
Figure 2 shows an exemplary vertical gallium nitride power FET with a field plate structure, which includes a thin layer formed of pi p-type graded AIGaN and a thin layer formed of p-type GaN.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
The GaN power FET of claim 1 further comprising a conducting layer between the gate dielectric region and the channel region, wherein the conducting layer is formed of AlGaN. Original
The GaN power FET of claim 2 wherein a thickness of the conducting layer is between 5 nms and 10 nms. Original
The GaN power FET of claim 1 wherein the drift region is formed of GaN and essentially free of aluminum content. Previously presented
The GaN power FET of claim 4 wherein a thickness of the drift region is between 5 p ms and 9 p ms. Original
The GaN power FET of claim 1 wherein the drift region is formed of graded AlGaN, where a percentage of aluminum in the graded AlGaN of the drift region decreases from no more than 5% to 0% from a top to a bottom of the drift region. Original
The GaN power FET of claim 1 wherein the recess of the drift region has a depth between nms and 200 nms. Original
The GaN power FET of claim 1 wherein a thickness of the upper layer of the field plate structure is between 50 nms and 300 nms Original
The GaN power FET of claim 1 wherein a thickness of the upper layer of the field plate structure is between 175 nms and 225 nms. Original
The GaN power FET of claim 1 wherein a thickness of the lower layer of the field plate structure is no more than 125 nms. Original
The GaN power FET of claim 1 wherein the percentage of the aluminum in the graded AlGaN of the lower layer decreases from no more than 20% to 0% from the bottom to the top of the lower layer. Original
The GaN power FET of claim 1 wherein the channel region has tapered side walls such that a width of the channel region decreases from an upper portion to a lower portion of the channel region. Original
The GaN power FET of claim 12 wherein an angle formed between the tapered side walls and a vertical plane that is orthogonal to a plane in which the conductive substrate resides is between 15 degrees and 45 degrees. Original
The GaN power FET of claim 12 wherein an angle formed between the tapered side walls and a vertical plane that is orthogonal to a plane in which the conductive substrate resides is between 23 degrees and 28 degrees. Original
The GaN power FET of claim 1 wherein the conductive substrate, the drift region, and the channel region are doped with an n-type dopant, and the upper layer and the lower layer of the field plate structure are doped with a p-type dopant. Original
The GaN power FET of claim 15 wherein a density of the p-type dopant within the lower layer is greater than a density of the p-type dopant within the upper layer. Original
The GaN power FET of claim 15 wherein a density of the n-type dopant within the channel region is no more than 5x10 16/cm 3 SVG 15053715.05-29-2018.JHS₄₃₈ZLRXEAPX0.CLM.2.svg 0.44 5.95 Black and white * a conductive substrate; * a drift region residing over a top surface of the conductive substrate and having a recess; * a field plate structure residing over the drift region and comprising a lower layer formed of graded indium gallium nitride (InGaN) over the drift region, and an upper layer formed of non-graded GaN and essentially free of indium content over the lower layer, wherein-0 the lower layer and the upper layer are doped with a same polarity of dopants; 0 the lower layer and the upper layer have different dopant densities; and 0 a percentage of indium in the InGaN of the lower layer decreases from no more than 33% to 0% from a bottom to a top of the lower layer; * a channel region extending vertically through the field plate structure and into the recess, wherein surr ounded by the upper layer and the lower layer region over the channel region; * a gate contact over the upper layer of the field plate structure; * conductive substrate; and ohmic contact regions of the field plate structure, wherein the source plate structure are doped with different polarities the channel region is formed of GaN and directly of the field plate structure; * a gate dielectric over the gate dielectric region; * source contacts a drain contact over a bottom surface of the and source contact regions within the upper layer contact regions and the upper layer of the field of dopants. Original
Layer stacks claimed or described, ordered top of device to substrate.
vertical GaN power FET with AlGaN/GaN field plate structure
vertical GaN power FET with InGaN/GaN field plate structure
Materials described outside the worked examples.
p-type GaN (upper layer of field plate structure)
GaN
AlGaN conducting layer
AlGaN
Measurements and analyses referenced in the patent, with their drawing references.
Figure 1 shows a conventional vertical gallium nitride power FET with a thick region formed of pi p-type graded AIGaN. 15
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
breakdown voltage target | ≥ 1000 | — |
Thickness | ≤ 125 nm |
Related documents with shared materials, methods, properties, or citations.
METHOD AND APPARATUS TO MODEL AND MONITOR TIME DEPENDENT DIELECTRIC BREAKDOWN IN MULTI-FIELD PLATE GALLIUM NITRIDE DEVICES
FOLDED CHANNEL GALLIUM NITRIDE BASED FIELD-EFFECT TRANSISTOR AND METHOD OF MANUFACTURING THE SAME
graded InGaN (lower layer of field plate structure, alternative embodiment)
InGaN
Figure 2 shows an exemplary vertical gallium nitride power FET with a field plate structure, which includes a thin layer formed of pi p-type graded AIGaN and a thin layer formed of p-type GaN.
| — |
Thickness | ≥ 125 nm | — |
graded InGaN (lower layer of field plate structure, alternative embodiment)
InGaN
Figure 2 shows an exemplary vertical gallium nitride power FET with a field plate structure, which includes a thin layer formed of pi p-type graded AIGaN and a thin layer formed of p-type GaN.
| — |
Thickness | ≥ 125 nm | — |
graded InGaN (lower layer of field plate structure, alternative embodiment)
InGaN
Figure 2 shows an exemplary vertical gallium nitride power FET with a field plate structure, which includes a thin layer formed of pi p-type graded AIGaN and a thin layer formed of p-type GaN.
| — |
Thickness | ≥ 125 nm | — |
graded InGaN (lower layer of field plate structure, alternative embodiment)
InGaN
Figure 2 shows an exemplary vertical gallium nitride power FET with a field plate structure, which includes a thin layer formed of pi p-type graded AIGaN and a thin layer formed of p-type GaN.
| — |
Thickness | ≥ 125 nm | — |