The device of claim 1, comprising a transistor and at least one of: the thickness varying discretely in sections of the gate width so that each of a plurality of portions of current flowing under a different one of the sections experience a different discrete threshold voltage and a longest one of the sections of a particular threshold voltage has a length no more than 0.1% of a free space wavelength of a maximum operating frequency of the transistor, so as to reduce a parasitic inductance between the portions of current, or the thickness varying continuously to continuously vary the threshold voltage and a distance between repeated threshold voltages is no more than 0.1% of the free space wavelength so as to reduce the parasitic induc-tance between the portions of current.

The device of claim 1, comprising a transistor wherein: the transistor has at least one of gm2 and gm3 tailored by a variation in the threshold voltage across the gate width; the thickness has two values, thereby setting two thresh-old voltages, which are selected in such a way that at least: the gm2 associated with each of the threshold voltages have opposite signs and magnitudes equal to within 50% over a range in gate voltages applied to the gate with respect to the channel, the gm3 associated with each of the threshold voltages have opposite signs and magnitudes equal to within 50% over the range in gate voltages, such that a summing of portions of the current in indi-vidual sections of the gate width experiencing the different ones of the two threshold voltages reduces the magnitude of at least one of gm2 Or gm3 over the range in the gate voltages relative to a constituent single-threshold voltage transistor having only one of the two threshold voltages.

The device of claim 1, comprising a transistor wherein: the transistor has at least one of gm2 and gm3 tailored by 20 a variation in the threshold voltage; and the thickness varies with more than two values, varies in a continuous fashion across the gate width, or has a combination of discrete and continuously varying val-ues, so as to set a plurality of threshold voltages, such that a summing of portions of the current, flowing in individual sections of the gate width experiencing different ones of the threshold voltages, reduces a magnitude of gm2 Or gm3 over a range in gate voltage, relative to a constituent single-threshold voltage tran-sistor comprising only one of the threshold voltages.

The device of claim 1, wherein: the materials and a total separation between the gate and the centroid lead to a planar mobile carrier charge density, of the mobile charge carriers underneath the gate at zero gate to source voltage, that at least: varies by no more than 20% across an active width of the gate; or, has a minimum value of 0.9·1013 cm⁻² assessed in any segment 50 nanometers or wider across the active width of the gate; and the active width of the gate includes portions of the gate which are above a conducting channel comprising the mobile charge carriers, and does not include edge regions where isolation processes may alter channel charge densities.

The transistor of claim 6 wherein the recess at least: extends into the channel across at least a portion of the gate width, or includes an electrically insulating material deposited on a base, sidewalls, or the base and the sidewalls of the recess.

The transistor of claim 6 wherein at least 50% of a thickness between the gate and a centroid of the mobile charge carriers, including the cap and the channel, consists essentially of the III-nitride material of the channel across an entirety of the gate width.

The transistor of claim 6 wherein a plurality of dis-tances between the gate and the centroid of the mobile charge carriers in the channel tailor a linearity or nonlinear-ity of the transistor.

The transistor of claim 6, wherein: the III-nitride material comprises one or more layers of ScvGawAlxInyBzN where 0≤v≤1, 0≤w≤1, 0≤x≤1, 0≤y≤1, 0≤z≤1, and v+w+x+y+z=1 and at least 50% of a thickness between the gate and the centroid of the mobile charge carriers comprises one or more layers of the ScvGawAlxInyBzN wherein the x, y, z, v, w do not vary by more than 5% as compared to in the channel, or the channel comprises a composition including Gallium and Nitrogen, and at least 50% of the thickness consists essentially of the composition or GaN.

The transistor of claim 6 wherein the cap comprises a plurality of layers, including at least two etch stop layers, wherein the etch stop layers are used to control the depths defining a distance between the gate and a centroid of the mobile charge carriers.

The transistor of claim 6, wherein: the channel comprises GaN comprising a two dimensional electron gas or a two dimensional hole gas confined in the channel by the back barrier; the cap comprises a cap structure on the channel and the cap structure comprises: a first aluminum containing nitride layer on or above the channel; a first GaN layer on or above the first aluminum containing nitride layer; a second aluminum containing nitride layer on or above the first GaN layer; a second GaN layer on or above the second aluminum containing nitride layer, the first and second alumi-num containing nitride layers are etch stop layers, a first region of the recess extends through the second GaN layer and the first GaN layer so that only a portion of the first aluminum containing nitride layer is between the channel and a base of the gate, or the recess extends all the way through the first aluminum con-taining nitride layer, and a second region of the recess extends through second GaN layer and at least a portion of the second aluminum containing nitride layer, so that the first aluminum containing nitride layer and at least a portion of the first GaN layer are between the channel and the base of the gate.

The transistor of claim 6, wherein: the cap includes two or more aluminum containing nitride layers, the recess in the cap includes two or more etched recesses, and the aluminum containing nitride layers form epitaxially-defined etch stops establishing the depths controlling the threshold voltages.

The transistor of claim 6 operating a frequency greater than 1 GHz.

The method of claim 17, wherein: the channel layer comprises GaN and the mobile charge carriers comprise a two dimensional electron gas or a two dimensional hole gas; the cap layer comprises: a first one of the etch stop layers comprising a first nitride layer comprising aluminum on or above the channel layer; a first GaN layer on or above the first nitride layer; a second one of the etch stop layers comprising a second nitride layer comprising aluminum on or above the first GaN layer; a second GaN layer on or above the second nitride layer, a first region of the recess extends through the second GaN layer, the second nitride layer, the first GaN layer, and the first nitride layer or so that only a portion of the first nitride layer is between the channel layer and a base of the gate, and a second region of the recess extends through second GaN layer and the second nitride layer, so that the first nitride layer and at least the first GaN layer is between the channel layer and the base of the gate. ∗ ∗ ∗ ∗ ∗

The device of claim 1, comprising a transistor and at least one of: the thickness varying discretely in sections of the gate width so that each of a plurality of portions of current flowing under a different one of the sections experience a different discrete threshold voltage and a longest one of the sections of a particular threshold voltage has a length no more than 0.1% of a free space wavelength of a maximum operating frequency of the transistor, so as to reduce a parasitic inductance between the portions of current, or the thickness varying continuously to continuously vary the threshold voltage and a distance between repeated threshold voltages is no more than 0.1% of the free space wavelength so as to reduce the parasitic induc-tance between the portions of current.

The device of claim 1, comprising a transistor wherein: the transistor has at least one of gm2 and gm3 tailored by a variation in the threshold voltage across the gate width; the thickness has two values, thereby setting two thresh-old voltages, which are selected in such a way that at least: the gm2 associated with each of the threshold voltages have opposite signs and magnitudes equal to within 50% over a range in gate voltages applied to the gate with respect to the channel, the gm3 associated with each of the threshold voltages have opposite signs and magnitudes equal to within 50% over the range in gate voltages, such that a summing of portions of the current in indi-vidual sections of the gate width experiencing the different ones of the two threshold voltages reduces the magnitude of at least one of gm2 Or gm3 over the range in the gate voltages relative to a constituent single-threshold voltage transistor having only one of the two threshold voltages.

The device of claim 1, comprising a transistor wherein: the transistor has at least one of gm2 and gm3 tailored by 20 a variation in the threshold voltage; and the thickness varies with more than two values, varies in a continuous fashion across the gate width, or has a combination of discrete and continuously varying val-ues, so as to set a plurality of threshold voltages, such that a summing of portions of the current, flowing in individual sections of the gate width experiencing different ones of the threshold voltages, reduces a magnitude of gm2 Or gm3 over a range in gate voltage, relative to a constituent single-threshold voltage tran-sistor comprising only one of the threshold voltages.

The device of claim 1, wherein: the materials and a total separation between the gate and the centroid lead to a planar mobile carrier charge density, of the mobile charge carriers underneath the gate at zero gate to source voltage, that at least: varies by no more than 20% across an active width of the gate; or, has a minimum value of 0.9·1013 cm⁻² assessed in any segment 50 nanometers or wider across the active width of the gate; and the active width of the gate includes portions of the gate which are above a conducting channel comprising the mobile charge carriers, and does not include edge regions where isolation processes may alter channel charge densities.

The transistor of claim 6 wherein the recess at least: extends into the channel across at least a portion of the gate width, or includes an electrically insulating material deposited on a base, sidewalls, or the base and the sidewalls of the recess.

The transistor of claim 6 wherein at least 50% of a thickness between the gate and a centroid of the mobile charge carriers, including the cap and the channel, consists essentially of the III-nitride material of the channel across an entirety of the gate width.

The transistor of claim 6 wherein a plurality of dis-tances between the gate and the centroid of the mobile charge carriers in the channel tailor a linearity or nonlinear-ity of the transistor.

The transistor of claim 6, wherein: the III-nitride material comprises one or more layers of ScvGawAlxInyBzN where 0≤v≤1, 0≤w≤1, 0≤x≤1, 0≤y≤1, 0≤z≤1, and v+w+x+y+z=1 and at least 50% of a thickness between the gate and the centroid of the mobile charge carriers comprises one or more layers of the ScvGawAlxInyBzN wherein the x, y, z, v, w do not vary by more than 5% as compared to in the channel, or the channel comprises a composition including Gallium and Nitrogen, and at least 50% of the thickness consists essentially of the composition or GaN.

The transistor of claim 6 wherein the cap comprises a plurality of layers, including at least two etch stop layers, wherein the etch stop layers are used to control the depths defining a distance between the gate and a centroid of the mobile charge carriers.

The transistor of claim 6, wherein: the channel comprises GaN comprising a two dimensional electron gas or a two dimensional hole gas confined in the channel by the back barrier; the cap comprises a cap structure on the channel and the cap structure comprises: a first aluminum containing nitride layer on or above the channel; a first GaN layer on or above the first aluminum containing nitride layer; a second aluminum containing nitride layer on or above the first GaN layer; a second GaN layer on or above the second aluminum containing nitride layer, the first and second alumi-num containing nitride layers are etch stop layers, a first region of the recess extends through the second GaN layer and the first GaN layer so that only a portion of the first aluminum containing nitride layer is between the channel and a base of the gate, or the recess extends all the way through the first aluminum con-taining nitride layer, and a second region of the recess extends through second GaN layer and at least a portion of the second aluminum containing nitride layer, so that the first aluminum containing nitride layer and at least a portion of the first GaN layer are between the channel and the base of the gate.

The transistor of claim 6, wherein: the cap includes two or more aluminum containing nitride layers, the recess in the cap includes two or more etched recesses, and the aluminum containing nitride layers form epitaxially-defined etch stops establishing the depths controlling the threshold voltages.

The transistor of claim 6 operating a frequency greater than 1 GHz.

The method of claim 17, wherein: the channel layer comprises GaN and the mobile charge carriers comprise a two dimensional electron gas or a two dimensional hole gas; the cap layer comprises: a first one of the etch stop layers comprising a first nitride layer comprising aluminum on or above the channel layer; a first GaN layer on or above the first nitride layer; a second one of the etch stop layers comprising a second nitride layer comprising aluminum on or above the first GaN layer; a second GaN layer on or above the second nitride layer, a first region of the recess extends through the second GaN layer, the second nitride layer, the first GaN layer, and the first nitride layer or so that only a portion of the first nitride layer is between the channel layer and a base of the gate, and a second region of the recess extends through second GaN layer and the second nitride layer, so that the first nitride layer and at least the first GaN layer is between the channel layer and the base of the gate. ∗ ∗ ∗ ∗ ∗

The device of claim 1, comprising a transistor and at least one of: the thickness varying discretely in sections of the gate width so that each of a plurality of portions of current flowing under a different one of the sections experience a different discrete threshold voltage and a longest one of the sections of a particular threshold voltage has a length no more than 0.1% of a free space wavelength of a maximum operating frequency of the transistor, so as to reduce a parasitic inductance between the portions of current, or the thickness varying continuously to continuously vary the threshold voltage and a distance between repeated threshold voltages is no more than 0.1% of the free space wavelength so as to reduce the parasitic induc-tance between the portions of current.

The device of claim 1, comprising a transistor wherein: the transistor has at least one of gm2 and gm3 tailored by a variation in the threshold voltage across the gate width; the thickness has two values, thereby setting two thresh-old voltages, which are selected in such a way that at least: the gm2 associated with each of the threshold voltages have opposite signs and magnitudes equal to within 50% over a range in gate voltages applied to the gate with respect to the channel, the gm3 associated with each of the threshold voltages have opposite signs and magnitudes equal to within 50% over the range in gate voltages, such that a summing of portions of the current in indi-vidual sections of the gate width experiencing the different ones of the two threshold voltages reduces the magnitude of at least one of gm2 Or gm3 over the range in the gate voltages relative to a constituent single-threshold voltage transistor having only one of the two threshold voltages.

The device of claim 1, comprising a transistor wherein: the transistor has at least one of gm2 and gm3 tailored by 20 a variation in the threshold voltage; and the thickness varies with more than two values, varies in a continuous fashion across the gate width, or has a combination of discrete and continuously varying val-ues, so as to set a plurality of threshold voltages, such that a summing of portions of the current, flowing in individual sections of the gate width experiencing different ones of the threshold voltages, reduces a magnitude of gm2 Or gm3 over a range in gate voltage, relative to a constituent single-threshold voltage tran-sistor comprising only one of the threshold voltages.

The device of claim 1, wherein: the materials and a total separation between the gate and the centroid lead to a planar mobile carrier charge density, of the mobile charge carriers underneath the gate at zero gate to source voltage, that at least: varies by no more than 20% across an active width of the gate; or, has a minimum value of 0.9·1013 cm⁻² assessed in any segment 50 nanometers or wider across the active width of the gate; and the active width of the gate includes portions of the gate which are above a conducting channel comprising the mobile charge carriers, and does not include edge regions where isolation processes may alter channel charge densities.

The transistor of claim 6 wherein the recess at least: extends into the channel across at least a portion of the gate width, or includes an electrically insulating material deposited on a base, sidewalls, or the base and the sidewalls of the recess.

The transistor of claim 6 wherein at least 50% of a thickness between the gate and a centroid of the mobile charge carriers, including the cap and the channel, consists essentially of the III-nitride material of the channel across an entirety of the gate width.

The transistor of claim 6 wherein a plurality of dis-tances between the gate and the centroid of the mobile charge carriers in the channel tailor a linearity or nonlinear-ity of the transistor.

The transistor of claim 6, wherein: the III-nitride material comprises one or more layers of ScvGawAlxInyBzN where 0≤v≤1, 0≤w≤1, 0≤x≤1, 0≤y≤1, 0≤z≤1, and v+w+x+y+z=1 and at least 50% of a thickness between the gate and the centroid of the mobile charge carriers comprises one or more layers of the ScvGawAlxInyBzN wherein the x, y, z, v, w do not vary by more than 5% as compared to in the channel, or the channel comprises a composition including Gallium and Nitrogen, and at least 50% of the thickness consists essentially of the composition or GaN.

The transistor of claim 6 wherein the cap comprises a plurality of layers, including at least two etch stop layers, wherein the etch stop layers are used to control the depths defining a distance between the gate and a centroid of the mobile charge carriers.

The transistor of claim 6, wherein: the channel comprises GaN comprising a two dimensional electron gas or a two dimensional hole gas confined in the channel by the back barrier; the cap comprises a cap structure on the channel and the cap structure comprises: a first aluminum containing nitride layer on or above the channel; a first GaN layer on or above the first aluminum containing nitride layer; a second aluminum containing nitride layer on or above the first GaN layer; a second GaN layer on or above the second aluminum containing nitride layer, the first and second alumi-num containing nitride layers are etch stop layers, a first region of the recess extends through the second GaN layer and the first GaN layer so that only a portion of the first aluminum containing nitride layer is between the channel and a base of the gate, or the recess extends all the way through the first aluminum con-taining nitride layer, and a second region of the recess extends through second GaN layer and at least a portion of the second aluminum containing nitride layer, so that the first aluminum containing nitride layer and at least a portion of the first GaN layer are between the channel and the base of the gate.

The transistor of claim 6, wherein: the cap includes two or more aluminum containing nitride layers, the recess in the cap includes two or more etched recesses, and the aluminum containing nitride layers form epitaxially-defined etch stops establishing the depths controlling the threshold voltages.

The transistor of claim 6 operating a frequency greater than 1 GHz.

The method of claim 17, wherein: the channel layer comprises GaN and the mobile charge carriers comprise a two dimensional electron gas or a two dimensional hole gas; the cap layer comprises: a first one of the etch stop layers comprising a first nitride layer comprising aluminum on or above the channel layer; a first GaN layer on or above the first nitride layer; a second one of the etch stop layers comprising a second nitride layer comprising aluminum on or above the first GaN layer; a second GaN layer on or above the second nitride layer, a first region of the recess extends through the second GaN layer, the second nitride layer, the first GaN layer, and the first nitride layer or so that only a portion of the first nitride layer is between the channel layer and a base of the gate, and a second region of the recess extends through second GaN layer and the second nitride layer, so that the first nitride layer and at least the first GaN layer is between the channel layer and the base of the gate. ∗ ∗ ∗ ∗ ∗

The device of claim 1, comprising a transistor and at least one of: the thickness varying discretely in sections of the gate width so that each of a plurality of portions of current flowing under a different one of the sections experience a different discrete threshold voltage and a longest one of the sections of a particular threshold voltage has a length no more than 0.1% of a free space wavelength of a maximum operating frequency of the transistor, so as to reduce a parasitic inductance between the portions of current, or the thickness varying continuously to continuously vary the threshold voltage and a distance between repeated threshold voltages is no more than 0.1% of the free space wavelength so as to reduce the parasitic induc-tance between the portions of current.

The device of claim 1, comprising a transistor wherein: the transistor has at least one of gm2 and gm3 tailored by a variation in the threshold voltage across the gate width; the thickness has two values, thereby setting two thresh-old voltages, which are selected in such a way that at least: the gm2 associated with each of the threshold voltages have opposite signs and magnitudes equal to within 50% over a range in gate voltages applied to the gate with respect to the channel, the gm3 associated with each of the threshold voltages have opposite signs and magnitudes equal to within 50% over the range in gate voltages, such that a summing of portions of the current in indi-vidual sections of the gate width experiencing the different ones of the two threshold voltages reduces the magnitude of at least one of gm2 Or gm3 over the range in the gate voltages relative to a constituent single-threshold voltage transistor having only one of the two threshold voltages.

The device of claim 1, comprising a transistor wherein: the transistor has at least one of gm2 and gm3 tailored by 20 a variation in the threshold voltage; and the thickness varies with more than two values, varies in a continuous fashion across the gate width, or has a combination of discrete and continuously varying val-ues, so as to set a plurality of threshold voltages, such that a summing of portions of the current, flowing in individual sections of the gate width experiencing different ones of the threshold voltages, reduces a magnitude of gm2 Or gm3 over a range in gate voltage, relative to a constituent single-threshold voltage tran-sistor comprising only one of the threshold voltages.

The device of claim 1, wherein: the materials and a total separation between the gate and the centroid lead to a planar mobile carrier charge density, of the mobile charge carriers underneath the gate at zero gate to source voltage, that at least: varies by no more than 20% across an active width of the gate; or, has a minimum value of 0.9·1013 cm⁻² assessed in any segment 50 nanometers or wider across the active width of the gate; and the active width of the gate includes portions of the gate which are above a conducting channel comprising the mobile charge carriers, and does not include edge regions where isolation processes may alter channel charge densities.

The transistor of claim 6 wherein the recess at least: extends into the channel across at least a portion of the gate width, or includes an electrically insulating material deposited on a base, sidewalls, or the base and the sidewalls of the recess.

The transistor of claim 6 wherein at least 50% of a thickness between the gate and a centroid of the mobile charge carriers, including the cap and the channel, consists essentially of the III-nitride material of the channel across an entirety of the gate width.

The transistor of claim 6 wherein a plurality of dis-tances between the gate and the centroid of the mobile charge carriers in the channel tailor a linearity or nonlinear-ity of the transistor.

The transistor of claim 6, wherein: the III-nitride material comprises one or more layers of ScvGawAlxInyBzN where 0≤v≤1, 0≤w≤1, 0≤x≤1, 0≤y≤1, 0≤z≤1, and v+w+x+y+z=1 and at least 50% of a thickness between the gate and the centroid of the mobile charge carriers comprises one or more layers of the ScvGawAlxInyBzN wherein the x, y, z, v, w do not vary by more than 5% as compared to in the channel, or the channel comprises a composition including Gallium and Nitrogen, and at least 50% of the thickness consists essentially of the composition or GaN.

The transistor of claim 6 wherein the cap comprises a plurality of layers, including at least two etch stop layers, wherein the etch stop layers are used to control the depths defining a distance between the gate and a centroid of the mobile charge carriers.

The transistor of claim 6, wherein: the channel comprises GaN comprising a two dimensional electron gas or a two dimensional hole gas confined in the channel by the back barrier; the cap comprises a cap structure on the channel and the cap structure comprises: a first aluminum containing nitride layer on or above the channel; a first GaN layer on or above the first aluminum containing nitride layer; a second aluminum containing nitride layer on or above the first GaN layer; a second GaN layer on or above the second aluminum containing nitride layer, the first and second alumi-num containing nitride layers are etch stop layers, a first region of the recess extends through the second GaN layer and the first GaN layer so that only a portion of the first aluminum containing nitride layer is between the channel and a base of the gate, or the recess extends all the way through the first aluminum con-taining nitride layer, and a second region of the recess extends through second GaN layer and at least a portion of the second aluminum containing nitride layer, so that the first aluminum containing nitride layer and at least a portion of the first GaN layer are between the channel and the base of the gate.

The transistor of claim 6, wherein: the cap includes two or more aluminum containing nitride layers, the recess in the cap includes two or more etched recesses, and the aluminum containing nitride layers form epitaxially-defined etch stops establishing the depths controlling the threshold voltages.

The transistor of claim 6 operating a frequency greater than 1 GHz.

The method of claim 17, wherein: the channel layer comprises GaN and the mobile charge carriers comprise a two dimensional electron gas or a two dimensional hole gas; the cap layer comprises: a first one of the etch stop layers comprising a first nitride layer comprising aluminum on or above the channel layer; a first GaN layer on or above the first nitride layer; a second one of the etch stop layers comprising a second nitride layer comprising aluminum on or above the first GaN layer; a second GaN layer on or above the second nitride layer, a first region of the recess extends through the second GaN layer, the second nitride layer, the first GaN layer, and the first nitride layer or so that only a portion of the first nitride layer is between the channel layer and a base of the gate, and a second region of the recess extends through second GaN layer and the second nitride layer, so that the first nitride layer and at least the first GaN layer is between the channel layer and the base of the gate. ∗ ∗ ∗ ∗ ∗