Patent
US 10,510,827CAPACITOR HAVING A GRAPHENE STRUCTURE, SEMICONDUCTOR DEVICE INCLUDING THE CAPACITOR AND METHOD OF FORMING THE SAME
Chewn-Pu Jou
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 10,510,827Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 A is a cross-sectional view of a semiconductor device in accordance with some embodiments.
Figure 1 B is a cross-sectional view of a semiconductor device in accordance with some embodiments.
Figure 2 is a cross-sectional view of a contact structure for a capacitor in accordance with some embodiments.
Figure 3 is a flowchart of a method of making a semiconductor device in accordance with some embodiments.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
The capacitor of claim 1, wherein a number of graphene layers in the first plurality of graphene layers ranges from 2 layers to 20 layers.
The capacitor of claim 2, wherein a number of graphene layers in the second plurality of graphene layers is equal to the number of graphene layers in the first plurality of graphene layers.
The capacitor of claim 2, wherein a number of graphene layers in the second plurality of graphene layers is different from the number of graphene layers in the first plurality of graphene layers.
The capacitor of claim 1, further comprising a first contact structure configured to transfer charge carriers into and out of the first graphene structure, wherein a portion of the first contact structure is disposed adjacent the second graphene structure.
The capacitor of claim 5, wherein the first contact structure extends into the first graphene structure to contact multiple graphene layers of the first plurality of graphene layers.
The capacitor of claim 5, wherein the first contact structure extends through the dielectric layer and into the first graphene structure, wherein the dielectric layer extends laterally past the sidewall of the second graphene structure.
The capacitor of claim 5, wherein the first contact structure comprises: a conductive material; and a barrier layer separating the conductive material from the first graphene structure.
The capacitor of claim 1, further comprising a second contact structure configured to transfer charge carriers into and out of the second graphene structure.
The capacitor of claim 9, wherein the second contact structure extends into the second graphene structure to contact multiple graphene layers of the second plurality of graphene layers.
The capacitor of claim 9, wherein the second contact structure in the second graphene structure has substantially vertical sidewalls over the second graphene structure.
The capacitor of claim 1, wherein the growth layer comprises at least one of copper, aluminum, or tungsten.
A semiconductor device comprising: a substrate; an interconnect structure over the substrate, the interconnect structure having a plurality of conductive features; and a capacitor in the interconnect structure, the capacitor being in electrical contact with at least one conductive feature of the plurality of conductive features, wherein the capacitor comprises: a first graphene structure in contact with the interconnect structure, the first graphene structure having a first plurality of graphene layers, the first graphene structure having a first lateral dimension measured between opposing sidewalls of the first graphene structure, a dielectric layer over the first graphene structure, and a second graphene structure over the dielectric layer, the second graphene structure having a second plurality of graphene layers and a second lateral dimension measured between opposing sidewalls of the second graphene structure, wherein the first lateral dimension is greater than the second lateral dimension.
The semiconductor device of claim 14, wherein the interconnect structure comprises a dielectric material between neighboring conductive features of the plurality of conductive features, and the dielectric layer comprises a same material as the dielectric material.
The semiconductor device of claim 14, wherein the interconnect structure comprises a dielectric material between neighboring conductive features of the plurality of conductive features, and the dielectric layer comprises a different material from the dielectric material, and wherein the dielectric layer forms an interface with a top surface of the dielectric material.
The semiconductor device of claim 14, wherein the capacitor further includes a growth layer between the dielectric layer and the second graphene structure.
A semiconductor device comprising: an interconnect structure, wherein the interconnect structure has a first lateral dimension measured between opposing sidewalls of the interconnect structure; a first graphene structure on the interconnect structure, the first graphene structure having a first plurality of graphene layers, wherein the first graphene structure has a second lateral dimension measured between opposing sidewalls of the first graphene structure, wherein the first lateral dimension is greater than the second lateral dimension; a dielectric layer over the first graphene structure, the dielectric layer having a third lateral dimension measured between opposing sidewalls of the dielectric layer, wherein the first graphene structure extends laterally past a sidewall of the dielectric layer; a conductive growth layer over the dielectric layer; and a second graphene structure over the conductive growth layer, wherein the second graphene structure includes a second plurality of graphene layers, the second graphene structure having a fourth lateral dimension measured between opposing sidewalls of the second graphene structure, wherein the dielectric layer extends laterally past a sidewall of the second graphene structure, wherein the second lateral dimension is greater than the third lateral dimension and the fourth lateral dimension, wherein the third lateral dimension
The semiconductor device of claim 19, further extending into the first graphene structure. is greater than the fourth lateral dimension. comprising a contact having tapered sidewalls
Layer stacks claimed or described, ordered top of device to substrate.
graphene capacitor
semiconductor device with graphene capacitor in interconnect structure
Materials described outside the worked examples.
graphene
C
dielectric layer
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
MOM capacitor storage ability (background, prior art) | <10 fF/µm² | — |
MIM capacitor storage ability (background, prior art) | 30–100 fF/µm² | — |
Dielectric layer 154 thickness range |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,510,827Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 A is a cross-sectional view of a semiconductor device in accordance with some embodiments.
Figure 1 B is a cross-sectional view of a semiconductor device in accordance with some embodiments.
Figure 2 is a cross-sectional view of a contact structure for a capacitor in accordance with some embodiments.
Figure 3 is a flowchart of a method of making a semiconductor device in accordance with some embodiments.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
The capacitor of claim 1, wherein a number of graphene layers in the first plurality of graphene layers ranges from 2 layers to 20 layers.
The capacitor of claim 2, wherein a number of graphene layers in the second plurality of graphene layers is equal to the number of graphene layers in the first plurality of graphene layers.
The capacitor of claim 2, wherein a number of graphene layers in the second plurality of graphene layers is different from the number of graphene layers in the first plurality of graphene layers.
The capacitor of claim 1, further comprising a first contact structure configured to transfer charge carriers into and out of the first graphene structure, wherein a portion of the first contact structure is disposed adjacent the second graphene structure.
The capacitor of claim 5, wherein the first contact structure extends into the first graphene structure to contact multiple graphene layers of the first plurality of graphene layers.
The capacitor of claim 5, wherein the first contact structure extends through the dielectric layer and into the first graphene structure, wherein the dielectric layer extends laterally past the sidewall of the second graphene structure.
The capacitor of claim 5, wherein the first contact structure comprises: a conductive material; and a barrier layer separating the conductive material from the first graphene structure.
The capacitor of claim 1, further comprising a second contact structure configured to transfer charge carriers into and out of the second graphene structure.
The capacitor of claim 9, wherein the second contact structure extends into the second graphene structure to contact multiple graphene layers of the second plurality of graphene layers.
The capacitor of claim 9, wherein the second contact structure in the second graphene structure has substantially vertical sidewalls over the second graphene structure.
The capacitor of claim 1, wherein the growth layer comprises at least one of copper, aluminum, or tungsten.
A semiconductor device comprising: a substrate; an interconnect structure over the substrate, the interconnect structure having a plurality of conductive features; and a capacitor in the interconnect structure, the capacitor being in electrical contact with at least one conductive feature of the plurality of conductive features, wherein the capacitor comprises: a first graphene structure in contact with the interconnect structure, the first graphene structure having a first plurality of graphene layers, the first graphene structure having a first lateral dimension measured between opposing sidewalls of the first graphene structure, a dielectric layer over the first graphene structure, and a second graphene structure over the dielectric layer, the second graphene structure having a second plurality of graphene layers and a second lateral dimension measured between opposing sidewalls of the second graphene structure, wherein the first lateral dimension is greater than the second lateral dimension.
The semiconductor device of claim 14, wherein the interconnect structure comprises a dielectric material between neighboring conductive features of the plurality of conductive features, and the dielectric layer comprises a same material as the dielectric material.
The semiconductor device of claim 14, wherein the interconnect structure comprises a dielectric material between neighboring conductive features of the plurality of conductive features, and the dielectric layer comprises a different material from the dielectric material, and wherein the dielectric layer forms an interface with a top surface of the dielectric material.
The semiconductor device of claim 14, wherein the capacitor further includes a growth layer between the dielectric layer and the second graphene structure.
A semiconductor device comprising: an interconnect structure, wherein the interconnect structure has a first lateral dimension measured between opposing sidewalls of the interconnect structure; a first graphene structure on the interconnect structure, the first graphene structure having a first plurality of graphene layers, wherein the first graphene structure has a second lateral dimension measured between opposing sidewalls of the first graphene structure, wherein the first lateral dimension is greater than the second lateral dimension; a dielectric layer over the first graphene structure, the dielectric layer having a third lateral dimension measured between opposing sidewalls of the dielectric layer, wherein the first graphene structure extends laterally past a sidewall of the dielectric layer; a conductive growth layer over the dielectric layer; and a second graphene structure over the conductive growth layer, wherein the second graphene structure includes a second plurality of graphene layers, the second graphene structure having a fourth lateral dimension measured between opposing sidewalls of the second graphene structure, wherein the dielectric layer extends laterally past a sidewall of the second graphene structure, wherein the second lateral dimension is greater than the third lateral dimension and the fourth lateral dimension, wherein the third lateral dimension
The semiconductor device of claim 19, further extending into the first graphene structure. is greater than the fourth lateral dimension. comprising a contact having tapered sidewalls
Layer stacks claimed or described, ordered top of device to substrate.
graphene capacitor
semiconductor device with graphene capacitor in interconnect structure
Materials described outside the worked examples.
graphene
C
dielectric layer
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
MOM capacitor storage ability (background, prior art) | <10 fF/µm² | — |
MIM capacitor storage ability (background, prior art) | 30–100 fF/µm² | — |
Dielectric layer 154 thickness range |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,510,827Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 A is a cross-sectional view of a semiconductor device in accordance with some embodiments.
Figure 1 B is a cross-sectional view of a semiconductor device in accordance with some embodiments.
Figure 2 is a cross-sectional view of a contact structure for a capacitor in accordance with some embodiments.
Figure 3 is a flowchart of a method of making a semiconductor device in accordance with some embodiments.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
The capacitor of claim 1, wherein a number of graphene layers in the first plurality of graphene layers ranges from 2 layers to 20 layers.
The capacitor of claim 2, wherein a number of graphene layers in the second plurality of graphene layers is equal to the number of graphene layers in the first plurality of graphene layers.
The capacitor of claim 2, wherein a number of graphene layers in the second plurality of graphene layers is different from the number of graphene layers in the first plurality of graphene layers.
The capacitor of claim 1, further comprising a first contact structure configured to transfer charge carriers into and out of the first graphene structure, wherein a portion of the first contact structure is disposed adjacent the second graphene structure.
The capacitor of claim 5, wherein the first contact structure extends into the first graphene structure to contact multiple graphene layers of the first plurality of graphene layers.
The capacitor of claim 5, wherein the first contact structure extends through the dielectric layer and into the first graphene structure, wherein the dielectric layer extends laterally past the sidewall of the second graphene structure.
The capacitor of claim 5, wherein the first contact structure comprises: a conductive material; and a barrier layer separating the conductive material from the first graphene structure.
The capacitor of claim 1, further comprising a second contact structure configured to transfer charge carriers into and out of the second graphene structure.
The capacitor of claim 9, wherein the second contact structure extends into the second graphene structure to contact multiple graphene layers of the second plurality of graphene layers.
The capacitor of claim 9, wherein the second contact structure in the second graphene structure has substantially vertical sidewalls over the second graphene structure.
The capacitor of claim 1, wherein the growth layer comprises at least one of copper, aluminum, or tungsten.
A semiconductor device comprising: a substrate; an interconnect structure over the substrate, the interconnect structure having a plurality of conductive features; and a capacitor in the interconnect structure, the capacitor being in electrical contact with at least one conductive feature of the plurality of conductive features, wherein the capacitor comprises: a first graphene structure in contact with the interconnect structure, the first graphene structure having a first plurality of graphene layers, the first graphene structure having a first lateral dimension measured between opposing sidewalls of the first graphene structure, a dielectric layer over the first graphene structure, and a second graphene structure over the dielectric layer, the second graphene structure having a second plurality of graphene layers and a second lateral dimension measured between opposing sidewalls of the second graphene structure, wherein the first lateral dimension is greater than the second lateral dimension.
The semiconductor device of claim 14, wherein the interconnect structure comprises a dielectric material between neighboring conductive features of the plurality of conductive features, and the dielectric layer comprises a same material as the dielectric material.
The semiconductor device of claim 14, wherein the interconnect structure comprises a dielectric material between neighboring conductive features of the plurality of conductive features, and the dielectric layer comprises a different material from the dielectric material, and wherein the dielectric layer forms an interface with a top surface of the dielectric material.
The semiconductor device of claim 14, wherein the capacitor further includes a growth layer between the dielectric layer and the second graphene structure.
A semiconductor device comprising: an interconnect structure, wherein the interconnect structure has a first lateral dimension measured between opposing sidewalls of the interconnect structure; a first graphene structure on the interconnect structure, the first graphene structure having a first plurality of graphene layers, wherein the first graphene structure has a second lateral dimension measured between opposing sidewalls of the first graphene structure, wherein the first lateral dimension is greater than the second lateral dimension; a dielectric layer over the first graphene structure, the dielectric layer having a third lateral dimension measured between opposing sidewalls of the dielectric layer, wherein the first graphene structure extends laterally past a sidewall of the dielectric layer; a conductive growth layer over the dielectric layer; and a second graphene structure over the conductive growth layer, wherein the second graphene structure includes a second plurality of graphene layers, the second graphene structure having a fourth lateral dimension measured between opposing sidewalls of the second graphene structure, wherein the dielectric layer extends laterally past a sidewall of the second graphene structure, wherein the second lateral dimension is greater than the third lateral dimension and the fourth lateral dimension, wherein the third lateral dimension
The semiconductor device of claim 19, further extending into the first graphene structure. is greater than the fourth lateral dimension. comprising a contact having tapered sidewalls
Layer stacks claimed or described, ordered top of device to substrate.
graphene capacitor
semiconductor device with graphene capacitor in interconnect structure
Materials described outside the worked examples.
graphene
C
dielectric layer
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
MOM capacitor storage ability (background, prior art) | <10 fF/µm² | — |
MIM capacitor storage ability (background, prior art) | 30–100 fF/µm² | — |
Dielectric layer 154 thickness range |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,510,827Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 A is a cross-sectional view of a semiconductor device in accordance with some embodiments.
Figure 1 B is a cross-sectional view of a semiconductor device in accordance with some embodiments.
Figure 2 is a cross-sectional view of a contact structure for a capacitor in accordance with some embodiments.
Figure 3 is a flowchart of a method of making a semiconductor device in accordance with some embodiments.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
The capacitor of claim 1, wherein a number of graphene layers in the first plurality of graphene layers ranges from 2 layers to 20 layers.
The capacitor of claim 2, wherein a number of graphene layers in the second plurality of graphene layers is equal to the number of graphene layers in the first plurality of graphene layers.
The capacitor of claim 2, wherein a number of graphene layers in the second plurality of graphene layers is different from the number of graphene layers in the first plurality of graphene layers.
The capacitor of claim 1, further comprising a first contact structure configured to transfer charge carriers into and out of the first graphene structure, wherein a portion of the first contact structure is disposed adjacent the second graphene structure.
The capacitor of claim 5, wherein the first contact structure extends into the first graphene structure to contact multiple graphene layers of the first plurality of graphene layers.
The capacitor of claim 5, wherein the first contact structure extends through the dielectric layer and into the first graphene structure, wherein the dielectric layer extends laterally past the sidewall of the second graphene structure.
The capacitor of claim 5, wherein the first contact structure comprises: a conductive material; and a barrier layer separating the conductive material from the first graphene structure.
The capacitor of claim 1, further comprising a second contact structure configured to transfer charge carriers into and out of the second graphene structure.
The capacitor of claim 9, wherein the second contact structure extends into the second graphene structure to contact multiple graphene layers of the second plurality of graphene layers.
The capacitor of claim 9, wherein the second contact structure in the second graphene structure has substantially vertical sidewalls over the second graphene structure.
The capacitor of claim 1, wherein the growth layer comprises at least one of copper, aluminum, or tungsten.
A semiconductor device comprising: a substrate; an interconnect structure over the substrate, the interconnect structure having a plurality of conductive features; and a capacitor in the interconnect structure, the capacitor being in electrical contact with at least one conductive feature of the plurality of conductive features, wherein the capacitor comprises: a first graphene structure in contact with the interconnect structure, the first graphene structure having a first plurality of graphene layers, the first graphene structure having a first lateral dimension measured between opposing sidewalls of the first graphene structure, a dielectric layer over the first graphene structure, and a second graphene structure over the dielectric layer, the second graphene structure having a second plurality of graphene layers and a second lateral dimension measured between opposing sidewalls of the second graphene structure, wherein the first lateral dimension is greater than the second lateral dimension.
The semiconductor device of claim 14, wherein the interconnect structure comprises a dielectric material between neighboring conductive features of the plurality of conductive features, and the dielectric layer comprises a same material as the dielectric material.
The semiconductor device of claim 14, wherein the interconnect structure comprises a dielectric material between neighboring conductive features of the plurality of conductive features, and the dielectric layer comprises a different material from the dielectric material, and wherein the dielectric layer forms an interface with a top surface of the dielectric material.
The semiconductor device of claim 14, wherein the capacitor further includes a growth layer between the dielectric layer and the second graphene structure.
A semiconductor device comprising: an interconnect structure, wherein the interconnect structure has a first lateral dimension measured between opposing sidewalls of the interconnect structure; a first graphene structure on the interconnect structure, the first graphene structure having a first plurality of graphene layers, wherein the first graphene structure has a second lateral dimension measured between opposing sidewalls of the first graphene structure, wherein the first lateral dimension is greater than the second lateral dimension; a dielectric layer over the first graphene structure, the dielectric layer having a third lateral dimension measured between opposing sidewalls of the dielectric layer, wherein the first graphene structure extends laterally past a sidewall of the dielectric layer; a conductive growth layer over the dielectric layer; and a second graphene structure over the conductive growth layer, wherein the second graphene structure includes a second plurality of graphene layers, the second graphene structure having a fourth lateral dimension measured between opposing sidewalls of the second graphene structure, wherein the dielectric layer extends laterally past a sidewall of the second graphene structure, wherein the second lateral dimension is greater than the third lateral dimension and the fourth lateral dimension, wherein the third lateral dimension
The semiconductor device of claim 19, further extending into the first graphene structure. is greater than the fourth lateral dimension. comprising a contact having tapered sidewalls
Layer stacks claimed or described, ordered top of device to substrate.
graphene capacitor
semiconductor device with graphene capacitor in interconnect structure
Materials described outside the worked examples.
graphene
C
dielectric layer
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
MOM capacitor storage ability (background, prior art) | <10 fF/µm² | — |
MIM capacitor storage ability (background, prior art) | 30–100 fF/µm² | — |
Dielectric layer 154 thickness range |
Related documents with shared materials, methods, properties, or citations.
semiconductor device with graphene capacitor and conductive growth layer
Cu
aluminum
Al
tungsten
W
conductive growth layer
silicon oxide
SiO₂
silicon nitride
Si₃N₄
silicon oxynitride
| 100–500 Å |
dielectric layer |
Pressure | 1–4 Torr | — |
Temperature | 400–1000 °C | — |
Temperature | 400–600 °C | — |
Thickness | 100–500 nm | — |
semiconductor device with graphene capacitor and conductive growth layer
Cu
aluminum
Al
tungsten
W
conductive growth layer
silicon oxide
SiO₂
silicon nitride
Si₃N₄
silicon oxynitride
| 100–500 Å |
dielectric layer |
Pressure | 1–4 Torr | — |
Temperature | 400–1000 °C | — |
Temperature | 400–600 °C | — |
Thickness | 100–500 nm | — |
semiconductor device with graphene capacitor and conductive growth layer
Cu
aluminum
Al
tungsten
W
conductive growth layer
silicon oxide
SiO₂
silicon nitride
Si₃N₄
silicon oxynitride
| 100–500 Å |
dielectric layer |
Pressure | 1–4 Torr | — |
Temperature | 400–1000 °C | — |
Temperature | 400–600 °C | — |
Thickness | 100–500 nm | — |
semiconductor device with graphene capacitor and conductive growth layer
Cu
aluminum
Al
tungsten
W
conductive growth layer
silicon oxide
SiO₂
silicon nitride
Si₃N₄
silicon oxynitride
| 100–500 Å |
dielectric layer |
Pressure | 1–4 Torr | — |
Temperature | 400–1000 °C | — |
Temperature | 400–600 °C | — |
Thickness | 100–500 nm | — |