CMOS-compatible Strain Engineering for High-Performance Monolayer Semiconductor Transistors

Marc Jaikissoon; Çağıl Köroğlu; Jerry A. Yang; Kathryn M. Neilson; Krishna C. Saraswat; Eric Pop

doi:10.1038/s41928-024-01244-7

Paper details

Research paper

Experimental GrowthExperimental CharacterizationComputational Multiscale

CMOS-compatible Strain Engineering for High-Performance Monolayer Semiconductor Transistors

Marc Jaikissoon, Çağıl Köroğlu, Jerry A. Yang, Kathryn M. Neilson et al.

2025·10.1038/s41928-024-01244-7·arXiv:2405.09792

Samples

Each sample groups how it was prepared, characterized, and measured. Click a card to expand.

Back-gated monolayer MoS₂ transistor with 1 µm channel and contact lengths, capped sequentially with AlOx and high-stress SiNx on 90 nm SiO₂/p++ Si.

5 preparations5 characterizations9 properties13 figures

ExperimentalMoS₂Studied Material

Back-gated monolayer MoS₂ transistor with 200 nm channel and contact lengths, capped sequentially with AlOx and high-stress SiNx on 90 nm SiO₂/p++ Si.

5 preparations5 characterizations9 properties13 figures

ExperimentalMoS₂Studied Material

Control monolayer MoS₂ transistor capped with low-stress SiNx on 90 nm SiO₂/p++ Si.

5 preparations2 characterizations6 properties8 figures

ExperimentalMoS₂Studied Material

Materials

MoS₂

Studied Material

Also known as

monolayer molybdenum disulfide

Variables

dimensionality= monolayer

studied material

SiO₂

Substrate / Dielectric

Why these are connected

Related documents with shared materials, methods, properties, or citations.

CMOS-compatible Strain Engineering for High-Performance Monolayer Semiconductor Transistors | Matter42 Literature

Properties

Type	Label	Value	Material	Sample	Source
Fet Drain Current	saturation current	488uA/um	MoS₂	Back-gated monolayer MoS₂ transistor with 1 µm channel and c	—
Fet Drain Current	median on-state current increase	14%	MoS₂	Back-gated monolayer MoS₂ transistor with 1 µm channel and c	—
Fet Drain Current	median on-state current increase	60%	MoS₂	Back-gated monolayer MoS₂ transistor with 200 nm channel and	—
Fet Drain Current	median on-state current increase	10%	MoS₂	Back-gated monolayer MoS₂ transistor with 1 µm channel and c	—
Fet Drain Current	median on-state current increase	18%	MoS₂	Back-gated monolayer MoS₂ transistor with 200 nm channel and	—
Schottky Barrier Height	effective barrier height	0.06eV	MoS₂	Back-gated monolayer MoS₂ transistor with 200 nm channel and	—
Schottky Barrier Height	effective barrier height	0.15eV	MoS₂	Control monolayer MoS₂ transistor capped with low-stress SiN	—
Sheet Stress	intrinsic tensile stress	600MPa	SiNx	Back-gated monolayer MoS₂ transistor with 1 µm channel and c Back-gated monolayer MoS₂ transistor with 200 nm channel and	—
Sheet Stress	intrinsic stress	50 to 100MPa	SiNx	Control monolayer MoS₂ transistor capped with low-stress SiN	—
Film Thickness	SiNx thickness	75nm	SiNx	Back-gated monolayer MoS₂ transistor with 1 µm channel and c Back-gated monolayer MoS₂ transistor with 200 nm channel and	—
Film Thickness	AlOx thickness	10nm	AlOx	Back-gated monolayer MoS₂ transistor with 1 µm channel and c Back-gated monolayer MoS₂ transistor with 200 nm channel and Control monolayer MoS₂ transistor capped with low-stress SiN	—
Film Thickness	Al thickness	1.5nm	Al	Back-gated monolayer MoS₂ transistor with 1 µm channel and c Back-gated monolayer MoS₂ transistor with 200 nm channel and Control monolayer MoS₂ transistor capped with low-stress SiN	—
Film Thickness	Au contact thickness	50nm	Au	Back-gated monolayer MoS₂ transistor with 1 µm channel and c Back-gated monolayer MoS₂ transistor with 200 nm channel and Control monolayer MoS₂ transistor capped with low-stress SiN	—
Substrate Thickness	SiO₂ thickness	90nm	SiO₂	Back-gated monolayer MoS₂ transistor with 1 µm channel and c Back-gated monolayer MoS₂ transistor with 200 nm channel and Control monolayer MoS₂ transistor capped with low-stress SiN	—

Properties

Type	Label	Value	Material	Sample	Source
Fet Drain Current	saturation current	488uA/um	MoS₂	Back-gated monolayer MoS₂ transistor with 1 µm channel and c	—
Fet Drain Current	median on-state current increase	14%	MoS₂	Back-gated monolayer MoS₂ transistor with 1 µm channel and c	—
Fet Drain Current	median on-state current increase	60%	MoS₂	Back-gated monolayer MoS₂ transistor with 200 nm channel and	—
Fet Drain Current	median on-state current increase	10%	MoS₂	Back-gated monolayer MoS₂ transistor with 1 µm channel and c	—
Fet Drain Current	median on-state current increase	18%	MoS₂	Back-gated monolayer MoS₂ transistor with 200 nm channel and	—
Schottky Barrier Height	effective barrier height	0.06eV	MoS₂	Back-gated monolayer MoS₂ transistor with 200 nm channel and	—
Schottky Barrier Height	effective barrier height	0.15eV	MoS₂	Control monolayer MoS₂ transistor capped with low-stress SiN	—
Sheet Stress	intrinsic tensile stress	600MPa	SiNx	Back-gated monolayer MoS₂ transistor with 1 µm channel and c Back-gated monolayer MoS₂ transistor with 200 nm channel and	—
Sheet Stress	intrinsic stress	50 to 100MPa	SiNx	Control monolayer MoS₂ transistor capped with low-stress SiN	—
Film Thickness	SiNx thickness	75nm	SiNx	Back-gated monolayer MoS₂ transistor with 1 µm channel and c Back-gated monolayer MoS₂ transistor with 200 nm channel and	—
Film Thickness	AlOx thickness	10nm	AlOx	Back-gated monolayer MoS₂ transistor with 1 µm channel and c Back-gated monolayer MoS₂ transistor with 200 nm channel and Control monolayer MoS₂ transistor capped with low-stress SiN	—
Film Thickness	Al thickness	1.5nm	Al	Back-gated monolayer MoS₂ transistor with 1 µm channel and c Back-gated monolayer MoS₂ transistor with 200 nm channel and Control monolayer MoS₂ transistor capped with low-stress SiN	—
Film Thickness	Au contact thickness	50nm	Au	Back-gated monolayer MoS₂ transistor with 1 µm channel and c Back-gated monolayer MoS₂ transistor with 200 nm channel and Control monolayer MoS₂ transistor capped with low-stress SiN	—
Substrate Thickness	SiO₂ thickness	90nm	SiO₂	Back-gated monolayer MoS₂ transistor with 1 µm channel and c Back-gated monolayer MoS₂ transistor with 200 nm channel and Control monolayer MoS₂ transistor capped with low-stress SiN	—

Properties

Type	Label	Value	Material	Sample	Source
Fet Drain Current	saturation current	488uA/um	MoS₂	Back-gated monolayer MoS₂ transistor with 1 µm channel and c	—
Fet Drain Current	median on-state current increase	14%	MoS₂	Back-gated monolayer MoS₂ transistor with 1 µm channel and c	—
Fet Drain Current	median on-state current increase	60%	MoS₂	Back-gated monolayer MoS₂ transistor with 200 nm channel and	—
Fet Drain Current	median on-state current increase	10%	MoS₂	Back-gated monolayer MoS₂ transistor with 1 µm channel and c	—
Fet Drain Current	median on-state current increase	18%	MoS₂	Back-gated monolayer MoS₂ transistor with 200 nm channel and	—
Schottky Barrier Height	effective barrier height	0.06eV	MoS₂	Back-gated monolayer MoS₂ transistor with 200 nm channel and	—
Schottky Barrier Height	effective barrier height	0.15eV	MoS₂	Control monolayer MoS₂ transistor capped with low-stress SiN	—
Sheet Stress	intrinsic tensile stress	600MPa	SiNx	Back-gated monolayer MoS₂ transistor with 1 µm channel and c Back-gated monolayer MoS₂ transistor with 200 nm channel and	—
Sheet Stress	intrinsic stress	50 to 100MPa	SiNx	Control monolayer MoS₂ transistor capped with low-stress SiN	—
Film Thickness	SiNx thickness	75nm	SiNx	Back-gated monolayer MoS₂ transistor with 1 µm channel and c Back-gated monolayer MoS₂ transistor with 200 nm channel and	—
Film Thickness	AlOx thickness	10nm	AlOx	Back-gated monolayer MoS₂ transistor with 1 µm channel and c Back-gated monolayer MoS₂ transistor with 200 nm channel and Control monolayer MoS₂ transistor capped with low-stress SiN	—
Film Thickness	Al thickness	1.5nm	Al	Back-gated monolayer MoS₂ transistor with 1 µm channel and c Back-gated monolayer MoS₂ transistor with 200 nm channel and Control monolayer MoS₂ transistor capped with low-stress SiN	—
Film Thickness	Au contact thickness	50nm	Au	Back-gated monolayer MoS₂ transistor with 1 µm channel and c Back-gated monolayer MoS₂ transistor with 200 nm channel and Control monolayer MoS₂ transistor capped with low-stress SiN	—
Substrate Thickness	SiO₂ thickness	90nm	SiO₂	Back-gated monolayer MoS₂ transistor with 1 µm channel and c Back-gated monolayer MoS₂ transistor with 200 nm channel and Control monolayer MoS₂ transistor capped with low-stress SiN	—

Properties

Type	Label	Value	Material	Sample	Source
Fet Drain Current	saturation current	488uA/um	MoS₂	Back-gated monolayer MoS₂ transistor with 1 µm channel and c	—
Fet Drain Current	median on-state current increase	14%	MoS₂	Back-gated monolayer MoS₂ transistor with 1 µm channel and c	—
Fet Drain Current	median on-state current increase	60%	MoS₂	Back-gated monolayer MoS₂ transistor with 200 nm channel and	—
Fet Drain Current	median on-state current increase	10%	MoS₂	Back-gated monolayer MoS₂ transistor with 1 µm channel and c	—
Fet Drain Current	median on-state current increase	18%	MoS₂	Back-gated monolayer MoS₂ transistor with 200 nm channel and	—
Schottky Barrier Height	effective barrier height	0.06eV	MoS₂	Back-gated monolayer MoS₂ transistor with 200 nm channel and	—
Schottky Barrier Height	effective barrier height	0.15eV	MoS₂	Control monolayer MoS₂ transistor capped with low-stress SiN	—
Sheet Stress	intrinsic tensile stress	600MPa	SiNx	Back-gated monolayer MoS₂ transistor with 1 µm channel and c Back-gated monolayer MoS₂ transistor with 200 nm channel and	—
Sheet Stress	intrinsic stress	50 to 100MPa	SiNx	Control monolayer MoS₂ transistor capped with low-stress SiN	—
Film Thickness	SiNx thickness	75nm	SiNx	Back-gated monolayer MoS₂ transistor with 1 µm channel and c Back-gated monolayer MoS₂ transistor with 200 nm channel and	—
Film Thickness	AlOx thickness	10nm	AlOx	Back-gated monolayer MoS₂ transistor with 1 µm channel and c Back-gated monolayer MoS₂ transistor with 200 nm channel and Control monolayer MoS₂ transistor capped with low-stress SiN	—
Film Thickness	Al thickness	1.5nm	Al	Back-gated monolayer MoS₂ transistor with 1 µm channel and c Back-gated monolayer MoS₂ transistor with 200 nm channel and Control monolayer MoS₂ transistor capped with low-stress SiN	—
Film Thickness	Au contact thickness	50nm	Au	Back-gated monolayer MoS₂ transistor with 1 µm channel and c Back-gated monolayer MoS₂ transistor with 200 nm channel and Control monolayer MoS₂ transistor capped with low-stress SiN	—
Substrate Thickness	SiO₂ thickness	90nm	SiO₂	Back-gated monolayer MoS₂ transistor with 1 µm channel and c Back-gated monolayer MoS₂ transistor with 200 nm channel and Control monolayer MoS₂ transistor capped with low-stress SiN	—

CMOS-compatible Strain Engineering for High-Performance Monolayer Semiconductor Transistors

Samples

Back-gated monolayer MoS₂ transistor with 1 µm channel and contact lengths, capped sequentially with AlOx and high-stress SiNx on 90 nm SiO₂/p++ Si.

Back-gated monolayer MoS₂ transistor with 200 nm channel and contact lengths, capped sequentially with AlOx and high-stress SiNx on 90 nm SiO₂/p++ Si.

Control monolayer MoS₂ transistor capped with low-stress SiNx on 90 nm SiO₂/p++ Si.

Materials

Why these are connected

CMOS-compatible Strain Engineering for High-Performance Monolayer Semiconductor Transistors

Samples

Back-gated monolayer MoS₂ transistor with 1 µm channel and contact lengths, capped sequentially with AlOx and high-stress SiNx on 90 nm SiO₂/p++ Si.

Back-gated monolayer MoS₂ transistor with 200 nm channel and contact lengths, capped sequentially with AlOx and high-stress SiNx on 90 nm SiO₂/p++ Si.

Control monolayer MoS₂ transistor capped with low-stress SiNx on 90 nm SiO₂/p++ Si.

Materials

Why these are connected

CMOS-compatible Strain Engineering for High-Performance Monolayer Semiconductor Transistors

Samples

Back-gated monolayer MoS₂ transistor with 1 µm channel and contact lengths, capped sequentially with AlOx and high-stress SiNx on 90 nm SiO₂/p++ Si.

Back-gated monolayer MoS₂ transistor with 200 nm channel and contact lengths, capped sequentially with AlOx and high-stress SiNx on 90 nm SiO₂/p++ Si.

Control monolayer MoS₂ transistor capped with low-stress SiNx on 90 nm SiO₂/p++ Si.

Materials

Why these are connected

CMOS-compatible Strain Engineering for High-Performance Monolayer Semiconductor Transistors

Samples

Back-gated monolayer MoS₂ transistor with 1 µm channel and contact lengths, capped sequentially with AlOx and high-stress SiNx on 90 nm SiO₂/p++ Si.

Back-gated monolayer MoS₂ transistor with 200 nm channel and contact lengths, capped sequentially with AlOx and high-stress SiNx on 90 nm SiO₂/p++ Si.

Control monolayer MoS₂ transistor capped with low-stress SiNx on 90 nm SiO₂/p++ Si.

Materials

Why these are connected

CMOS-compatible Strain Engineering for High-Performance Monolayer Semiconductor Transistors

Samples

Back-gated monolayer MoS₂ transistor with 1 µm channel and contact lengths, capped sequentially with AlOx and high-stress SiNx on 90 nm SiO₂/p++ Si.

Back-gated monolayer MoS₂ transistor with 200 nm channel and contact lengths, capped sequentially with AlOx and high-stress SiNx on 90 nm SiO₂/p++ Si.

Control monolayer MoS₂ transistor capped with low-stress SiNx on 90 nm SiO₂/p++ Si.

Materials

Why these are connected

CMOS-compatible Strain Engineering for High-Performance Monolayer Semiconductor Transistors

Samples

Back-gated monolayer MoS₂ transistor with 1 µm channel and contact lengths, capped sequentially with AlOx and high-stress SiNx on 90 nm SiO₂/p++ Si.

Back-gated monolayer MoS₂ transistor with 200 nm channel and contact lengths, capped sequentially with AlOx and high-stress SiNx on 90 nm SiO₂/p++ Si.

Control monolayer MoS₂ transistor capped with low-stress SiNx on 90 nm SiO₂/p++ Si.

Materials

Why these are connected

CMOS-compatible Strain Engineering for High-Performance Monolayer Semiconductor Transistors

Samples

Back-gated monolayer MoS₂ transistor with 1 µm channel and contact lengths, capped sequentially with AlOx and high-stress SiNx on 90 nm SiO₂/p++ Si.

Back-gated monolayer MoS₂ transistor with 200 nm channel and contact lengths, capped sequentially with AlOx and high-stress SiNx on 90 nm SiO₂/p++ Si.

Control monolayer MoS₂ transistor capped with low-stress SiNx on 90 nm SiO₂/p++ Si.

Materials

Why these are connected

CMOS-compatible Strain Engineering for High-Performance Monolayer Semiconductor Transistors

Samples

Back-gated monolayer MoS₂ transistor with 1 µm channel and contact lengths, capped sequentially with AlOx and high-stress SiNx on 90 nm SiO₂/p++ Si.

Back-gated monolayer MoS₂ transistor with 200 nm channel and contact lengths, capped sequentially with AlOx and high-stress SiNx on 90 nm SiO₂/p++ Si.

Control monolayer MoS₂ transistor capped with low-stress SiNx on 90 nm SiO₂/p++ Si.

Materials

Why these are connected

Growth

Processing

Characterization

Properties

Simulations

Growth

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Characterization

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Simulations

Growth

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Simulations

Growth

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Simulations