Abstract

Silicon nitride capping layers can impart strain to monolayer MoS₂ transistors on conventional silicon substrates, enhancing electrical performance with a low thermal budget. The work reports CMOS-compatible strain engineering using plasma-enhanced CVD SiNx, electrical characterization of back-gated and dual-gated devices, Raman and grazing-incidence XRD observations, and finite-element simulations of strain distribution and device performance.

Abstract

Silicon nitride capping layers can impart strain to monolayer MoS₂ transistors on conventional silicon substrates, enhancing electrical performance with a low thermal budget. The work reports CMOS-compatible strain engineering using plasma-enhanced CVD SiNx, electrical characterization of back-gated and dual-gated devices, Raman and grazing-incidence XRD observations, and finite-element simulations of strain distribution and device performance.

Abstract

Silicon nitride capping layers can impart strain to monolayer MoS₂ transistors on conventional silicon substrates, enhancing electrical performance with a low thermal budget. The work reports CMOS-compatible strain engineering using plasma-enhanced CVD SiNx, electrical characterization of back-gated and dual-gated devices, Raman and grazing-incidence XRD observations, and finite-element simulations of strain distribution and device performance.

Abstract

Silicon nitride capping layers can impart strain to monolayer MoS₂ transistors on conventional silicon substrates, enhancing electrical performance with a low thermal budget. The work reports CMOS-compatible strain engineering using plasma-enhanced CVD SiNx, electrical characterization of back-gated and dual-gated devices, Raman and grazing-incidence XRD observations, and finite-element simulations of strain distribution and device performance.