Patent
US 8,629,531STRUCTURE AND METHOD TO REDUCE WAFER WARP FOR GALLIUM NITRIDE ON SILICON WAFER
Ming Chyi Liu
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 8,629,531Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor structure comprising: a dielectric material layer on a silicon substrate, the dielectric material layer being patterned to define a plurality of regions separated by the dielectric material layer, wherein the dielectric material layer has a bottom surface facing a top surface of the silicon substrate; a first buffer layer disposed on the silicon substrate; a heterogeneous buffer layer disposed on the first buffer layer; and a gallium nitride layer selectively grown on the heterogeneous buffer layer only within the plurality of regions, and wherein at least one of the first buffer layer and the heterogeneous buffer layer extends between the top surface of the silicon substrate and the bottom surface of the dielectric material layer to prevent a portion of the dielectric material layer from physically contacting the silicon substrate.
The semiconductor structure of claim 1, wherein the silicon substrate has a (111) oriented surface.
The semiconductor structure of claim 1, wherein the dielectric material layer includes a material selected from the group consisting of silicon oxide, silicon nitride, and silicon oxynitride.
The semiconductor structure of claim 1, wherein the dielectric material layer includes a first set of features extended in a first direction and a second set of features extended in a second direction different from the first direction; and the first set of features intersects the second set of features, defining the plurality of regions. R-339502 _ 1.DOCX 2 SVG 13030645.09-04-2013.HL₇₁₇ZCVPXXIFW3.CLM7433303.1.309.158.2244.245.svg 0.29 6.45 Graph Black and white
The semiconductor structure of claim 1, wherein the first buffer layer includes aluminum nitride (A l N); and the heterogeneous buffer layer includes a graded aluminum gallium nitride (A l GaN) layer.
The semiconductor structure of claim 1, wherein the first buffer layer includes aluminum nitride (A l N); and the heterogeneous buffer layer includes a super lattice structure having one of GaN/A lN, GaN/A l GaN, and A l GaN.
The semiconductor structure of claim 1, wherein each of the plurality of regions corresponds to a chip surrounded by scribe lines.
The semiconductor structure of claim 1, wherein each of the plurality of regions is a field main region including multiple chips. R-339502 _ 1 DOCX 3 SVG 13030645.09-04-2013.HL₇₁₇ZCVPXXIFW3.CLM7433304.1.311.158.2246.245.svg 0.29 6.45 Chemistry Black and white
A semiconductor structure comprising: a dielectric material layer on a silicon substrate, wherein the dielectric material layer is patterned to have a first set of features extended in a first direction and a second set of features extended in a second direction different from the first direction, and the first set of features intersects the second set of features, defining a plurality of regions on the silicon substrate; a first buffer layer disposed on the silicon substrate; a heterogeneous buffer layer disposed on the first buffer layer; and a gallium nitride layer grown on the heterogeneous buffer layer within the plurality of regions, wherein a portion of the gallium nitride layer physically contacts a portion of the dielectric material layer.
The semiconductor structure of claim 12, wherein the dielectric material layer is positioned within scribe lines. original
The semiconductor structure of claim 12, wherein the dielectric material layer is patterned to further have a third set of features extended in a third direction and a fourth set of features extended in a fourth direction, the plurality of regions on the silicon substrate being defined by the first, second, third and fourth sets of features; the third set of features intersects the fourth set of features; and the third and fourth directions are different from each other and different from the first and second directions.
The semiconductor structure of claim 12, wherein the plurality of regions are defined in circular shape.
The semiconductor structure of claim 12, wherein the first buffer layer includes aluminum nitride (A l N); and the heterogeneous buffer layer includes a graded aluminum gallium nitride (A l GaN) layer.
The semiconductor structure of claim 12, wherein the first buffer layer includes aluminum nitride (A l N); and the heterogeneous buffer layer includes a super lattice structure having one of GaN/A lN, GaN/A l GaN, and A l GaN.
The semiconductor structure of claim 12, wherein the dielectric material layer is directly disposed on one of the silicon substrate and the heterogeneous buffer layer.
The semiconductor structure of claim 12, wherein the first set of features include one of solid lines and dashed lines; have a width ranging between about 0.1 micron the and about 5 mm; and are spaced from each other with a spacing ranging between about 100 microns and about 100 mm.
canceled
A method of making an integrated circuit, comprising: forming a dielectric material layer on a silicon substrate; patterning the dielectric material layer into lines, defining a plurality of regions on the silicon substrate; forming a first buffer layer on the silicon substrate; forming a heterogeneous buffer layer on the first buffer layer; and R-339502 1 DOCX 5 SVG 13030645.09-04-2013.HL₇₁₇ZCVPXXIFW3.CLM7433306.1.309.157.2244.244.svg 0.29 6.45 Drawing Black and white selectively epitaxy growing a gallium nitride layer on the heterogeneous buffer layer within the plurality of regions using the dielectric material layer as a hard mask, and wherein the forming and patterning the dielectric material layer are implemented after the forming the heterogeneous buffer layer on the first buffer layer. 24-25.
The method of claim 23, wherein forming the dielectric material layer on the silicon substrate includes forming the dielectric material layer directly on the heterogeneous buffer layer.
The method of claim 23, wherein forming the dielectric material layer on the silicon substrate includes forming the dielectric material layer over the heterogeneous buffer layer and the first buffer layer such that the heterogeneous buffer layer and the first buffer layer are positioned between a portion of the silicon substrate and a portion of the dielectric material layer. previously presented
The method of claim 23, wherein selectively heterogeneous buffer layer within the plurality of hard mask includes growing the gallium nitride R-339502 1 DOCX 6 epitaxy growing the gallium nitride layer on the regions using the dielectric material layer as the layer directly on the heterogeneous buffer layer.
canceled
canceled
canceled
Layer stacks claimed or described, ordered top of device to substrate.
GaN-on-Si semiconductor structure (claim 1)
GaN-on-Si semiconductor structure (claim 12)
Materials described outside the worked examples.
silicon substrate
Si
dielectric material layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.1–20000 nm | — |
Thickness | 100000–100000000 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,629,531Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor structure comprising: a dielectric material layer on a silicon substrate, the dielectric material layer being patterned to define a plurality of regions separated by the dielectric material layer, wherein the dielectric material layer has a bottom surface facing a top surface of the silicon substrate; a first buffer layer disposed on the silicon substrate; a heterogeneous buffer layer disposed on the first buffer layer; and a gallium nitride layer selectively grown on the heterogeneous buffer layer only within the plurality of regions, and wherein at least one of the first buffer layer and the heterogeneous buffer layer extends between the top surface of the silicon substrate and the bottom surface of the dielectric material layer to prevent a portion of the dielectric material layer from physically contacting the silicon substrate.
The semiconductor structure of claim 1, wherein the silicon substrate has a (111) oriented surface.
The semiconductor structure of claim 1, wherein the dielectric material layer includes a material selected from the group consisting of silicon oxide, silicon nitride, and silicon oxynitride.
The semiconductor structure of claim 1, wherein the dielectric material layer includes a first set of features extended in a first direction and a second set of features extended in a second direction different from the first direction; and the first set of features intersects the second set of features, defining the plurality of regions. R-339502 _ 1.DOCX 2 SVG 13030645.09-04-2013.HL₇₁₇ZCVPXXIFW3.CLM7433303.1.309.158.2244.245.svg 0.29 6.45 Graph Black and white
The semiconductor structure of claim 1, wherein the first buffer layer includes aluminum nitride (A l N); and the heterogeneous buffer layer includes a graded aluminum gallium nitride (A l GaN) layer.
The semiconductor structure of claim 1, wherein the first buffer layer includes aluminum nitride (A l N); and the heterogeneous buffer layer includes a super lattice structure having one of GaN/A lN, GaN/A l GaN, and A l GaN.
The semiconductor structure of claim 1, wherein each of the plurality of regions corresponds to a chip surrounded by scribe lines.
The semiconductor structure of claim 1, wherein each of the plurality of regions is a field main region including multiple chips. R-339502 _ 1 DOCX 3 SVG 13030645.09-04-2013.HL₇₁₇ZCVPXXIFW3.CLM7433304.1.311.158.2246.245.svg 0.29 6.45 Chemistry Black and white
A semiconductor structure comprising: a dielectric material layer on a silicon substrate, wherein the dielectric material layer is patterned to have a first set of features extended in a first direction and a second set of features extended in a second direction different from the first direction, and the first set of features intersects the second set of features, defining a plurality of regions on the silicon substrate; a first buffer layer disposed on the silicon substrate; a heterogeneous buffer layer disposed on the first buffer layer; and a gallium nitride layer grown on the heterogeneous buffer layer within the plurality of regions, wherein a portion of the gallium nitride layer physically contacts a portion of the dielectric material layer.
The semiconductor structure of claim 12, wherein the dielectric material layer is positioned within scribe lines. original
The semiconductor structure of claim 12, wherein the dielectric material layer is patterned to further have a third set of features extended in a third direction and a fourth set of features extended in a fourth direction, the plurality of regions on the silicon substrate being defined by the first, second, third and fourth sets of features; the third set of features intersects the fourth set of features; and the third and fourth directions are different from each other and different from the first and second directions.
The semiconductor structure of claim 12, wherein the plurality of regions are defined in circular shape.
The semiconductor structure of claim 12, wherein the first buffer layer includes aluminum nitride (A l N); and the heterogeneous buffer layer includes a graded aluminum gallium nitride (A l GaN) layer.
The semiconductor structure of claim 12, wherein the first buffer layer includes aluminum nitride (A l N); and the heterogeneous buffer layer includes a super lattice structure having one of GaN/A lN, GaN/A l GaN, and A l GaN.
The semiconductor structure of claim 12, wherein the dielectric material layer is directly disposed on one of the silicon substrate and the heterogeneous buffer layer.
The semiconductor structure of claim 12, wherein the first set of features include one of solid lines and dashed lines; have a width ranging between about 0.1 micron the and about 5 mm; and are spaced from each other with a spacing ranging between about 100 microns and about 100 mm.
canceled
A method of making an integrated circuit, comprising: forming a dielectric material layer on a silicon substrate; patterning the dielectric material layer into lines, defining a plurality of regions on the silicon substrate; forming a first buffer layer on the silicon substrate; forming a heterogeneous buffer layer on the first buffer layer; and R-339502 1 DOCX 5 SVG 13030645.09-04-2013.HL₇₁₇ZCVPXXIFW3.CLM7433306.1.309.157.2244.244.svg 0.29 6.45 Drawing Black and white selectively epitaxy growing a gallium nitride layer on the heterogeneous buffer layer within the plurality of regions using the dielectric material layer as a hard mask, and wherein the forming and patterning the dielectric material layer are implemented after the forming the heterogeneous buffer layer on the first buffer layer. 24-25.
The method of claim 23, wherein forming the dielectric material layer on the silicon substrate includes forming the dielectric material layer directly on the heterogeneous buffer layer.
The method of claim 23, wherein forming the dielectric material layer on the silicon substrate includes forming the dielectric material layer over the heterogeneous buffer layer and the first buffer layer such that the heterogeneous buffer layer and the first buffer layer are positioned between a portion of the silicon substrate and a portion of the dielectric material layer. previously presented
The method of claim 23, wherein selectively heterogeneous buffer layer within the plurality of hard mask includes growing the gallium nitride R-339502 1 DOCX 6 epitaxy growing the gallium nitride layer on the regions using the dielectric material layer as the layer directly on the heterogeneous buffer layer.
canceled
canceled
canceled
Layer stacks claimed or described, ordered top of device to substrate.
GaN-on-Si semiconductor structure (claim 1)
GaN-on-Si semiconductor structure (claim 12)
Materials described outside the worked examples.
silicon substrate
Si
dielectric material layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.1–20000 nm | — |
Thickness | 100000–100000000 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,629,531Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor structure comprising: a dielectric material layer on a silicon substrate, the dielectric material layer being patterned to define a plurality of regions separated by the dielectric material layer, wherein the dielectric material layer has a bottom surface facing a top surface of the silicon substrate; a first buffer layer disposed on the silicon substrate; a heterogeneous buffer layer disposed on the first buffer layer; and a gallium nitride layer selectively grown on the heterogeneous buffer layer only within the plurality of regions, and wherein at least one of the first buffer layer and the heterogeneous buffer layer extends between the top surface of the silicon substrate and the bottom surface of the dielectric material layer to prevent a portion of the dielectric material layer from physically contacting the silicon substrate.
The semiconductor structure of claim 1, wherein the silicon substrate has a (111) oriented surface.
The semiconductor structure of claim 1, wherein the dielectric material layer includes a material selected from the group consisting of silicon oxide, silicon nitride, and silicon oxynitride.
The semiconductor structure of claim 1, wherein the dielectric material layer includes a first set of features extended in a first direction and a second set of features extended in a second direction different from the first direction; and the first set of features intersects the second set of features, defining the plurality of regions. R-339502 _ 1.DOCX 2 SVG 13030645.09-04-2013.HL₇₁₇ZCVPXXIFW3.CLM7433303.1.309.158.2244.245.svg 0.29 6.45 Graph Black and white
The semiconductor structure of claim 1, wherein the first buffer layer includes aluminum nitride (A l N); and the heterogeneous buffer layer includes a graded aluminum gallium nitride (A l GaN) layer.
The semiconductor structure of claim 1, wherein the first buffer layer includes aluminum nitride (A l N); and the heterogeneous buffer layer includes a super lattice structure having one of GaN/A lN, GaN/A l GaN, and A l GaN.
The semiconductor structure of claim 1, wherein each of the plurality of regions corresponds to a chip surrounded by scribe lines.
The semiconductor structure of claim 1, wherein each of the plurality of regions is a field main region including multiple chips. R-339502 _ 1 DOCX 3 SVG 13030645.09-04-2013.HL₇₁₇ZCVPXXIFW3.CLM7433304.1.311.158.2246.245.svg 0.29 6.45 Chemistry Black and white
A semiconductor structure comprising: a dielectric material layer on a silicon substrate, wherein the dielectric material layer is patterned to have a first set of features extended in a first direction and a second set of features extended in a second direction different from the first direction, and the first set of features intersects the second set of features, defining a plurality of regions on the silicon substrate; a first buffer layer disposed on the silicon substrate; a heterogeneous buffer layer disposed on the first buffer layer; and a gallium nitride layer grown on the heterogeneous buffer layer within the plurality of regions, wherein a portion of the gallium nitride layer physically contacts a portion of the dielectric material layer.
The semiconductor structure of claim 12, wherein the dielectric material layer is positioned within scribe lines. original
The semiconductor structure of claim 12, wherein the dielectric material layer is patterned to further have a third set of features extended in a third direction and a fourth set of features extended in a fourth direction, the plurality of regions on the silicon substrate being defined by the first, second, third and fourth sets of features; the third set of features intersects the fourth set of features; and the third and fourth directions are different from each other and different from the first and second directions.
The semiconductor structure of claim 12, wherein the plurality of regions are defined in circular shape.
The semiconductor structure of claim 12, wherein the first buffer layer includes aluminum nitride (A l N); and the heterogeneous buffer layer includes a graded aluminum gallium nitride (A l GaN) layer.
The semiconductor structure of claim 12, wherein the first buffer layer includes aluminum nitride (A l N); and the heterogeneous buffer layer includes a super lattice structure having one of GaN/A lN, GaN/A l GaN, and A l GaN.
The semiconductor structure of claim 12, wherein the dielectric material layer is directly disposed on one of the silicon substrate and the heterogeneous buffer layer.
The semiconductor structure of claim 12, wherein the first set of features include one of solid lines and dashed lines; have a width ranging between about 0.1 micron the and about 5 mm; and are spaced from each other with a spacing ranging between about 100 microns and about 100 mm.
canceled
A method of making an integrated circuit, comprising: forming a dielectric material layer on a silicon substrate; patterning the dielectric material layer into lines, defining a plurality of regions on the silicon substrate; forming a first buffer layer on the silicon substrate; forming a heterogeneous buffer layer on the first buffer layer; and R-339502 1 DOCX 5 SVG 13030645.09-04-2013.HL₇₁₇ZCVPXXIFW3.CLM7433306.1.309.157.2244.244.svg 0.29 6.45 Drawing Black and white selectively epitaxy growing a gallium nitride layer on the heterogeneous buffer layer within the plurality of regions using the dielectric material layer as a hard mask, and wherein the forming and patterning the dielectric material layer are implemented after the forming the heterogeneous buffer layer on the first buffer layer. 24-25.
The method of claim 23, wherein forming the dielectric material layer on the silicon substrate includes forming the dielectric material layer directly on the heterogeneous buffer layer.
The method of claim 23, wherein forming the dielectric material layer on the silicon substrate includes forming the dielectric material layer over the heterogeneous buffer layer and the first buffer layer such that the heterogeneous buffer layer and the first buffer layer are positioned between a portion of the silicon substrate and a portion of the dielectric material layer. previously presented
The method of claim 23, wherein selectively heterogeneous buffer layer within the plurality of hard mask includes growing the gallium nitride R-339502 1 DOCX 6 epitaxy growing the gallium nitride layer on the regions using the dielectric material layer as the layer directly on the heterogeneous buffer layer.
canceled
canceled
canceled
Layer stacks claimed or described, ordered top of device to substrate.
GaN-on-Si semiconductor structure (claim 1)
GaN-on-Si semiconductor structure (claim 12)
Materials described outside the worked examples.
silicon substrate
Si
dielectric material layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.1–20000 nm | — |
Thickness | 100000–100000000 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,629,531Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor structure comprising: a dielectric material layer on a silicon substrate, the dielectric material layer being patterned to define a plurality of regions separated by the dielectric material layer, wherein the dielectric material layer has a bottom surface facing a top surface of the silicon substrate; a first buffer layer disposed on the silicon substrate; a heterogeneous buffer layer disposed on the first buffer layer; and a gallium nitride layer selectively grown on the heterogeneous buffer layer only within the plurality of regions, and wherein at least one of the first buffer layer and the heterogeneous buffer layer extends between the top surface of the silicon substrate and the bottom surface of the dielectric material layer to prevent a portion of the dielectric material layer from physically contacting the silicon substrate.
The semiconductor structure of claim 1, wherein the silicon substrate has a (111) oriented surface.
The semiconductor structure of claim 1, wherein the dielectric material layer includes a material selected from the group consisting of silicon oxide, silicon nitride, and silicon oxynitride.
The semiconductor structure of claim 1, wherein the dielectric material layer includes a first set of features extended in a first direction and a second set of features extended in a second direction different from the first direction; and the first set of features intersects the second set of features, defining the plurality of regions. R-339502 _ 1.DOCX 2 SVG 13030645.09-04-2013.HL₇₁₇ZCVPXXIFW3.CLM7433303.1.309.158.2244.245.svg 0.29 6.45 Graph Black and white
The semiconductor structure of claim 1, wherein the first buffer layer includes aluminum nitride (A l N); and the heterogeneous buffer layer includes a graded aluminum gallium nitride (A l GaN) layer.
The semiconductor structure of claim 1, wherein the first buffer layer includes aluminum nitride (A l N); and the heterogeneous buffer layer includes a super lattice structure having one of GaN/A lN, GaN/A l GaN, and A l GaN.
The semiconductor structure of claim 1, wherein each of the plurality of regions corresponds to a chip surrounded by scribe lines.
The semiconductor structure of claim 1, wherein each of the plurality of regions is a field main region including multiple chips. R-339502 _ 1 DOCX 3 SVG 13030645.09-04-2013.HL₇₁₇ZCVPXXIFW3.CLM7433304.1.311.158.2246.245.svg 0.29 6.45 Chemistry Black and white
A semiconductor structure comprising: a dielectric material layer on a silicon substrate, wherein the dielectric material layer is patterned to have a first set of features extended in a first direction and a second set of features extended in a second direction different from the first direction, and the first set of features intersects the second set of features, defining a plurality of regions on the silicon substrate; a first buffer layer disposed on the silicon substrate; a heterogeneous buffer layer disposed on the first buffer layer; and a gallium nitride layer grown on the heterogeneous buffer layer within the plurality of regions, wherein a portion of the gallium nitride layer physically contacts a portion of the dielectric material layer.
The semiconductor structure of claim 12, wherein the dielectric material layer is positioned within scribe lines. original
The semiconductor structure of claim 12, wherein the dielectric material layer is patterned to further have a third set of features extended in a third direction and a fourth set of features extended in a fourth direction, the plurality of regions on the silicon substrate being defined by the first, second, third and fourth sets of features; the third set of features intersects the fourth set of features; and the third and fourth directions are different from each other and different from the first and second directions.
The semiconductor structure of claim 12, wherein the plurality of regions are defined in circular shape.
The semiconductor structure of claim 12, wherein the first buffer layer includes aluminum nitride (A l N); and the heterogeneous buffer layer includes a graded aluminum gallium nitride (A l GaN) layer.
The semiconductor structure of claim 12, wherein the first buffer layer includes aluminum nitride (A l N); and the heterogeneous buffer layer includes a super lattice structure having one of GaN/A lN, GaN/A l GaN, and A l GaN.
The semiconductor structure of claim 12, wherein the dielectric material layer is directly disposed on one of the silicon substrate and the heterogeneous buffer layer.
The semiconductor structure of claim 12, wherein the first set of features include one of solid lines and dashed lines; have a width ranging between about 0.1 micron the and about 5 mm; and are spaced from each other with a spacing ranging between about 100 microns and about 100 mm.
canceled
A method of making an integrated circuit, comprising: forming a dielectric material layer on a silicon substrate; patterning the dielectric material layer into lines, defining a plurality of regions on the silicon substrate; forming a first buffer layer on the silicon substrate; forming a heterogeneous buffer layer on the first buffer layer; and R-339502 1 DOCX 5 SVG 13030645.09-04-2013.HL₇₁₇ZCVPXXIFW3.CLM7433306.1.309.157.2244.244.svg 0.29 6.45 Drawing Black and white selectively epitaxy growing a gallium nitride layer on the heterogeneous buffer layer within the plurality of regions using the dielectric material layer as a hard mask, and wherein the forming and patterning the dielectric material layer are implemented after the forming the heterogeneous buffer layer on the first buffer layer. 24-25.
The method of claim 23, wherein forming the dielectric material layer on the silicon substrate includes forming the dielectric material layer directly on the heterogeneous buffer layer.
The method of claim 23, wherein forming the dielectric material layer on the silicon substrate includes forming the dielectric material layer over the heterogeneous buffer layer and the first buffer layer such that the heterogeneous buffer layer and the first buffer layer are positioned between a portion of the silicon substrate and a portion of the dielectric material layer. previously presented
The method of claim 23, wherein selectively heterogeneous buffer layer within the plurality of hard mask includes growing the gallium nitride R-339502 1 DOCX 6 epitaxy growing the gallium nitride layer on the regions using the dielectric material layer as the layer directly on the heterogeneous buffer layer.
canceled
canceled
canceled
Layer stacks claimed or described, ordered top of device to substrate.
GaN-on-Si semiconductor structure (claim 1)
GaN-on-Si semiconductor structure (claim 12)
Materials described outside the worked examples.
silicon substrate
Si
dielectric material layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.1–20000 nm | — |
Thickness | 100000–100000000 nm |
Related documents with shared materials, methods, properties, or citations.
aluminum nitride
AlN
graded aluminum gallium nitride
AlGaN
gallium nitride
GaN
silicon oxide
SiO₂
silicon nitride
Si₃N₄
silicon oxynitride
SiON
GaN/AlN superlattice
GaN/AlN
GaN/AlGaN superlattice
GaN/AlGaN
trimethylaluminum
Al(CH₃)3
triethylaluminum
Al(C₂H₅)3
ammonia
NH₃
| — |
Thickness | 20–100 Å | — |
Thickness | 30–500 Å | — |
Thickness | 1–20 µm | — |
Thickness | 1–100 nm | — |
Thickness | 1–10 nm | — |
Thickness | 100–5000000 nm | — |
aluminum nitride
AlN
graded aluminum gallium nitride
AlGaN
gallium nitride
GaN
silicon oxide
SiO₂
silicon nitride
Si₃N₄
silicon oxynitride
SiON
GaN/AlN superlattice
GaN/AlN
GaN/AlGaN superlattice
GaN/AlGaN
trimethylaluminum
Al(CH₃)3
triethylaluminum
Al(C₂H₅)3
ammonia
NH₃
| — |
Thickness | 20–100 Å | — |
Thickness | 30–500 Å | — |
Thickness | 1–20 µm | — |
Thickness | 1–100 nm | — |
Thickness | 1–10 nm | — |
Thickness | 100–5000000 nm | — |
aluminum nitride
AlN
graded aluminum gallium nitride
AlGaN
gallium nitride
GaN
silicon oxide
SiO₂
silicon nitride
Si₃N₄
silicon oxynitride
SiON
GaN/AlN superlattice
GaN/AlN
GaN/AlGaN superlattice
GaN/AlGaN
trimethylaluminum
Al(CH₃)3
triethylaluminum
Al(C₂H₅)3
ammonia
NH₃
| — |
Thickness | 20–100 Å | — |
Thickness | 30–500 Å | — |
Thickness | 1–20 µm | — |
Thickness | 1–100 nm | — |
Thickness | 1–10 nm | — |
Thickness | 100–5000000 nm | — |
aluminum nitride
AlN
graded aluminum gallium nitride
AlGaN
gallium nitride
GaN
silicon oxide
SiO₂
silicon nitride
Si₃N₄
silicon oxynitride
SiON
GaN/AlN superlattice
GaN/AlN
GaN/AlGaN superlattice
GaN/AlGaN
trimethylaluminum
Al(CH₃)3
triethylaluminum
Al(C₂H₅)3
ammonia
NH₃
| — |
Thickness | 20–100 Å | — |
Thickness | 30–500 Å | — |
Thickness | 1–20 µm | — |
Thickness | 1–100 nm | — |
Thickness | 1–10 nm | — |
Thickness | 100–5000000 nm | — |