Patent
US 9,608,160POLARIZATION FREE GALLIUM NITRIDE-BASED PHOTONIC DEVICES ON NANOPATTERNED SILICON
Can Bayram
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 9,608,160Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross sectional view of a(100) silicon substrate that can be employed in one embodiment of the present application. [0009]
FIG. 2 after forming first openings extending through the dielectric material layer to provide patterned dielectric material structures. [0011]
FIG. 3 after forming second openings within the silicon substrate each of which exposes a surface of the silicon substrate having a(111) crystal plane. [0012]
FIG. 4 after forming a buffer layer on exposed surfaces of the patterned dielectric material structures and the silicon substrate. [0013]
FIG. 5 after forming a dual phase Group III nitride structure filling a space between each neighboring pair of the patterned dielectric material structures and …
FIG. 6 after removing portions of the buffer layer from an uppermost surface of each patterned dielectric material structure. YO R₉₂₀₁₅₀₈₅₂U S 1 Page 4 of 22 …
FIG. 7 is a scanning electron micrograph (SEM) of a structure including a dual phase gallium nitride structure integrated on a(100) silicon substrate that is …
FIG. 8 after epitaxially growing at least one Group III nitride layer over an uppermost surface of each dual phase Group III nitride structure. [0017]
FIG. 9 is a cross sectional view of the structure of
FIG. 10 illustrates components of the at least one Group III nitride layer that provides a laser diode.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for forming a semiconductor structure comprising: forming a dielectric material layer on an uppermost surface of a (100) silicon substrate; patterning the dielectric material layer forming a plurality of patterned dielectric material structures on portions of the uppermost surface of the (100) silicon substrate and exposing other portions of the uppermost surface of the (100) silicon substrate; etching the exposed another portions of the uppermost surface of the (100) silicon substrate to form a plurality of openings within the (100) silicon substrate, each of the plurality of openings exposing a surface having a (111) crystal plane within the (100) silicon substrate; forming a buffer layer on exposed surfaces of the plurality of patterned dielectric material structures and the (100) silicon substrate; forming a dual phase Group III nitride structure filling a space between each neighboring pair of the plurality of patterned dielectric material structures and one of the plurality of openings located beneath the space, wherein the dual phase Group III nitride structure comprises a wurtzite phase region and a cubic phase region, wherein the cubic phase region defines an uppermost surface of the Group III nitride structure; and epitaxially growing at least one Group-I II nitride layer on the cubic phase region of the dual phase Group-I II nitride structure, wherein the epitaxially growing the at least one Group-III nitride layer comprises: 2 I \IBM\105\32940\US M08695\2016-09-29 REPLY FILEDNFRESP\32940.aml.doc
The method of Claim 1, wherein the cubic phase region of the dual phase Group III nitride structure has a shape of an inverted triangular and wherein a base of the inverted triangular constitutes the entirety of the uppermost surface of the dual phase Group III nitride structure.
The method of Claim 1, further comprising removing a horizontal portion of the buffer layer from an uppermost surface of each of the plurality of patterned dielectric material structures prior to the epitaxially growing the at least one Group III nitride layer.
The method of Claim 1, wherein the buffer layer comprises A lN. 3 I \IBM\105\32940\US M08695\2016-09-29 REPLY FILEDNFRESP\32940.aml.doc
The method of Claim 1, wherein the dual phase Group III nitride layer comprises GaN.
The method of Claim 1, wherein the exposed another portions of the uppermost surface of the (100) silicon substrate is etched by a crystallographic wet etch.
The method of Claim 1, wherein each of the at least one Group III nitride layer has a cubic phase.
The method of Claim 1, wherein the dual phase Group III nitride structure is formed at a temperature ranging from 1100 ° C to 1250 °C.
The method of Claim 1, wherein the at least one Group III nitride layer is formed at a temperature ranging from 750 ° C to 950 °C.
canceled
canceled
A semiconductor structure comprising: a (100) silicon substrate having a plurality of openings located within the (100) silicon substrate, wherein each of the plurality of openings exposes a surface of the (100) silicon substrate having a (111) crystal plane; 4 I \IBM\105\32940\US M08695\2016-09-29 REPLY FILEDNFRESP\32940.aml.doc
The semiconductor structure of Claim 12, wherein the dual phase Group III nitride structure comprises GaN, A l GaN, InGaN, or A l InGaN. 5 I \IBM\105\32940\US M08695\2016-09-29 REPLY FILEDNFRESP\32940.aml.doc
The semiconductor structure of Claim 12, wherein a portion of the dual phase Group III nitride structure within each of the plurality of openings extends above a surface of the (100) silicon substrate having a non-(111) crystal plane.
The semiconductor structure of Claim 12, further comprising a buffer layer portion located between the dual phase Group III nitride structure and the neighboring sidewalls of the plurality of patterned dielectric material structures and surfaces of the (100) silicon substrate within each of the plurality of openings.
The semiconductor structure of Claim 12, wherein the cubic phase region of the dual phase Group III nitride structure has a shape of an inverted triangular and wherein a base of the inverted triangular constitutes the entirety of an uppe rm ost surface of the dual phase Group III nitride structure.
The semiconductor structure of Claim 12, further comprising a cavity within each of the plurality of openings and located beneath the wurtzite phase region of the dual phase Group III nitride structure.
The semiconductor structure of Claim 12, wherein an uppermost surface of the dual phase Group III nitride structure is coplanar with uppermost surfaces of one of the plurality of patterned dielectric material structure. 6 I \IBM\105\32940\US M08695\2016-09-29 REPLY FILEDNFRESP\32940.aml.doc
The semiconductor structure of Claim 12, wherein each of the at least one Group III nitride layer has a cubic phase.
7 I \IBM\105\32940\US M08695\2016-09-29 REPLY FILEDNFRESP\32940.aml.doc canceled
Layer stacks claimed or described, ordered top of device to substrate.
polarization-free Group III nitride photonic semiconductor structure (method)
polarization-free Group III nitride photonic semiconductor structure (product)
Materials described outside the worked examples.
(100) silicon substrate
Si
dual phase Group III nitride structure
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 7 is a scanning electron micrograph (SEM) of a structure including a dual phase gallium nitride structure integrated on a(100) silicon substrate that is …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 2–100 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,608,160Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross sectional view of a(100) silicon substrate that can be employed in one embodiment of the present application. [0009]
FIG. 2 after forming first openings extending through the dielectric material layer to provide patterned dielectric material structures. [0011]
FIG. 3 after forming second openings within the silicon substrate each of which exposes a surface of the silicon substrate having a(111) crystal plane. [0012]
FIG. 4 after forming a buffer layer on exposed surfaces of the patterned dielectric material structures and the silicon substrate. [0013]
FIG. 5 after forming a dual phase Group III nitride structure filling a space between each neighboring pair of the patterned dielectric material structures and …
FIG. 6 after removing portions of the buffer layer from an uppermost surface of each patterned dielectric material structure. YO R₉₂₀₁₅₀₈₅₂U S 1 Page 4 of 22 …
FIG. 7 is a scanning electron micrograph (SEM) of a structure including a dual phase gallium nitride structure integrated on a(100) silicon substrate that is …
FIG. 8 after epitaxially growing at least one Group III nitride layer over an uppermost surface of each dual phase Group III nitride structure. [0017]
FIG. 9 is a cross sectional view of the structure of
FIG. 10 illustrates components of the at least one Group III nitride layer that provides a laser diode.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for forming a semiconductor structure comprising: forming a dielectric material layer on an uppermost surface of a (100) silicon substrate; patterning the dielectric material layer forming a plurality of patterned dielectric material structures on portions of the uppermost surface of the (100) silicon substrate and exposing other portions of the uppermost surface of the (100) silicon substrate; etching the exposed another portions of the uppermost surface of the (100) silicon substrate to form a plurality of openings within the (100) silicon substrate, each of the plurality of openings exposing a surface having a (111) crystal plane within the (100) silicon substrate; forming a buffer layer on exposed surfaces of the plurality of patterned dielectric material structures and the (100) silicon substrate; forming a dual phase Group III nitride structure filling a space between each neighboring pair of the plurality of patterned dielectric material structures and one of the plurality of openings located beneath the space, wherein the dual phase Group III nitride structure comprises a wurtzite phase region and a cubic phase region, wherein the cubic phase region defines an uppermost surface of the Group III nitride structure; and epitaxially growing at least one Group-I II nitride layer on the cubic phase region of the dual phase Group-I II nitride structure, wherein the epitaxially growing the at least one Group-III nitride layer comprises: 2 I \IBM\105\32940\US M08695\2016-09-29 REPLY FILEDNFRESP\32940.aml.doc
The method of Claim 1, wherein the cubic phase region of the dual phase Group III nitride structure has a shape of an inverted triangular and wherein a base of the inverted triangular constitutes the entirety of the uppermost surface of the dual phase Group III nitride structure.
The method of Claim 1, further comprising removing a horizontal portion of the buffer layer from an uppermost surface of each of the plurality of patterned dielectric material structures prior to the epitaxially growing the at least one Group III nitride layer.
The method of Claim 1, wherein the buffer layer comprises A lN. 3 I \IBM\105\32940\US M08695\2016-09-29 REPLY FILEDNFRESP\32940.aml.doc
The method of Claim 1, wherein the dual phase Group III nitride layer comprises GaN.
The method of Claim 1, wherein the exposed another portions of the uppermost surface of the (100) silicon substrate is etched by a crystallographic wet etch.
The method of Claim 1, wherein each of the at least one Group III nitride layer has a cubic phase.
The method of Claim 1, wherein the dual phase Group III nitride structure is formed at a temperature ranging from 1100 ° C to 1250 °C.
The method of Claim 1, wherein the at least one Group III nitride layer is formed at a temperature ranging from 750 ° C to 950 °C.
canceled
canceled
A semiconductor structure comprising: a (100) silicon substrate having a plurality of openings located within the (100) silicon substrate, wherein each of the plurality of openings exposes a surface of the (100) silicon substrate having a (111) crystal plane; 4 I \IBM\105\32940\US M08695\2016-09-29 REPLY FILEDNFRESP\32940.aml.doc
The semiconductor structure of Claim 12, wherein the dual phase Group III nitride structure comprises GaN, A l GaN, InGaN, or A l InGaN. 5 I \IBM\105\32940\US M08695\2016-09-29 REPLY FILEDNFRESP\32940.aml.doc
The semiconductor structure of Claim 12, wherein a portion of the dual phase Group III nitride structure within each of the plurality of openings extends above a surface of the (100) silicon substrate having a non-(111) crystal plane.
The semiconductor structure of Claim 12, further comprising a buffer layer portion located between the dual phase Group III nitride structure and the neighboring sidewalls of the plurality of patterned dielectric material structures and surfaces of the (100) silicon substrate within each of the plurality of openings.
The semiconductor structure of Claim 12, wherein the cubic phase region of the dual phase Group III nitride structure has a shape of an inverted triangular and wherein a base of the inverted triangular constitutes the entirety of an uppe rm ost surface of the dual phase Group III nitride structure.
The semiconductor structure of Claim 12, further comprising a cavity within each of the plurality of openings and located beneath the wurtzite phase region of the dual phase Group III nitride structure.
The semiconductor structure of Claim 12, wherein an uppermost surface of the dual phase Group III nitride structure is coplanar with uppermost surfaces of one of the plurality of patterned dielectric material structure. 6 I \IBM\105\32940\US M08695\2016-09-29 REPLY FILEDNFRESP\32940.aml.doc
The semiconductor structure of Claim 12, wherein each of the at least one Group III nitride layer has a cubic phase.
7 I \IBM\105\32940\US M08695\2016-09-29 REPLY FILEDNFRESP\32940.aml.doc canceled
Layer stacks claimed or described, ordered top of device to substrate.
polarization-free Group III nitride photonic semiconductor structure (method)
polarization-free Group III nitride photonic semiconductor structure (product)
Materials described outside the worked examples.
(100) silicon substrate
Si
dual phase Group III nitride structure
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 7 is a scanning electron micrograph (SEM) of a structure including a dual phase gallium nitride structure integrated on a(100) silicon substrate that is …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 2–100 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,608,160Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross sectional view of a(100) silicon substrate that can be employed in one embodiment of the present application. [0009]
FIG. 2 after forming first openings extending through the dielectric material layer to provide patterned dielectric material structures. [0011]
FIG. 3 after forming second openings within the silicon substrate each of which exposes a surface of the silicon substrate having a(111) crystal plane. [0012]
FIG. 4 after forming a buffer layer on exposed surfaces of the patterned dielectric material structures and the silicon substrate. [0013]
FIG. 5 after forming a dual phase Group III nitride structure filling a space between each neighboring pair of the patterned dielectric material structures and …
FIG. 6 after removing portions of the buffer layer from an uppermost surface of each patterned dielectric material structure. YO R₉₂₀₁₅₀₈₅₂U S 1 Page 4 of 22 …
FIG. 7 is a scanning electron micrograph (SEM) of a structure including a dual phase gallium nitride structure integrated on a(100) silicon substrate that is …
FIG. 8 after epitaxially growing at least one Group III nitride layer over an uppermost surface of each dual phase Group III nitride structure. [0017]
FIG. 9 is a cross sectional view of the structure of
FIG. 10 illustrates components of the at least one Group III nitride layer that provides a laser diode.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for forming a semiconductor structure comprising: forming a dielectric material layer on an uppermost surface of a (100) silicon substrate; patterning the dielectric material layer forming a plurality of patterned dielectric material structures on portions of the uppermost surface of the (100) silicon substrate and exposing other portions of the uppermost surface of the (100) silicon substrate; etching the exposed another portions of the uppermost surface of the (100) silicon substrate to form a plurality of openings within the (100) silicon substrate, each of the plurality of openings exposing a surface having a (111) crystal plane within the (100) silicon substrate; forming a buffer layer on exposed surfaces of the plurality of patterned dielectric material structures and the (100) silicon substrate; forming a dual phase Group III nitride structure filling a space between each neighboring pair of the plurality of patterned dielectric material structures and one of the plurality of openings located beneath the space, wherein the dual phase Group III nitride structure comprises a wurtzite phase region and a cubic phase region, wherein the cubic phase region defines an uppermost surface of the Group III nitride structure; and epitaxially growing at least one Group-I II nitride layer on the cubic phase region of the dual phase Group-I II nitride structure, wherein the epitaxially growing the at least one Group-III nitride layer comprises: 2 I \IBM\105\32940\US M08695\2016-09-29 REPLY FILEDNFRESP\32940.aml.doc
The method of Claim 1, wherein the cubic phase region of the dual phase Group III nitride structure has a shape of an inverted triangular and wherein a base of the inverted triangular constitutes the entirety of the uppermost surface of the dual phase Group III nitride structure.
The method of Claim 1, further comprising removing a horizontal portion of the buffer layer from an uppermost surface of each of the plurality of patterned dielectric material structures prior to the epitaxially growing the at least one Group III nitride layer.
The method of Claim 1, wherein the buffer layer comprises A lN. 3 I \IBM\105\32940\US M08695\2016-09-29 REPLY FILEDNFRESP\32940.aml.doc
The method of Claim 1, wherein the dual phase Group III nitride layer comprises GaN.
The method of Claim 1, wherein the exposed another portions of the uppermost surface of the (100) silicon substrate is etched by a crystallographic wet etch.
The method of Claim 1, wherein each of the at least one Group III nitride layer has a cubic phase.
The method of Claim 1, wherein the dual phase Group III nitride structure is formed at a temperature ranging from 1100 ° C to 1250 °C.
The method of Claim 1, wherein the at least one Group III nitride layer is formed at a temperature ranging from 750 ° C to 950 °C.
canceled
canceled
A semiconductor structure comprising: a (100) silicon substrate having a plurality of openings located within the (100) silicon substrate, wherein each of the plurality of openings exposes a surface of the (100) silicon substrate having a (111) crystal plane; 4 I \IBM\105\32940\US M08695\2016-09-29 REPLY FILEDNFRESP\32940.aml.doc
The semiconductor structure of Claim 12, wherein the dual phase Group III nitride structure comprises GaN, A l GaN, InGaN, or A l InGaN. 5 I \IBM\105\32940\US M08695\2016-09-29 REPLY FILEDNFRESP\32940.aml.doc
The semiconductor structure of Claim 12, wherein a portion of the dual phase Group III nitride structure within each of the plurality of openings extends above a surface of the (100) silicon substrate having a non-(111) crystal plane.
The semiconductor structure of Claim 12, further comprising a buffer layer portion located between the dual phase Group III nitride structure and the neighboring sidewalls of the plurality of patterned dielectric material structures and surfaces of the (100) silicon substrate within each of the plurality of openings.
The semiconductor structure of Claim 12, wherein the cubic phase region of the dual phase Group III nitride structure has a shape of an inverted triangular and wherein a base of the inverted triangular constitutes the entirety of an uppe rm ost surface of the dual phase Group III nitride structure.
The semiconductor structure of Claim 12, further comprising a cavity within each of the plurality of openings and located beneath the wurtzite phase region of the dual phase Group III nitride structure.
The semiconductor structure of Claim 12, wherein an uppermost surface of the dual phase Group III nitride structure is coplanar with uppermost surfaces of one of the plurality of patterned dielectric material structure. 6 I \IBM\105\32940\US M08695\2016-09-29 REPLY FILEDNFRESP\32940.aml.doc
The semiconductor structure of Claim 12, wherein each of the at least one Group III nitride layer has a cubic phase.
7 I \IBM\105\32940\US M08695\2016-09-29 REPLY FILEDNFRESP\32940.aml.doc canceled
Layer stacks claimed or described, ordered top of device to substrate.
polarization-free Group III nitride photonic semiconductor structure (method)
polarization-free Group III nitride photonic semiconductor structure (product)
Materials described outside the worked examples.
(100) silicon substrate
Si
dual phase Group III nitride structure
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 7 is a scanning electron micrograph (SEM) of a structure including a dual phase gallium nitride structure integrated on a(100) silicon substrate that is …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 2–100 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,608,160Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross sectional view of a(100) silicon substrate that can be employed in one embodiment of the present application. [0009]
FIG. 2 after forming first openings extending through the dielectric material layer to provide patterned dielectric material structures. [0011]
FIG. 3 after forming second openings within the silicon substrate each of which exposes a surface of the silicon substrate having a(111) crystal plane. [0012]
FIG. 4 after forming a buffer layer on exposed surfaces of the patterned dielectric material structures and the silicon substrate. [0013]
FIG. 5 after forming a dual phase Group III nitride structure filling a space between each neighboring pair of the patterned dielectric material structures and …
FIG. 6 after removing portions of the buffer layer from an uppermost surface of each patterned dielectric material structure. YO R₉₂₀₁₅₀₈₅₂U S 1 Page 4 of 22 …
FIG. 7 is a scanning electron micrograph (SEM) of a structure including a dual phase gallium nitride structure integrated on a(100) silicon substrate that is …
FIG. 8 after epitaxially growing at least one Group III nitride layer over an uppermost surface of each dual phase Group III nitride structure. [0017]
FIG. 9 is a cross sectional view of the structure of
FIG. 10 illustrates components of the at least one Group III nitride layer that provides a laser diode.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for forming a semiconductor structure comprising: forming a dielectric material layer on an uppermost surface of a (100) silicon substrate; patterning the dielectric material layer forming a plurality of patterned dielectric material structures on portions of the uppermost surface of the (100) silicon substrate and exposing other portions of the uppermost surface of the (100) silicon substrate; etching the exposed another portions of the uppermost surface of the (100) silicon substrate to form a plurality of openings within the (100) silicon substrate, each of the plurality of openings exposing a surface having a (111) crystal plane within the (100) silicon substrate; forming a buffer layer on exposed surfaces of the plurality of patterned dielectric material structures and the (100) silicon substrate; forming a dual phase Group III nitride structure filling a space between each neighboring pair of the plurality of patterned dielectric material structures and one of the plurality of openings located beneath the space, wherein the dual phase Group III nitride structure comprises a wurtzite phase region and a cubic phase region, wherein the cubic phase region defines an uppermost surface of the Group III nitride structure; and epitaxially growing at least one Group-I II nitride layer on the cubic phase region of the dual phase Group-I II nitride structure, wherein the epitaxially growing the at least one Group-III nitride layer comprises: 2 I \IBM\105\32940\US M08695\2016-09-29 REPLY FILEDNFRESP\32940.aml.doc
The method of Claim 1, wherein the cubic phase region of the dual phase Group III nitride structure has a shape of an inverted triangular and wherein a base of the inverted triangular constitutes the entirety of the uppermost surface of the dual phase Group III nitride structure.
The method of Claim 1, further comprising removing a horizontal portion of the buffer layer from an uppermost surface of each of the plurality of patterned dielectric material structures prior to the epitaxially growing the at least one Group III nitride layer.
The method of Claim 1, wherein the buffer layer comprises A lN. 3 I \IBM\105\32940\US M08695\2016-09-29 REPLY FILEDNFRESP\32940.aml.doc
The method of Claim 1, wherein the dual phase Group III nitride layer comprises GaN.
The method of Claim 1, wherein the exposed another portions of the uppermost surface of the (100) silicon substrate is etched by a crystallographic wet etch.
The method of Claim 1, wherein each of the at least one Group III nitride layer has a cubic phase.
The method of Claim 1, wherein the dual phase Group III nitride structure is formed at a temperature ranging from 1100 ° C to 1250 °C.
The method of Claim 1, wherein the at least one Group III nitride layer is formed at a temperature ranging from 750 ° C to 950 °C.
canceled
canceled
A semiconductor structure comprising: a (100) silicon substrate having a plurality of openings located within the (100) silicon substrate, wherein each of the plurality of openings exposes a surface of the (100) silicon substrate having a (111) crystal plane; 4 I \IBM\105\32940\US M08695\2016-09-29 REPLY FILEDNFRESP\32940.aml.doc
The semiconductor structure of Claim 12, wherein the dual phase Group III nitride structure comprises GaN, A l GaN, InGaN, or A l InGaN. 5 I \IBM\105\32940\US M08695\2016-09-29 REPLY FILEDNFRESP\32940.aml.doc
The semiconductor structure of Claim 12, wherein a portion of the dual phase Group III nitride structure within each of the plurality of openings extends above a surface of the (100) silicon substrate having a non-(111) crystal plane.
The semiconductor structure of Claim 12, further comprising a buffer layer portion located between the dual phase Group III nitride structure and the neighboring sidewalls of the plurality of patterned dielectric material structures and surfaces of the (100) silicon substrate within each of the plurality of openings.
The semiconductor structure of Claim 12, wherein the cubic phase region of the dual phase Group III nitride structure has a shape of an inverted triangular and wherein a base of the inverted triangular constitutes the entirety of an uppe rm ost surface of the dual phase Group III nitride structure.
The semiconductor structure of Claim 12, further comprising a cavity within each of the plurality of openings and located beneath the wurtzite phase region of the dual phase Group III nitride structure.
The semiconductor structure of Claim 12, wherein an uppermost surface of the dual phase Group III nitride structure is coplanar with uppermost surfaces of one of the plurality of patterned dielectric material structure. 6 I \IBM\105\32940\US M08695\2016-09-29 REPLY FILEDNFRESP\32940.aml.doc
The semiconductor structure of Claim 12, wherein each of the at least one Group III nitride layer has a cubic phase.
7 I \IBM\105\32940\US M08695\2016-09-29 REPLY FILEDNFRESP\32940.aml.doc canceled
Layer stacks claimed or described, ordered top of device to substrate.
polarization-free Group III nitride photonic semiconductor structure (method)
polarization-free Group III nitride photonic semiconductor structure (product)
Materials described outside the worked examples.
(100) silicon substrate
Si
dual phase Group III nitride structure
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 7 is a scanning electron micrograph (SEM) of a structure including a dual phase gallium nitride structure integrated on a(100) silicon substrate that is …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 2–100 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
buffer layer
AlN buffer layer
AlN
Group III nitride layer (cubic phase)
GaN
AlGaN
InGaN
AlInGaN
dielectric material layer
silicon dioxide
SiO₂
silicon nitride
Si₃N₄
silicon oxynitride
SiON
| — |
Duration | 5–20 minutes | — |
Duration | 5–120 seconds | — |
Duration | 1–20 minutes | — |
Thickness | 10–250 nm | — |
Thickness | 60–80 nm | — |
Duration | 60–7200 s | — |
Thickness | 100–5000 nm | — |
Thickness | 500–1000 nm | — |
Temperature | 750–950 °C | — |
Thickness | 100–500 nm | — |
Temperature | 1100–1250 °C | — |
buffer layer
AlN buffer layer
AlN
Group III nitride layer (cubic phase)
GaN
AlGaN
InGaN
AlInGaN
dielectric material layer
silicon dioxide
SiO₂
silicon nitride
Si₃N₄
silicon oxynitride
SiON
| — |
Duration | 5–20 minutes | — |
Duration | 5–120 seconds | — |
Duration | 1–20 minutes | — |
Thickness | 10–250 nm | — |
Thickness | 60–80 nm | — |
Duration | 60–7200 s | — |
Thickness | 100–5000 nm | — |
Thickness | 500–1000 nm | — |
Temperature | 750–950 °C | — |
Thickness | 100–500 nm | — |
Temperature | 1100–1250 °C | — |
buffer layer
AlN buffer layer
AlN
Group III nitride layer (cubic phase)
GaN
AlGaN
InGaN
AlInGaN
dielectric material layer
silicon dioxide
SiO₂
silicon nitride
Si₃N₄
silicon oxynitride
SiON
| — |
Duration | 5–20 minutes | — |
Duration | 5–120 seconds | — |
Duration | 1–20 minutes | — |
Thickness | 10–250 nm | — |
Thickness | 60–80 nm | — |
Duration | 60–7200 s | — |
Thickness | 100–5000 nm | — |
Thickness | 500–1000 nm | — |
Temperature | 750–950 °C | — |
Thickness | 100–500 nm | — |
Temperature | 1100–1250 °C | — |
buffer layer
AlN buffer layer
AlN
Group III nitride layer (cubic phase)
GaN
AlGaN
InGaN
AlInGaN
dielectric material layer
silicon dioxide
SiO₂
silicon nitride
Si₃N₄
silicon oxynitride
SiON
| — |
Duration | 5–20 minutes | — |
Duration | 5–120 seconds | — |
Duration | 1–20 minutes | — |
Thickness | 10–250 nm | — |
Thickness | 60–80 nm | — |
Duration | 60–7200 s | — |
Thickness | 100–5000 nm | — |
Thickness | 500–1000 nm | — |
Temperature | 750–950 °C | — |
Thickness | 100–500 nm | — |
Temperature | 1100–1250 °C | — |