The enhancement-mode GaN-based HEMT device on the Si substrate according to claim 1, wherein a size of the Si substrate is in the range of 2 inches to 10 inches. Previously presented

The enhancement-mode GaN-based H EMT device on the Si substrate according to claim 1, wherein the AlGaN transition layers have a total of three layers, wherein molar contents of aluminium element in the A l GaN transition layers fro m bottom to top are in turn x, y, and z respectively, and the relationship of l >x>y>z>0 is satisfied, wherein thicknesses of the A I GaN transition layers from bottom to top are in turn hl, h2, and h3 respectively, and the relationship of 300 nm>h3>h2>hl>50 nm is satisfied. Currently amended

The enhancement-mode GaN-based HEMT device on the Si substrate according to claim 1, wherein molar contents of aluminium element in the AI GaN buffer layer) and the A l GaN main buffer layer are m and n respectively, and the relationships of m>0 and n>0 are satisfied. Currently amended

The enhancement-mode GaN-based HEMT device on the Si substrate according to claim 1, wherein the A I GaN/GaN superlattice layer is provided below the GaN channel layer, and has more than 5 periods. Currently amended

(Cur r ently amended) The enhancement-mode GaN-based HEMT device on the Si substrate according to claim 1, wherein a channel of two-dimensional electron gas (2DEG) in high concentration is formed at an interface between the GaN channel layer and the A I GaN barrier layer. Currently amended

(Cu rr ently amended) The enhancement-mode GaN-based HEMT device on the Si substrate according to claim 1, wherein an alloy metal used for electrode metal of the source electrode and the drain electrode on both sides of the top end is a g old-free metal. Currently amended

(Withdrawn-currently amended) A preparation method of the enhancement-mode GaN-based HEMT device on the Si substrate according to claim 1, comprising: 1) annealing a surface of the Si substrate in a reaction chamber at a temperature of 1100 degrees Celsius for 15 minutes; 2) epitaxially growing the A I N nucleation layer on the substrate to provide a nucleation node f or subsequent growth; 3) epitaxially growing the AlGaN transition layers, which have a total of three layers, on the basis of the AIN nucleation layer, wherein molar contents of aluminium element in the A l GaN transition layers decrease in turn, and the thicknesses of the A l GaN transition layers increase in turn; 4) epitaxially growing the A l GaN buffer layer and the AlGaN main buffer layer as the main layers of the device material on the basis of the A l GaN transition layers, wherein the Al composition is greater than zero, and the low temperature A l N insertion layer is interposed therebetween to reduce the cumulative stress o f ' the material; 5) epitaxially growing the AlGaN/GaN superlattice layer which has more than 5 periods, on the basis of the AlGaN main buffer layer; 6) epitaxially growing the GaN channel layer; 7) epitaxially growing the AlkGa(I -k) N barrie r layer, a molar content k o f the aluminium element in the AlkGa v-k)N barrier layer satisfies 0.5>k>0.2; 8) etching the A I GaN barrier layer and the GaN channel layer of the material for mesa isolation, separating the respective devices, a etching depth is in the range of 200 nm to 500 nm; 9) passivation protection: performing passivation protective layer deposition by PVD or CVD method or sputtering method to perform passivation protection for the device; 10) forming a gate electrode recess by etching, etching through the A I GaN ba rrier layer to form the recess, and connecting the bottom of the recess to the GaN channel layer; 11) depositing a S iO 2 passivation protective layer at the recess by PVD or CVD method, and simultaneously the S iO 2 passivation protective layer serving as a gate insulating dielectric layer; 12) depositing a gate electrode dielect r ic layer in the recess by sputtering method; 13) etching the SiO 2 passivation protective layer after photolithography to expose the source electrode window and the drain electrode window; 14) evaporating the Schottky contact metal and the ohmic contact metal in the gate electrode window, the source electrode window and the drain electrode window by electron beam evaporation technique, and after stripping and annealing, forming the gate electrode, a source contact electrode and a drain contact electrode; 1 5) having fo rm ed the surface of the gate elect r ode, the source electrode and the drain electrode by photolithography, obtaining a thickened electrode pattern, and thickening the electrodes by electron beam evaporation technique to complete the device fabrication. Currently amended

The enhancement-mode GaN-based HEMT device on the Si substrate according to claim 1, wherein a size of the Si substrate is in the range of 2 inches to 10 inches. Previously presented

The enhancement-mode GaN-based H EMT device on the Si substrate according to claim 1, wherein the AlGaN transition layers have a total of three layers, wherein molar contents of aluminium element in the A l GaN transition layers fro m bottom to top are in turn x, y, and z respectively, and the relationship of l >x>y>z>0 is satisfied, wherein thicknesses of the A I GaN transition layers from bottom to top are in turn hl, h2, and h3 respectively, and the relationship of 300 nm>h3>h2>hl>50 nm is satisfied. Currently amended

The enhancement-mode GaN-based HEMT device on the Si substrate according to claim 1, wherein molar contents of aluminium element in the AI GaN buffer layer) and the A l GaN main buffer layer are m and n respectively, and the relationships of m>0 and n>0 are satisfied. Currently amended

The enhancement-mode GaN-based HEMT device on the Si substrate according to claim 1, wherein the A I GaN/GaN superlattice layer is provided below the GaN channel layer, and has more than 5 periods. Currently amended

(Cur r ently amended) The enhancement-mode GaN-based HEMT device on the Si substrate according to claim 1, wherein a channel of two-dimensional electron gas (2DEG) in high concentration is formed at an interface between the GaN channel layer and the A I GaN barrier layer. Currently amended

(Cu rr ently amended) The enhancement-mode GaN-based HEMT device on the Si substrate according to claim 1, wherein an alloy metal used for electrode metal of the source electrode and the drain electrode on both sides of the top end is a g old-free metal. Currently amended

(Withdrawn-currently amended) A preparation method of the enhancement-mode GaN-based HEMT device on the Si substrate according to claim 1, comprising: 1) annealing a surface of the Si substrate in a reaction chamber at a temperature of 1100 degrees Celsius for 15 minutes; 2) epitaxially growing the A I N nucleation layer on the substrate to provide a nucleation node f or subsequent growth; 3) epitaxially growing the AlGaN transition layers, which have a total of three layers, on the basis of the AIN nucleation layer, wherein molar contents of aluminium element in the A l GaN transition layers decrease in turn, and the thicknesses of the A l GaN transition layers increase in turn; 4) epitaxially growing the A l GaN buffer layer and the AlGaN main buffer layer as the main layers of the device material on the basis of the A l GaN transition layers, wherein the Al composition is greater than zero, and the low temperature A l N insertion layer is interposed therebetween to reduce the cumulative stress o f ' the material; 5) epitaxially growing the AlGaN/GaN superlattice layer which has more than 5 periods, on the basis of the AlGaN main buffer layer; 6) epitaxially growing the GaN channel layer; 7) epitaxially growing the AlkGa(I -k) N barrie r layer, a molar content k o f the aluminium element in the AlkGa v-k)N barrier layer satisfies 0.5>k>0.2; 8) etching the A I GaN barrier layer and the GaN channel layer of the material for mesa isolation, separating the respective devices, a etching depth is in the range of 200 nm to 500 nm; 9) passivation protection: performing passivation protective layer deposition by PVD or CVD method or sputtering method to perform passivation protection for the device; 10) forming a gate electrode recess by etching, etching through the A I GaN ba rrier layer to form the recess, and connecting the bottom of the recess to the GaN channel layer; 11) depositing a S iO 2 passivation protective layer at the recess by PVD or CVD method, and simultaneously the S iO 2 passivation protective layer serving as a gate insulating dielectric layer; 12) depositing a gate electrode dielect r ic layer in the recess by sputtering method; 13) etching the SiO 2 passivation protective layer after photolithography to expose the source electrode window and the drain electrode window; 14) evaporating the Schottky contact metal and the ohmic contact metal in the gate electrode window, the source electrode window and the drain electrode window by electron beam evaporation technique, and after stripping and annealing, forming the gate electrode, a source contact electrode and a drain contact electrode; 1 5) having fo rm ed the surface of the gate elect r ode, the source electrode and the drain electrode by photolithography, obtaining a thickened electrode pattern, and thickening the electrodes by electron beam evaporation technique to complete the device fabrication. Currently amended

The enhancement-mode GaN-based HEMT device on the Si substrate according to claim 1, wherein a size of the Si substrate is in the range of 2 inches to 10 inches. Previously presented

The enhancement-mode GaN-based H EMT device on the Si substrate according to claim 1, wherein the AlGaN transition layers have a total of three layers, wherein molar contents of aluminium element in the A l GaN transition layers fro m bottom to top are in turn x, y, and z respectively, and the relationship of l >x>y>z>0 is satisfied, wherein thicknesses of the A I GaN transition layers from bottom to top are in turn hl, h2, and h3 respectively, and the relationship of 300 nm>h3>h2>hl>50 nm is satisfied. Currently amended

The enhancement-mode GaN-based HEMT device on the Si substrate according to claim 1, wherein molar contents of aluminium element in the AI GaN buffer layer) and the A l GaN main buffer layer are m and n respectively, and the relationships of m>0 and n>0 are satisfied. Currently amended

The enhancement-mode GaN-based HEMT device on the Si substrate according to claim 1, wherein the A I GaN/GaN superlattice layer is provided below the GaN channel layer, and has more than 5 periods. Currently amended

(Cur r ently amended) The enhancement-mode GaN-based HEMT device on the Si substrate according to claim 1, wherein a channel of two-dimensional electron gas (2DEG) in high concentration is formed at an interface between the GaN channel layer and the A I GaN barrier layer. Currently amended

(Cu rr ently amended) The enhancement-mode GaN-based HEMT device on the Si substrate according to claim 1, wherein an alloy metal used for electrode metal of the source electrode and the drain electrode on both sides of the top end is a g old-free metal. Currently amended

(Withdrawn-currently amended) A preparation method of the enhancement-mode GaN-based HEMT device on the Si substrate according to claim 1, comprising: 1) annealing a surface of the Si substrate in a reaction chamber at a temperature of 1100 degrees Celsius for 15 minutes; 2) epitaxially growing the A I N nucleation layer on the substrate to provide a nucleation node f or subsequent growth; 3) epitaxially growing the AlGaN transition layers, which have a total of three layers, on the basis of the AIN nucleation layer, wherein molar contents of aluminium element in the A l GaN transition layers decrease in turn, and the thicknesses of the A l GaN transition layers increase in turn; 4) epitaxially growing the A l GaN buffer layer and the AlGaN main buffer layer as the main layers of the device material on the basis of the A l GaN transition layers, wherein the Al composition is greater than zero, and the low temperature A l N insertion layer is interposed therebetween to reduce the cumulative stress o f ' the material; 5) epitaxially growing the AlGaN/GaN superlattice layer which has more than 5 periods, on the basis of the AlGaN main buffer layer; 6) epitaxially growing the GaN channel layer; 7) epitaxially growing the AlkGa(I -k) N barrie r layer, a molar content k o f the aluminium element in the AlkGa v-k)N barrier layer satisfies 0.5>k>0.2; 8) etching the A I GaN barrier layer and the GaN channel layer of the material for mesa isolation, separating the respective devices, a etching depth is in the range of 200 nm to 500 nm; 9) passivation protection: performing passivation protective layer deposition by PVD or CVD method or sputtering method to perform passivation protection for the device; 10) forming a gate electrode recess by etching, etching through the A I GaN ba rrier layer to form the recess, and connecting the bottom of the recess to the GaN channel layer; 11) depositing a S iO 2 passivation protective layer at the recess by PVD or CVD method, and simultaneously the S iO 2 passivation protective layer serving as a gate insulating dielectric layer; 12) depositing a gate electrode dielect r ic layer in the recess by sputtering method; 13) etching the SiO 2 passivation protective layer after photolithography to expose the source electrode window and the drain electrode window; 14) evaporating the Schottky contact metal and the ohmic contact metal in the gate electrode window, the source electrode window and the drain electrode window by electron beam evaporation technique, and after stripping and annealing, forming the gate electrode, a source contact electrode and a drain contact electrode; 1 5) having fo rm ed the surface of the gate elect r ode, the source electrode and the drain electrode by photolithography, obtaining a thickened electrode pattern, and thickening the electrodes by electron beam evaporation technique to complete the device fabrication. Currently amended

The enhancement-mode GaN-based HEMT device on the Si substrate according to claim 1, wherein a size of the Si substrate is in the range of 2 inches to 10 inches. Previously presented

The enhancement-mode GaN-based H EMT device on the Si substrate according to claim 1, wherein the AlGaN transition layers have a total of three layers, wherein molar contents of aluminium element in the A l GaN transition layers fro m bottom to top are in turn x, y, and z respectively, and the relationship of l >x>y>z>0 is satisfied, wherein thicknesses of the A I GaN transition layers from bottom to top are in turn hl, h2, and h3 respectively, and the relationship of 300 nm>h3>h2>hl>50 nm is satisfied. Currently amended

The enhancement-mode GaN-based HEMT device on the Si substrate according to claim 1, wherein molar contents of aluminium element in the AI GaN buffer layer) and the A l GaN main buffer layer are m and n respectively, and the relationships of m>0 and n>0 are satisfied. Currently amended

The enhancement-mode GaN-based HEMT device on the Si substrate according to claim 1, wherein the A I GaN/GaN superlattice layer is provided below the GaN channel layer, and has more than 5 periods. Currently amended

(Cur r ently amended) The enhancement-mode GaN-based HEMT device on the Si substrate according to claim 1, wherein a channel of two-dimensional electron gas (2DEG) in high concentration is formed at an interface between the GaN channel layer and the A I GaN barrier layer. Currently amended

(Cu rr ently amended) The enhancement-mode GaN-based HEMT device on the Si substrate according to claim 1, wherein an alloy metal used for electrode metal of the source electrode and the drain electrode on both sides of the top end is a g old-free metal. Currently amended

(Withdrawn-currently amended) A preparation method of the enhancement-mode GaN-based HEMT device on the Si substrate according to claim 1, comprising: 1) annealing a surface of the Si substrate in a reaction chamber at a temperature of 1100 degrees Celsius for 15 minutes; 2) epitaxially growing the A I N nucleation layer on the substrate to provide a nucleation node f or subsequent growth; 3) epitaxially growing the AlGaN transition layers, which have a total of three layers, on the basis of the AIN nucleation layer, wherein molar contents of aluminium element in the A l GaN transition layers decrease in turn, and the thicknesses of the A l GaN transition layers increase in turn; 4) epitaxially growing the A l GaN buffer layer and the AlGaN main buffer layer as the main layers of the device material on the basis of the A l GaN transition layers, wherein the Al composition is greater than zero, and the low temperature A l N insertion layer is interposed therebetween to reduce the cumulative stress o f ' the material; 5) epitaxially growing the AlGaN/GaN superlattice layer which has more than 5 periods, on the basis of the AlGaN main buffer layer; 6) epitaxially growing the GaN channel layer; 7) epitaxially growing the AlkGa(I -k) N barrie r layer, a molar content k o f the aluminium element in the AlkGa v-k)N barrier layer satisfies 0.5>k>0.2; 8) etching the A I GaN barrier layer and the GaN channel layer of the material for mesa isolation, separating the respective devices, a etching depth is in the range of 200 nm to 500 nm; 9) passivation protection: performing passivation protective layer deposition by PVD or CVD method or sputtering method to perform passivation protection for the device; 10) forming a gate electrode recess by etching, etching through the A I GaN ba rrier layer to form the recess, and connecting the bottom of the recess to the GaN channel layer; 11) depositing a S iO 2 passivation protective layer at the recess by PVD or CVD method, and simultaneously the S iO 2 passivation protective layer serving as a gate insulating dielectric layer; 12) depositing a gate electrode dielect r ic layer in the recess by sputtering method; 13) etching the SiO 2 passivation protective layer after photolithography to expose the source electrode window and the drain electrode window; 14) evaporating the Schottky contact metal and the ohmic contact metal in the gate electrode window, the source electrode window and the drain electrode window by electron beam evaporation technique, and after stripping and annealing, forming the gate electrode, a source contact electrode and a drain contact electrode; 1 5) having fo rm ed the surface of the gate elect r ode, the source electrode and the drain electrode by photolithography, obtaining a thickened electrode pattern, and thickening the electrodes by electron beam evaporation technique to complete the device fabrication. Currently amended