Patent
US 12,369,375 B2GALLIUM NITRIDE TRANSISTOR
Edward Yi Chang, Jui-Sheng Wu
NATIONAL YANG MING CHIAO TUNG UNIVERSITY, Hsinchu (TW)·Jul. 22, 2025·US
Copyright © 2026 Matter42. All rights reserved.
Patent
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US 12,369,375 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic cross-sectional view of a ferroelec- tric capacitor structure according to Embodiment 1 of the present invention.
FIG. 2 is a graph showing the relationship between polarization and voltage of the ferroelectric capacitor struc- tures of Embodiment 1 and Comparative …
FIG. 3 is a graph showing the relationship between voltage and current of the ferroelectric capacitor structures of Embodiment 1 and Comparative embodiments 1 …
FIG. 4 shows graphs showing the relationship between polarization and voltage of the ferroelectric capacitor struc- ture according to Comparative embodiment 1 …
FIG. 5 is a graph showing the relationship between polarization and hard breakdown voltage of the ferroelectric capacitor structures of Embodiment 1 and …
FIG. 6 shows In-plane GIXRD patterns of the ferroelec- tric capacitor structures of Embodiment 1 and Comparative embodiment 1 of the present invention after …
FIG. 7B is a schematic cross-sectional view of a part of a composite dielectric layer in the GaN transistor according to Embodiment 2 of the present invention.
FIG. 8B is a graph showing the relationship between voltage and current of the GaN transistor according to 5 Comparative embodiment 4 of the present invention.
FIG. 9 is a graph showing the analysis results of the time-dependent dielectric breakdown reliability of the GaN transistor according to Embodiment 2 of the …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A GaN transistor, comprising: a substrate; a GaN layer disposed on the substrate; a barrier layer disposed on the GaN layer; a source electrode disposed on the barrier layer; a drain electrode disposed on the barrier layer; a composite dielectric layer disposed on the barrier layer and comprising a first seed layer and a doped HZO layer, wherein the first seed layer comprises ZrO2; and a gate electrode disposed on the composite dielectric layer.
The GaN transistor of claim 1, wherein the doped HZO layer is a La-doped HZO layer.
The GaN transistor of claim 1, wherein the first seed layer is a ZrO₂ layer formed by plasma-enhanced atomic layer deposition (PEALD).
The GaN transistor of claim 1, wherein the first seed layer has a thickness ranging from 0.5 nm to 5 nm.
The GaN transistor of claim 1, wherein the composite dielectric layer further comprises a second seed layer, the doped HZO layer is disposed between the first seed layer and the second seed layer, and the second seed layer comprises ZrO2.
The GaN transistor of claim 1, wherein the barrier layer is an AlGaN layer.
The GaN transistor of claim 1, further comprising a passivation layer disposed on the barrier layer, wherein the composite dielectric layer is disposed on the passivation layer.
The GaN transistor of claim 1, wherein the barrier layer further comprises a recess, the composite dielectric layer is disposed in the recess, and the gate electrode is disposed correspondingly to the recess.
The GaN transistor of claim 1, wherein the composite dielectric layer further comprises a high bandgap blocking layer, and the high bandgap blocking layer is disposed between the barrier layer and the doped HZO layer.
The GaN transistor of claim 1, wherein the composite dielectric layer further comprises a charge trapping layer, and the charge trapping layer is disposed between the barrier layer and the doped HZO layer.
Layer stacks claimed or described, ordered top of device to substrate.
GaN transistor (HEMT/FeFET)
Materials described outside the worked examples.
GaN
AlGaN barrier layer
AlGaN
ZrO₂ first seed layer
ZrO₂
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 is a graph showing the relationship between polarization and voltage of the ferroelectric capacitor struc- tures of Embodiment 1 and Comparative …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
first/second ZrO2 seed layer thickness | 0.5–5 nm | ZrO₂ |
doped HZO layer thickness | 5–20 nm |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 1
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Patent
Atlas literature
Patent
US 12,369,375 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic cross-sectional view of a ferroelec- tric capacitor structure according to Embodiment 1 of the present invention.
FIG. 2 is a graph showing the relationship between polarization and voltage of the ferroelectric capacitor struc- tures of Embodiment 1 and Comparative …
FIG. 3 is a graph showing the relationship between voltage and current of the ferroelectric capacitor structures of Embodiment 1 and Comparative embodiments 1 …
FIG. 4 shows graphs showing the relationship between polarization and voltage of the ferroelectric capacitor struc- ture according to Comparative embodiment 1 …
FIG. 5 is a graph showing the relationship between polarization and hard breakdown voltage of the ferroelectric capacitor structures of Embodiment 1 and …
FIG. 6 shows In-plane GIXRD patterns of the ferroelec- tric capacitor structures of Embodiment 1 and Comparative embodiment 1 of the present invention after …
FIG. 7B is a schematic cross-sectional view of a part of a composite dielectric layer in the GaN transistor according to Embodiment 2 of the present invention.
FIG. 8B is a graph showing the relationship between voltage and current of the GaN transistor according to 5 Comparative embodiment 4 of the present invention.
FIG. 9 is a graph showing the analysis results of the time-dependent dielectric breakdown reliability of the GaN transistor according to Embodiment 2 of the …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A GaN transistor, comprising: a substrate; a GaN layer disposed on the substrate; a barrier layer disposed on the GaN layer; a source electrode disposed on the barrier layer; a drain electrode disposed on the barrier layer; a composite dielectric layer disposed on the barrier layer and comprising a first seed layer and a doped HZO layer, wherein the first seed layer comprises ZrO2; and a gate electrode disposed on the composite dielectric layer.
The GaN transistor of claim 1, wherein the doped HZO layer is a La-doped HZO layer.
The GaN transistor of claim 1, wherein the first seed layer is a ZrO₂ layer formed by plasma-enhanced atomic layer deposition (PEALD).
The GaN transistor of claim 1, wherein the first seed layer has a thickness ranging from 0.5 nm to 5 nm.
The GaN transistor of claim 1, wherein the composite dielectric layer further comprises a second seed layer, the doped HZO layer is disposed between the first seed layer and the second seed layer, and the second seed layer comprises ZrO2.
The GaN transistor of claim 1, wherein the barrier layer is an AlGaN layer.
The GaN transistor of claim 1, further comprising a passivation layer disposed on the barrier layer, wherein the composite dielectric layer is disposed on the passivation layer.
The GaN transistor of claim 1, wherein the barrier layer further comprises a recess, the composite dielectric layer is disposed in the recess, and the gate electrode is disposed correspondingly to the recess.
The GaN transistor of claim 1, wherein the composite dielectric layer further comprises a high bandgap blocking layer, and the high bandgap blocking layer is disposed between the barrier layer and the doped HZO layer.
The GaN transistor of claim 1, wherein the composite dielectric layer further comprises a charge trapping layer, and the charge trapping layer is disposed between the barrier layer and the doped HZO layer.
Layer stacks claimed or described, ordered top of device to substrate.
GaN transistor (HEMT/FeFET)
Materials described outside the worked examples.
GaN
AlGaN barrier layer
AlGaN
ZrO₂ first seed layer
ZrO₂
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 is a graph showing the relationship between polarization and voltage of the ferroelectric capacitor struc- tures of Embodiment 1 and Comparative …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
first/second ZrO2 seed layer thickness | 0.5–5 nm | ZrO₂ |
doped HZO layer thickness | 5–20 nm |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 1
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,369,375 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic cross-sectional view of a ferroelec- tric capacitor structure according to Embodiment 1 of the present invention.
FIG. 2 is a graph showing the relationship between polarization and voltage of the ferroelectric capacitor struc- tures of Embodiment 1 and Comparative …
FIG. 3 is a graph showing the relationship between voltage and current of the ferroelectric capacitor structures of Embodiment 1 and Comparative embodiments 1 …
FIG. 4 shows graphs showing the relationship between polarization and voltage of the ferroelectric capacitor struc- ture according to Comparative embodiment 1 …
FIG. 5 is a graph showing the relationship between polarization and hard breakdown voltage of the ferroelectric capacitor structures of Embodiment 1 and …
FIG. 6 shows In-plane GIXRD patterns of the ferroelec- tric capacitor structures of Embodiment 1 and Comparative embodiment 1 of the present invention after …
FIG. 7B is a schematic cross-sectional view of a part of a composite dielectric layer in the GaN transistor according to Embodiment 2 of the present invention.
FIG. 8B is a graph showing the relationship between voltage and current of the GaN transistor according to 5 Comparative embodiment 4 of the present invention.
FIG. 9 is a graph showing the analysis results of the time-dependent dielectric breakdown reliability of the GaN transistor according to Embodiment 2 of the …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A GaN transistor, comprising: a substrate; a GaN layer disposed on the substrate; a barrier layer disposed on the GaN layer; a source electrode disposed on the barrier layer; a drain electrode disposed on the barrier layer; a composite dielectric layer disposed on the barrier layer and comprising a first seed layer and a doped HZO layer, wherein the first seed layer comprises ZrO2; and a gate electrode disposed on the composite dielectric layer.
The GaN transistor of claim 1, wherein the doped HZO layer is a La-doped HZO layer.
The GaN transistor of claim 1, wherein the first seed layer is a ZrO₂ layer formed by plasma-enhanced atomic layer deposition (PEALD).
The GaN transistor of claim 1, wherein the first seed layer has a thickness ranging from 0.5 nm to 5 nm.
The GaN transistor of claim 1, wherein the composite dielectric layer further comprises a second seed layer, the doped HZO layer is disposed between the first seed layer and the second seed layer, and the second seed layer comprises ZrO2.
The GaN transistor of claim 1, wherein the barrier layer is an AlGaN layer.
The GaN transistor of claim 1, further comprising a passivation layer disposed on the barrier layer, wherein the composite dielectric layer is disposed on the passivation layer.
The GaN transistor of claim 1, wherein the barrier layer further comprises a recess, the composite dielectric layer is disposed in the recess, and the gate electrode is disposed correspondingly to the recess.
The GaN transistor of claim 1, wherein the composite dielectric layer further comprises a high bandgap blocking layer, and the high bandgap blocking layer is disposed between the barrier layer and the doped HZO layer.
The GaN transistor of claim 1, wherein the composite dielectric layer further comprises a charge trapping layer, and the charge trapping layer is disposed between the barrier layer and the doped HZO layer.
Layer stacks claimed or described, ordered top of device to substrate.
GaN transistor (HEMT/FeFET)
Materials described outside the worked examples.
GaN
AlGaN barrier layer
AlGaN
ZrO₂ first seed layer
ZrO₂
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 is a graph showing the relationship between polarization and voltage of the ferroelectric capacitor struc- tures of Embodiment 1 and Comparative …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
first/second ZrO2 seed layer thickness | 0.5–5 nm | ZrO₂ |
doped HZO layer thickness | 5–20 nm |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 1
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,369,375 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic cross-sectional view of a ferroelec- tric capacitor structure according to Embodiment 1 of the present invention.
FIG. 2 is a graph showing the relationship between polarization and voltage of the ferroelectric capacitor struc- tures of Embodiment 1 and Comparative …
FIG. 3 is a graph showing the relationship between voltage and current of the ferroelectric capacitor structures of Embodiment 1 and Comparative embodiments 1 …
FIG. 4 shows graphs showing the relationship between polarization and voltage of the ferroelectric capacitor struc- ture according to Comparative embodiment 1 …
FIG. 5 is a graph showing the relationship between polarization and hard breakdown voltage of the ferroelectric capacitor structures of Embodiment 1 and …
FIG. 6 shows In-plane GIXRD patterns of the ferroelec- tric capacitor structures of Embodiment 1 and Comparative embodiment 1 of the present invention after …
FIG. 7B is a schematic cross-sectional view of a part of a composite dielectric layer in the GaN transistor according to Embodiment 2 of the present invention.
FIG. 8B is a graph showing the relationship between voltage and current of the GaN transistor according to 5 Comparative embodiment 4 of the present invention.
FIG. 9 is a graph showing the analysis results of the time-dependent dielectric breakdown reliability of the GaN transistor according to Embodiment 2 of the …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A GaN transistor, comprising: a substrate; a GaN layer disposed on the substrate; a barrier layer disposed on the GaN layer; a source electrode disposed on the barrier layer; a drain electrode disposed on the barrier layer; a composite dielectric layer disposed on the barrier layer and comprising a first seed layer and a doped HZO layer, wherein the first seed layer comprises ZrO2; and a gate electrode disposed on the composite dielectric layer.
The GaN transistor of claim 1, wherein the doped HZO layer is a La-doped HZO layer.
The GaN transistor of claim 1, wherein the first seed layer is a ZrO₂ layer formed by plasma-enhanced atomic layer deposition (PEALD).
The GaN transistor of claim 1, wherein the first seed layer has a thickness ranging from 0.5 nm to 5 nm.
The GaN transistor of claim 1, wherein the composite dielectric layer further comprises a second seed layer, the doped HZO layer is disposed between the first seed layer and the second seed layer, and the second seed layer comprises ZrO2.
The GaN transistor of claim 1, wherein the barrier layer is an AlGaN layer.
The GaN transistor of claim 1, further comprising a passivation layer disposed on the barrier layer, wherein the composite dielectric layer is disposed on the passivation layer.
The GaN transistor of claim 1, wherein the barrier layer further comprises a recess, the composite dielectric layer is disposed in the recess, and the gate electrode is disposed correspondingly to the recess.
The GaN transistor of claim 1, wherein the composite dielectric layer further comprises a high bandgap blocking layer, and the high bandgap blocking layer is disposed between the barrier layer and the doped HZO layer.
The GaN transistor of claim 1, wherein the composite dielectric layer further comprises a charge trapping layer, and the charge trapping layer is disposed between the barrier layer and the doped HZO layer.
Layer stacks claimed or described, ordered top of device to substrate.
GaN transistor (HEMT/FeFET)
Materials described outside the worked examples.
GaN
AlGaN barrier layer
AlGaN
ZrO₂ first seed layer
ZrO₂
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 is a graph showing the relationship between polarization and voltage of the ferroelectric capacitor struc- tures of Embodiment 1 and Comparative …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
first/second ZrO2 seed layer thickness | 0.5–5 nm | ZrO₂ |
doped HZO layer thickness | 5–20 nm |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 1
Related documents with shared materials, methods, properties, or citations.
doped HZO layer
HfxZr₁-xO₂ (doped)
La-doped HZO layer
La:HfxZr₁-xO₂
SiN passivation layer
SiN
Al₂O₃ high bandgap blocking layer
Al₂O₃
HfON charge trapping layer
HfON
AlN nucleation layer
AlN
FIG. 3 is a graph showing the relationship between voltage and current of the ferroelectric capacitor structures of Embodiment 1 and Comparative embodiments 1 …
FIG. 5 is a graph showing the relationship between polarization and hard breakdown voltage of the ferroelectric capacitor structures of Embodiment 1 and …
FIG. 7B is a schematic cross-sectional view of a part of a composite dielectric layer in the GaN transistor according to Embodiment 2 of the present invention.
FIG. 8B is a graph showing the relationship between voltage and current of the GaN transistor according to 5 Comparative embodiment 4 of the present invention.
FIG. 8B is a graph showing the relationship between voltage and current of the GaN transistor according to 5 Comparative embodiment 4 of the present invention.
FIG. 9 is a graph showing the analysis results of the time-dependent dielectric breakdown reliability of the GaN transistor according to Embodiment 2 of the …
FIG. 9 is a graph showing the analysis results of the time-dependent dielectric breakdown reliability of the GaN transistor according to Embodiment 2 of the …
high bandgap blocking layer (Al2O3) thickness | 3–20 nm | Al₂O₃ |
charge trapping layer (HfON) thickness | 3–20 nm | HfON |
AlGaN barrier layer thickness | 10–100 nm | AlGaN |
GaN channel layer thickness | 1–20 µm | GaN |
SiN passivation layer thickness | 10–100 nm | SiN |
La doping amount in La-doped HZO layer | 0.1–2 mol% | La:HfxZr₁-xO₂ |
Hf fraction x in HfxZr1-xO2 (HZO) | 0.3–0.9 dimensionless | HfxZr₁-xO₂ (doped) |
Temperature | ≥ 600 °C | — |
Thickness | 5–15 nm | — |
Thickness | 5–10 nm | — |
Thickness | 0.5–3 nm | — |
Thickness | 0.5–2 nm | — |
Thickness | 3–15 nm | — |
Thickness | 5–13 nm | — |
Thickness | 10–200 nm | — |
Thickness | 50–150 nm | — |
Thickness | 80–120 nm | — |
Thickness | 1–15 µm | — |
Thickness | 1–10 µm | — |
Thickness | 2–5 µm | — |
Thickness | 15–75 nm | — |
Thickness | 15–50 nm | — |
Thickness | 20–75 nm | — |
Thickness | 40–60 nm | — |
doped HZO layer
HfxZr₁-xO₂ (doped)
La-doped HZO layer
La:HfxZr₁-xO₂
SiN passivation layer
SiN
Al₂O₃ high bandgap blocking layer
Al₂O₃
HfON charge trapping layer
HfON
AlN nucleation layer
AlN
FIG. 3 is a graph showing the relationship between voltage and current of the ferroelectric capacitor structures of Embodiment 1 and Comparative embodiments 1 …
FIG. 5 is a graph showing the relationship between polarization and hard breakdown voltage of the ferroelectric capacitor structures of Embodiment 1 and …
FIG. 7B is a schematic cross-sectional view of a part of a composite dielectric layer in the GaN transistor according to Embodiment 2 of the present invention.
FIG. 8B is a graph showing the relationship between voltage and current of the GaN transistor according to 5 Comparative embodiment 4 of the present invention.
FIG. 8B is a graph showing the relationship between voltage and current of the GaN transistor according to 5 Comparative embodiment 4 of the present invention.
FIG. 9 is a graph showing the analysis results of the time-dependent dielectric breakdown reliability of the GaN transistor according to Embodiment 2 of the …
FIG. 9 is a graph showing the analysis results of the time-dependent dielectric breakdown reliability of the GaN transistor according to Embodiment 2 of the …
high bandgap blocking layer (Al2O3) thickness | 3–20 nm | Al₂O₃ |
charge trapping layer (HfON) thickness | 3–20 nm | HfON |
AlGaN barrier layer thickness | 10–100 nm | AlGaN |
GaN channel layer thickness | 1–20 µm | GaN |
SiN passivation layer thickness | 10–100 nm | SiN |
La doping amount in La-doped HZO layer | 0.1–2 mol% | La:HfxZr₁-xO₂ |
Hf fraction x in HfxZr1-xO2 (HZO) | 0.3–0.9 dimensionless | HfxZr₁-xO₂ (doped) |
Temperature | ≥ 600 °C | — |
Thickness | 5–15 nm | — |
Thickness | 5–10 nm | — |
Thickness | 0.5–3 nm | — |
Thickness | 0.5–2 nm | — |
Thickness | 3–15 nm | — |
Thickness | 5–13 nm | — |
Thickness | 10–200 nm | — |
Thickness | 50–150 nm | — |
Thickness | 80–120 nm | — |
Thickness | 1–15 µm | — |
Thickness | 1–10 µm | — |
Thickness | 2–5 µm | — |
Thickness | 15–75 nm | — |
Thickness | 15–50 nm | — |
Thickness | 20–75 nm | — |
Thickness | 40–60 nm | — |
doped HZO layer
HfxZr₁-xO₂ (doped)
La-doped HZO layer
La:HfxZr₁-xO₂
SiN passivation layer
SiN
Al₂O₃ high bandgap blocking layer
Al₂O₃
HfON charge trapping layer
HfON
AlN nucleation layer
AlN
FIG. 3 is a graph showing the relationship between voltage and current of the ferroelectric capacitor structures of Embodiment 1 and Comparative embodiments 1 …
FIG. 5 is a graph showing the relationship between polarization and hard breakdown voltage of the ferroelectric capacitor structures of Embodiment 1 and …
FIG. 7B is a schematic cross-sectional view of a part of a composite dielectric layer in the GaN transistor according to Embodiment 2 of the present invention.
FIG. 8B is a graph showing the relationship between voltage and current of the GaN transistor according to 5 Comparative embodiment 4 of the present invention.
FIG. 8B is a graph showing the relationship between voltage and current of the GaN transistor according to 5 Comparative embodiment 4 of the present invention.
FIG. 9 is a graph showing the analysis results of the time-dependent dielectric breakdown reliability of the GaN transistor according to Embodiment 2 of the …
FIG. 9 is a graph showing the analysis results of the time-dependent dielectric breakdown reliability of the GaN transistor according to Embodiment 2 of the …
high bandgap blocking layer (Al2O3) thickness | 3–20 nm | Al₂O₃ |
charge trapping layer (HfON) thickness | 3–20 nm | HfON |
AlGaN barrier layer thickness | 10–100 nm | AlGaN |
GaN channel layer thickness | 1–20 µm | GaN |
SiN passivation layer thickness | 10–100 nm | SiN |
La doping amount in La-doped HZO layer | 0.1–2 mol% | La:HfxZr₁-xO₂ |
Hf fraction x in HfxZr1-xO2 (HZO) | 0.3–0.9 dimensionless | HfxZr₁-xO₂ (doped) |
Temperature | ≥ 600 °C | — |
Thickness | 5–15 nm | — |
Thickness | 5–10 nm | — |
Thickness | 0.5–3 nm | — |
Thickness | 0.5–2 nm | — |
Thickness | 3–15 nm | — |
Thickness | 5–13 nm | — |
Thickness | 10–200 nm | — |
Thickness | 50–150 nm | — |
Thickness | 80–120 nm | — |
Thickness | 1–15 µm | — |
Thickness | 1–10 µm | — |
Thickness | 2–5 µm | — |
Thickness | 15–75 nm | — |
Thickness | 15–50 nm | — |
Thickness | 20–75 nm | — |
Thickness | 40–60 nm | — |
doped HZO layer
HfxZr₁-xO₂ (doped)
La-doped HZO layer
La:HfxZr₁-xO₂
SiN passivation layer
SiN
Al₂O₃ high bandgap blocking layer
Al₂O₃
HfON charge trapping layer
HfON
AlN nucleation layer
AlN
FIG. 3 is a graph showing the relationship between voltage and current of the ferroelectric capacitor structures of Embodiment 1 and Comparative embodiments 1 …
FIG. 5 is a graph showing the relationship between polarization and hard breakdown voltage of the ferroelectric capacitor structures of Embodiment 1 and …
FIG. 7B is a schematic cross-sectional view of a part of a composite dielectric layer in the GaN transistor according to Embodiment 2 of the present invention.
FIG. 8B is a graph showing the relationship between voltage and current of the GaN transistor according to 5 Comparative embodiment 4 of the present invention.
FIG. 8B is a graph showing the relationship between voltage and current of the GaN transistor according to 5 Comparative embodiment 4 of the present invention.
FIG. 9 is a graph showing the analysis results of the time-dependent dielectric breakdown reliability of the GaN transistor according to Embodiment 2 of the …
FIG. 9 is a graph showing the analysis results of the time-dependent dielectric breakdown reliability of the GaN transistor according to Embodiment 2 of the …
high bandgap blocking layer (Al2O3) thickness | 3–20 nm | Al₂O₃ |
charge trapping layer (HfON) thickness | 3–20 nm | HfON |
AlGaN barrier layer thickness | 10–100 nm | AlGaN |
GaN channel layer thickness | 1–20 µm | GaN |
SiN passivation layer thickness | 10–100 nm | SiN |
La doping amount in La-doped HZO layer | 0.1–2 mol% | La:HfxZr₁-xO₂ |
Hf fraction x in HfxZr1-xO2 (HZO) | 0.3–0.9 dimensionless | HfxZr₁-xO₂ (doped) |
Temperature | ≥ 600 °C | — |
Thickness | 5–15 nm | — |
Thickness | 5–10 nm | — |
Thickness | 0.5–3 nm | — |
Thickness | 0.5–2 nm | — |
Thickness | 3–15 nm | — |
Thickness | 5–13 nm | — |
Thickness | 10–200 nm | — |
Thickness | 50–150 nm | — |
Thickness | 80–120 nm | — |
Thickness | 1–15 µm | — |
Thickness | 1–10 µm | — |
Thickness | 2–5 µm | — |
Thickness | 15–75 nm | — |
Thickness | 15–50 nm | — |
Thickness | 20–75 nm | — |
Thickness | 40–60 nm | — |