Patent
US 9,923,087SELF-ALIGNED STRUCTURES AND METHODS FOR ASYMMETRIC GAN TRANSISTORS & ENHANCEMENT MODE OPERATION
Sansaptak Dasgupta, Han Wui Then, Marko Radosavljevic, Niloy Mukherjee et al.
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 9,923,087Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 is a flow diagram illustrating a method of fabricating an asymmetric I II -N HEMT, in accordance with embodiments. [008]
Figures 2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H, 2 I, and 2J illustrates a cross- section of an asymmetric I II -N HEMT as it evolves as a result of the performance of operations in the method depicted in
Figure 3 illustrates an isometric view of a mobile computing device platform and schematic view of a microelectronic device employed by the mobile platform, in accordance with one embodiment of the present invention; and
Figure 4 illustrates a functional block diagram of computing device in accordance with one embodiment of the invention. 42P₄₄₇₆₀DC
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A high electron mobility field effect transistor (HEMT), comprising: a group I II -N semiconductor channel layer disposed over a substrate; a semiconductor barrier layer disposed on the group I II -N semiconductor channel layer; a gate stack having a portion disposed on a portion of the semiconductor barrier layer to define a channel region in the group I II -N semiconductor channel layer beneath the portion of the gate stack on the portion of the semiconductor barrier layer, wherein the portion of the gate stack disposed on the portion of the semiconductor barrier layer is in a recess of the semiconductor barrier la y er, the recess having an upper portion with a first width, and the recess having a lower portion with a second width less than the first width, wherein a region of the semiconductor barrier layer beneath the portion of the gate stack is fluorine doped; a source region on the group I II -N semiconductor channel layer at a first side of the gate stack, the source region laterally adjacent to a first end of the semiconductor barrier layer; and a drain region in contact with the group I II -N semiconductor channel layer on a second side of the gate stack opposite the source region, the drain region laterally adjacent to a second end of the semiconductor barrier layer opposite the first end of the semiconductor barrier layer, wherein the channel region is spaced apart from the source region by a first length and is spaced apart from the drain region by a second length, and wherein the first length is less than the second length. Currently amended
The HEMT of claim 1, wherein the source region and the drain region are in recesses in the group I II -N semiconductor channel layer. Original
The HEMT of claim 1, wherein the gate stack comprises a gate dielectric layer including a metal oxide. Original
The HEMT of claim 1, wherein the source and drain regions each comprise InGaN. Original
The HEMT of claim 1, wherein the group I II -N semiconductor channel layer is GaN. Original
The HEMT of claim 1, wherein the stack comprises a gate dielectric layer, the gate dielectric layer comprising: a base dielectric layer of a first composition disposed directly on the region of the semiconductor barrier layer beneath the portion of the gate stack on the portion of the semiconductor barrier layer that is fluorine doped; and a top dielectric layer of a second composition disposed directly on the base dielectric layer. Original
The HEMT of claim 1, wherein the region of the semiconductor barrier layer beneath the portion of the gate stack on the portion of the semiconductor barrier layer is fluorine doped to between 1 e17cm⁻³ and le1 8cm 3. Original
Canceled
A high electron mobility field effect transistor (HEMT), comprising: a group I II -N semiconductor channel layer disposed over a substrate; a semiconductor barrier layer disposed on the group I II -N semiconductor channel layer; a gate stack having a portion disposed in a recess of the semiconductor barrier layer to define a channel region in the group I II -N semiconductor channel layer beneath the portion of the gate stack in the recess, the recess having an upper portion with a first width, and the recess having a lower portion with a second width less than the first width; a source region on the group I II -N semiconductor channel layer at a first side of the gate stack, the source region laterally adjacent to a first end of the semiconductor barrier layer; and a drain region in contact with the group I II -N semiconductor channel layer on a second side of the gate stack opposite the source region, the drain region laterally adjacent to a second end of the semiconductor barrier layer opposite the first end of the semiconductor barrier layer, wherein the channel region is spaced apart from the source wherein the first length is less than the second length. Currently amended
The HEMT of claim 12, wherein the source region and the drain region are in recesses in the group I II -N semiconductor channel layer. Original
The HEMT of claim 12, wherein the gate stack comprises a gate dielectric layer including a metal oxide. Original
The HEMT of claim 12, wherein the source and drain regions each comprise InGaN. Original
The HEMT of claim 12, wherein the group I II -N semiconductor channel layer is GaN. Original
The HEMT of claim 12, wherein the stack comprises a gate dielectric layer, the gate dielectric layer comprising a base dielectric layer of a first composition disposed directly on the recessed region of the semiconductor barrier layer beneath the portion of the gate stack on the portion of the semiconductor barrier layer. Original
Layer stacks claimed or described, ordered top of device to substrate.
asymmetric III-N HEMT with fluorine-doped barrier (claim 1)
Materials described outside the worked examples.
group III-N semiconductor channel layer (GaN)
GaN
semiconductor barrier layer
Measurements and analyses referenced in the patent, with their drawing references.
Figures 2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H, 2 I, and 2J illustrates a cross- section of an asymmetric I II -N HEMT as it evolves as a result of the performance of operations in the method depicted in
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 10–200 nm | — |
Thickness | 20–100 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,923,087Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 is a flow diagram illustrating a method of fabricating an asymmetric I II -N HEMT, in accordance with embodiments. [008]
Figures 2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H, 2 I, and 2J illustrates a cross- section of an asymmetric I II -N HEMT as it evolves as a result of the performance of operations in the method depicted in
Figure 3 illustrates an isometric view of a mobile computing device platform and schematic view of a microelectronic device employed by the mobile platform, in accordance with one embodiment of the present invention; and
Figure 4 illustrates a functional block diagram of computing device in accordance with one embodiment of the invention. 42P₄₄₇₆₀DC
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A high electron mobility field effect transistor (HEMT), comprising: a group I II -N semiconductor channel layer disposed over a substrate; a semiconductor barrier layer disposed on the group I II -N semiconductor channel layer; a gate stack having a portion disposed on a portion of the semiconductor barrier layer to define a channel region in the group I II -N semiconductor channel layer beneath the portion of the gate stack on the portion of the semiconductor barrier layer, wherein the portion of the gate stack disposed on the portion of the semiconductor barrier layer is in a recess of the semiconductor barrier la y er, the recess having an upper portion with a first width, and the recess having a lower portion with a second width less than the first width, wherein a region of the semiconductor barrier layer beneath the portion of the gate stack is fluorine doped; a source region on the group I II -N semiconductor channel layer at a first side of the gate stack, the source region laterally adjacent to a first end of the semiconductor barrier layer; and a drain region in contact with the group I II -N semiconductor channel layer on a second side of the gate stack opposite the source region, the drain region laterally adjacent to a second end of the semiconductor barrier layer opposite the first end of the semiconductor barrier layer, wherein the channel region is spaced apart from the source region by a first length and is spaced apart from the drain region by a second length, and wherein the first length is less than the second length. Currently amended
The HEMT of claim 1, wherein the source region and the drain region are in recesses in the group I II -N semiconductor channel layer. Original
The HEMT of claim 1, wherein the gate stack comprises a gate dielectric layer including a metal oxide. Original
The HEMT of claim 1, wherein the source and drain regions each comprise InGaN. Original
The HEMT of claim 1, wherein the group I II -N semiconductor channel layer is GaN. Original
The HEMT of claim 1, wherein the stack comprises a gate dielectric layer, the gate dielectric layer comprising: a base dielectric layer of a first composition disposed directly on the region of the semiconductor barrier layer beneath the portion of the gate stack on the portion of the semiconductor barrier layer that is fluorine doped; and a top dielectric layer of a second composition disposed directly on the base dielectric layer. Original
The HEMT of claim 1, wherein the region of the semiconductor barrier layer beneath the portion of the gate stack on the portion of the semiconductor barrier layer is fluorine doped to between 1 e17cm⁻³ and le1 8cm 3. Original
Canceled
A high electron mobility field effect transistor (HEMT), comprising: a group I II -N semiconductor channel layer disposed over a substrate; a semiconductor barrier layer disposed on the group I II -N semiconductor channel layer; a gate stack having a portion disposed in a recess of the semiconductor barrier layer to define a channel region in the group I II -N semiconductor channel layer beneath the portion of the gate stack in the recess, the recess having an upper portion with a first width, and the recess having a lower portion with a second width less than the first width; a source region on the group I II -N semiconductor channel layer at a first side of the gate stack, the source region laterally adjacent to a first end of the semiconductor barrier layer; and a drain region in contact with the group I II -N semiconductor channel layer on a second side of the gate stack opposite the source region, the drain region laterally adjacent to a second end of the semiconductor barrier layer opposite the first end of the semiconductor barrier layer, wherein the channel region is spaced apart from the source wherein the first length is less than the second length. Currently amended
The HEMT of claim 12, wherein the source region and the drain region are in recesses in the group I II -N semiconductor channel layer. Original
The HEMT of claim 12, wherein the gate stack comprises a gate dielectric layer including a metal oxide. Original
The HEMT of claim 12, wherein the source and drain regions each comprise InGaN. Original
The HEMT of claim 12, wherein the group I II -N semiconductor channel layer is GaN. Original
The HEMT of claim 12, wherein the stack comprises a gate dielectric layer, the gate dielectric layer comprising a base dielectric layer of a first composition disposed directly on the recessed region of the semiconductor barrier layer beneath the portion of the gate stack on the portion of the semiconductor barrier layer. Original
Layer stacks claimed or described, ordered top of device to substrate.
asymmetric III-N HEMT with fluorine-doped barrier (claim 1)
Materials described outside the worked examples.
group III-N semiconductor channel layer (GaN)
GaN
semiconductor barrier layer
Measurements and analyses referenced in the patent, with their drawing references.
Figures 2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H, 2 I, and 2J illustrates a cross- section of an asymmetric I II -N HEMT as it evolves as a result of the performance of operations in the method depicted in
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 10–200 nm | — |
Thickness | 20–100 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,923,087Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 is a flow diagram illustrating a method of fabricating an asymmetric I II -N HEMT, in accordance with embodiments. [008]
Figures 2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H, 2 I, and 2J illustrates a cross- section of an asymmetric I II -N HEMT as it evolves as a result of the performance of operations in the method depicted in
Figure 3 illustrates an isometric view of a mobile computing device platform and schematic view of a microelectronic device employed by the mobile platform, in accordance with one embodiment of the present invention; and
Figure 4 illustrates a functional block diagram of computing device in accordance with one embodiment of the invention. 42P₄₄₇₆₀DC
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A high electron mobility field effect transistor (HEMT), comprising: a group I II -N semiconductor channel layer disposed over a substrate; a semiconductor barrier layer disposed on the group I II -N semiconductor channel layer; a gate stack having a portion disposed on a portion of the semiconductor barrier layer to define a channel region in the group I II -N semiconductor channel layer beneath the portion of the gate stack on the portion of the semiconductor barrier layer, wherein the portion of the gate stack disposed on the portion of the semiconductor barrier layer is in a recess of the semiconductor barrier la y er, the recess having an upper portion with a first width, and the recess having a lower portion with a second width less than the first width, wherein a region of the semiconductor barrier layer beneath the portion of the gate stack is fluorine doped; a source region on the group I II -N semiconductor channel layer at a first side of the gate stack, the source region laterally adjacent to a first end of the semiconductor barrier layer; and a drain region in contact with the group I II -N semiconductor channel layer on a second side of the gate stack opposite the source region, the drain region laterally adjacent to a second end of the semiconductor barrier layer opposite the first end of the semiconductor barrier layer, wherein the channel region is spaced apart from the source region by a first length and is spaced apart from the drain region by a second length, and wherein the first length is less than the second length. Currently amended
The HEMT of claim 1, wherein the source region and the drain region are in recesses in the group I II -N semiconductor channel layer. Original
The HEMT of claim 1, wherein the gate stack comprises a gate dielectric layer including a metal oxide. Original
The HEMT of claim 1, wherein the source and drain regions each comprise InGaN. Original
The HEMT of claim 1, wherein the group I II -N semiconductor channel layer is GaN. Original
The HEMT of claim 1, wherein the stack comprises a gate dielectric layer, the gate dielectric layer comprising: a base dielectric layer of a first composition disposed directly on the region of the semiconductor barrier layer beneath the portion of the gate stack on the portion of the semiconductor barrier layer that is fluorine doped; and a top dielectric layer of a second composition disposed directly on the base dielectric layer. Original
The HEMT of claim 1, wherein the region of the semiconductor barrier layer beneath the portion of the gate stack on the portion of the semiconductor barrier layer is fluorine doped to between 1 e17cm⁻³ and le1 8cm 3. Original
Canceled
A high electron mobility field effect transistor (HEMT), comprising: a group I II -N semiconductor channel layer disposed over a substrate; a semiconductor barrier layer disposed on the group I II -N semiconductor channel layer; a gate stack having a portion disposed in a recess of the semiconductor barrier layer to define a channel region in the group I II -N semiconductor channel layer beneath the portion of the gate stack in the recess, the recess having an upper portion with a first width, and the recess having a lower portion with a second width less than the first width; a source region on the group I II -N semiconductor channel layer at a first side of the gate stack, the source region laterally adjacent to a first end of the semiconductor barrier layer; and a drain region in contact with the group I II -N semiconductor channel layer on a second side of the gate stack opposite the source region, the drain region laterally adjacent to a second end of the semiconductor barrier layer opposite the first end of the semiconductor barrier layer, wherein the channel region is spaced apart from the source wherein the first length is less than the second length. Currently amended
The HEMT of claim 12, wherein the source region and the drain region are in recesses in the group I II -N semiconductor channel layer. Original
The HEMT of claim 12, wherein the gate stack comprises a gate dielectric layer including a metal oxide. Original
The HEMT of claim 12, wherein the source and drain regions each comprise InGaN. Original
The HEMT of claim 12, wherein the group I II -N semiconductor channel layer is GaN. Original
The HEMT of claim 12, wherein the stack comprises a gate dielectric layer, the gate dielectric layer comprising a base dielectric layer of a first composition disposed directly on the recessed region of the semiconductor barrier layer beneath the portion of the gate stack on the portion of the semiconductor barrier layer. Original
Layer stacks claimed or described, ordered top of device to substrate.
asymmetric III-N HEMT with fluorine-doped barrier (claim 1)
Materials described outside the worked examples.
group III-N semiconductor channel layer (GaN)
GaN
semiconductor barrier layer
Measurements and analyses referenced in the patent, with their drawing references.
Figures 2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H, 2 I, and 2J illustrates a cross- section of an asymmetric I II -N HEMT as it evolves as a result of the performance of operations in the method depicted in
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 10–200 nm | — |
Thickness | 20–100 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,923,087Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 is a flow diagram illustrating a method of fabricating an asymmetric I II -N HEMT, in accordance with embodiments. [008]
Figures 2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H, 2 I, and 2J illustrates a cross- section of an asymmetric I II -N HEMT as it evolves as a result of the performance of operations in the method depicted in
Figure 3 illustrates an isometric view of a mobile computing device platform and schematic view of a microelectronic device employed by the mobile platform, in accordance with one embodiment of the present invention; and
Figure 4 illustrates a functional block diagram of computing device in accordance with one embodiment of the invention. 42P₄₄₇₆₀DC
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A high electron mobility field effect transistor (HEMT), comprising: a group I II -N semiconductor channel layer disposed over a substrate; a semiconductor barrier layer disposed on the group I II -N semiconductor channel layer; a gate stack having a portion disposed on a portion of the semiconductor barrier layer to define a channel region in the group I II -N semiconductor channel layer beneath the portion of the gate stack on the portion of the semiconductor barrier layer, wherein the portion of the gate stack disposed on the portion of the semiconductor barrier layer is in a recess of the semiconductor barrier la y er, the recess having an upper portion with a first width, and the recess having a lower portion with a second width less than the first width, wherein a region of the semiconductor barrier layer beneath the portion of the gate stack is fluorine doped; a source region on the group I II -N semiconductor channel layer at a first side of the gate stack, the source region laterally adjacent to a first end of the semiconductor barrier layer; and a drain region in contact with the group I II -N semiconductor channel layer on a second side of the gate stack opposite the source region, the drain region laterally adjacent to a second end of the semiconductor barrier layer opposite the first end of the semiconductor barrier layer, wherein the channel region is spaced apart from the source region by a first length and is spaced apart from the drain region by a second length, and wherein the first length is less than the second length. Currently amended
The HEMT of claim 1, wherein the source region and the drain region are in recesses in the group I II -N semiconductor channel layer. Original
The HEMT of claim 1, wherein the gate stack comprises a gate dielectric layer including a metal oxide. Original
The HEMT of claim 1, wherein the source and drain regions each comprise InGaN. Original
The HEMT of claim 1, wherein the group I II -N semiconductor channel layer is GaN. Original
The HEMT of claim 1, wherein the stack comprises a gate dielectric layer, the gate dielectric layer comprising: a base dielectric layer of a first composition disposed directly on the region of the semiconductor barrier layer beneath the portion of the gate stack on the portion of the semiconductor barrier layer that is fluorine doped; and a top dielectric layer of a second composition disposed directly on the base dielectric layer. Original
The HEMT of claim 1, wherein the region of the semiconductor barrier layer beneath the portion of the gate stack on the portion of the semiconductor barrier layer is fluorine doped to between 1 e17cm⁻³ and le1 8cm 3. Original
Canceled
A high electron mobility field effect transistor (HEMT), comprising: a group I II -N semiconductor channel layer disposed over a substrate; a semiconductor barrier layer disposed on the group I II -N semiconductor channel layer; a gate stack having a portion disposed in a recess of the semiconductor barrier layer to define a channel region in the group I II -N semiconductor channel layer beneath the portion of the gate stack in the recess, the recess having an upper portion with a first width, and the recess having a lower portion with a second width less than the first width; a source region on the group I II -N semiconductor channel layer at a first side of the gate stack, the source region laterally adjacent to a first end of the semiconductor barrier layer; and a drain region in contact with the group I II -N semiconductor channel layer on a second side of the gate stack opposite the source region, the drain region laterally adjacent to a second end of the semiconductor barrier layer opposite the first end of the semiconductor barrier layer, wherein the channel region is spaced apart from the source wherein the first length is less than the second length. Currently amended
The HEMT of claim 12, wherein the source region and the drain region are in recesses in the group I II -N semiconductor channel layer. Original
The HEMT of claim 12, wherein the gate stack comprises a gate dielectric layer including a metal oxide. Original
The HEMT of claim 12, wherein the source and drain regions each comprise InGaN. Original
The HEMT of claim 12, wherein the group I II -N semiconductor channel layer is GaN. Original
The HEMT of claim 12, wherein the stack comprises a gate dielectric layer, the gate dielectric layer comprising a base dielectric layer of a first composition disposed directly on the recessed region of the semiconductor barrier layer beneath the portion of the gate stack on the portion of the semiconductor barrier layer. Original
Layer stacks claimed or described, ordered top of device to substrate.
asymmetric III-N HEMT with fluorine-doped barrier (claim 1)
Materials described outside the worked examples.
group III-N semiconductor channel layer (GaN)
GaN
semiconductor barrier layer
Measurements and analyses referenced in the patent, with their drawing references.
Figures 2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H, 2 I, and 2J illustrates a cross- section of an asymmetric I II -N HEMT as it evolves as a result of the performance of operations in the method depicted in
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 10–200 nm | — |
Thickness | 20–100 nm |
Related documents with shared materials, methods, properties, or citations.
asymmetric III-N HEMT with recessed gate stack (claim 12)
fluorine-doped semiconductor barrier layer region
gate dielectric (metal oxide)
InGaN
AlGaN
AlzGa(1-z)N
AlInN
AlwIn(1-w)N
AlN or quaternary AlInGaN
substrate (silicon, SiC, sapphire, etc.)
| — |
Thickness | 2–20 nm | — |
Thickness | 80–100 nm | — |
Thickness | 2–3 nm | — |
Thickness | 3–5 nm | — |
Voltage | 7–10 V | — |
Thickness | ≤ 10 nm | — |
Voltage | ≥ 10 V | — |
Voltage | ≥ 20 V | — |
asymmetric III-N HEMT with recessed gate stack (claim 12)
fluorine-doped semiconductor barrier layer region
gate dielectric (metal oxide)
InGaN
AlGaN
AlzGa(1-z)N
AlInN
AlwIn(1-w)N
AlN or quaternary AlInGaN
substrate (silicon, SiC, sapphire, etc.)
| — |
Thickness | 2–20 nm | — |
Thickness | 80–100 nm | — |
Thickness | 2–3 nm | — |
Thickness | 3–5 nm | — |
Voltage | 7–10 V | — |
Thickness | ≤ 10 nm | — |
Voltage | ≥ 10 V | — |
Voltage | ≥ 20 V | — |
asymmetric III-N HEMT with recessed gate stack (claim 12)
fluorine-doped semiconductor barrier layer region
gate dielectric (metal oxide)
InGaN
AlGaN
AlzGa(1-z)N
AlInN
AlwIn(1-w)N
AlN or quaternary AlInGaN
substrate (silicon, SiC, sapphire, etc.)
| — |
Thickness | 2–20 nm | — |
Thickness | 80–100 nm | — |
Thickness | 2–3 nm | — |
Thickness | 3–5 nm | — |
Voltage | 7–10 V | — |
Thickness | ≤ 10 nm | — |
Voltage | ≥ 10 V | — |
Voltage | ≥ 20 V | — |
asymmetric III-N HEMT with recessed gate stack (claim 12)
fluorine-doped semiconductor barrier layer region
gate dielectric (metal oxide)
InGaN
AlGaN
AlzGa(1-z)N
AlInN
AlwIn(1-w)N
AlN or quaternary AlInGaN
substrate (silicon, SiC, sapphire, etc.)
| — |
Thickness | 2–20 nm | — |
Thickness | 80–100 nm | — |
Thickness | 2–3 nm | — |
Thickness | 3–5 nm | — |
Voltage | 7–10 V | — |
Thickness | ≤ 10 nm | — |
Voltage | ≥ 10 V | — |
Voltage | ≥ 20 V | — |