Patent
US 10,840,264ULTRA-THIN-BODY GaN ON INSULATOR DEVICE
Lukas Czornomaz
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 10,840,264Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An ultra-thin-body GaN-on-Insulator device partially stacked on top of a complementary metal-oxide semiconductor (CMOS) device, comprising: a front-end-of-line (FEOL) processed CMOS platform terminated with an interlayer dielectric material; a first bonding layer atop the interlayer dielectric material, wherein the interlayer dielectric material is planarized before the first bonding layer is deposited; an ultra-thin-body GaN-based hetero-structure terminated with a second bonding layer, wherein the ultra-thin-body GaN-based hetero-structure is bonded with the second bonding layer, and partially stacked, on top of the first bonding layer of the CMOS platform, and wherein the ultra-thin-body GaN-based hetero-structure comprises a combined thickness of the following layers in the range of 1 5nm to 100 nm: the first bonding layer, the second bonding layer, a GaN channel layer, and a Al(Ga, I n)N barrier layer [[.]]; and at least one metal layer on the ultra-thin-body GaN-on-Insulator device bringing the CMOS device in electrical contact with an element of the ultra-thin-body GaN-on-Insulator device, wherein the one or more bonding layers of the ultra-thin-body GaN-based hetero- structure permits at least one metal layer to be deposited on the GaN-on-Insulator device and the CMOS device, independently, without causing damage to the one or more bonding layers. Currently amended
The device according to claim 1, wherein the ultra-thin-body GaN-based hetero-structure is Ga-polar or N-polar. Previously presented
The device according to claim 1, wherein the CMOS platform is a silicon on insulator (SOI) device. Previously presented
The device according to claim 1, wherein the ultra-thin-body GaN-based hetero-structure comprises the Al(Ga, I n)N barrier layer atop the second bonding layer. Previously presented
Canceled
Canceled
12-20. Canceled
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
ultra-thin-body GaN-on-Insulator device on CMOS platform
Materials described outside the worked examples.
GaN channel layer
GaN
Al(Ga,In)N barrier layer
Al(Ga,In)N
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
combined thickness of first bonding layer, second bonding layer, GaN channel layer, and Al(Ga,In)N barrier layer | 15–100 | — |
passivation layer maximum thickness | ≤ 100 |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,840,264Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An ultra-thin-body GaN-on-Insulator device partially stacked on top of a complementary metal-oxide semiconductor (CMOS) device, comprising: a front-end-of-line (FEOL) processed CMOS platform terminated with an interlayer dielectric material; a first bonding layer atop the interlayer dielectric material, wherein the interlayer dielectric material is planarized before the first bonding layer is deposited; an ultra-thin-body GaN-based hetero-structure terminated with a second bonding layer, wherein the ultra-thin-body GaN-based hetero-structure is bonded with the second bonding layer, and partially stacked, on top of the first bonding layer of the CMOS platform, and wherein the ultra-thin-body GaN-based hetero-structure comprises a combined thickness of the following layers in the range of 1 5nm to 100 nm: the first bonding layer, the second bonding layer, a GaN channel layer, and a Al(Ga, I n)N barrier layer [[.]]; and at least one metal layer on the ultra-thin-body GaN-on-Insulator device bringing the CMOS device in electrical contact with an element of the ultra-thin-body GaN-on-Insulator device, wherein the one or more bonding layers of the ultra-thin-body GaN-based hetero- structure permits at least one metal layer to be deposited on the GaN-on-Insulator device and the CMOS device, independently, without causing damage to the one or more bonding layers. Currently amended
The device according to claim 1, wherein the ultra-thin-body GaN-based hetero-structure is Ga-polar or N-polar. Previously presented
The device according to claim 1, wherein the CMOS platform is a silicon on insulator (SOI) device. Previously presented
The device according to claim 1, wherein the ultra-thin-body GaN-based hetero-structure comprises the Al(Ga, I n)N barrier layer atop the second bonding layer. Previously presented
Canceled
Canceled
12-20. Canceled
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
ultra-thin-body GaN-on-Insulator device on CMOS platform
Materials described outside the worked examples.
GaN channel layer
GaN
Al(Ga,In)N barrier layer
Al(Ga,In)N
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
combined thickness of first bonding layer, second bonding layer, GaN channel layer, and Al(Ga,In)N barrier layer | 15–100 | — |
passivation layer maximum thickness | ≤ 100 |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,840,264Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An ultra-thin-body GaN-on-Insulator device partially stacked on top of a complementary metal-oxide semiconductor (CMOS) device, comprising: a front-end-of-line (FEOL) processed CMOS platform terminated with an interlayer dielectric material; a first bonding layer atop the interlayer dielectric material, wherein the interlayer dielectric material is planarized before the first bonding layer is deposited; an ultra-thin-body GaN-based hetero-structure terminated with a second bonding layer, wherein the ultra-thin-body GaN-based hetero-structure is bonded with the second bonding layer, and partially stacked, on top of the first bonding layer of the CMOS platform, and wherein the ultra-thin-body GaN-based hetero-structure comprises a combined thickness of the following layers in the range of 1 5nm to 100 nm: the first bonding layer, the second bonding layer, a GaN channel layer, and a Al(Ga, I n)N barrier layer [[.]]; and at least one metal layer on the ultra-thin-body GaN-on-Insulator device bringing the CMOS device in electrical contact with an element of the ultra-thin-body GaN-on-Insulator device, wherein the one or more bonding layers of the ultra-thin-body GaN-based hetero- structure permits at least one metal layer to be deposited on the GaN-on-Insulator device and the CMOS device, independently, without causing damage to the one or more bonding layers. Currently amended
The device according to claim 1, wherein the ultra-thin-body GaN-based hetero-structure is Ga-polar or N-polar. Previously presented
The device according to claim 1, wherein the CMOS platform is a silicon on insulator (SOI) device. Previously presented
The device according to claim 1, wherein the ultra-thin-body GaN-based hetero-structure comprises the Al(Ga, I n)N barrier layer atop the second bonding layer. Previously presented
Canceled
Canceled
12-20. Canceled
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
ultra-thin-body GaN-on-Insulator device on CMOS platform
Materials described outside the worked examples.
GaN channel layer
GaN
Al(Ga,In)N barrier layer
Al(Ga,In)N
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
combined thickness of first bonding layer, second bonding layer, GaN channel layer, and Al(Ga,In)N barrier layer | 15–100 | — |
passivation layer maximum thickness | ≤ 100 |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,840,264Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An ultra-thin-body GaN-on-Insulator device partially stacked on top of a complementary metal-oxide semiconductor (CMOS) device, comprising: a front-end-of-line (FEOL) processed CMOS platform terminated with an interlayer dielectric material; a first bonding layer atop the interlayer dielectric material, wherein the interlayer dielectric material is planarized before the first bonding layer is deposited; an ultra-thin-body GaN-based hetero-structure terminated with a second bonding layer, wherein the ultra-thin-body GaN-based hetero-structure is bonded with the second bonding layer, and partially stacked, on top of the first bonding layer of the CMOS platform, and wherein the ultra-thin-body GaN-based hetero-structure comprises a combined thickness of the following layers in the range of 1 5nm to 100 nm: the first bonding layer, the second bonding layer, a GaN channel layer, and a Al(Ga, I n)N barrier layer [[.]]; and at least one metal layer on the ultra-thin-body GaN-on-Insulator device bringing the CMOS device in electrical contact with an element of the ultra-thin-body GaN-on-Insulator device, wherein the one or more bonding layers of the ultra-thin-body GaN-based hetero- structure permits at least one metal layer to be deposited on the GaN-on-Insulator device and the CMOS device, independently, without causing damage to the one or more bonding layers. Currently amended
The device according to claim 1, wherein the ultra-thin-body GaN-based hetero-structure is Ga-polar or N-polar. Previously presented
The device according to claim 1, wherein the CMOS platform is a silicon on insulator (SOI) device. Previously presented
The device according to claim 1, wherein the ultra-thin-body GaN-based hetero-structure comprises the Al(Ga, I n)N barrier layer atop the second bonding layer. Previously presented
Canceled
Canceled
12-20. Canceled
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
ultra-thin-body GaN-on-Insulator device on CMOS platform
Materials described outside the worked examples.
GaN channel layer
GaN
Al(Ga,In)N barrier layer
Al(Ga,In)N
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
combined thickness of first bonding layer, second bonding layer, GaN channel layer, and Al(Ga,In)N barrier layer | 15–100 | — |
passivation layer maximum thickness | ≤ 100 |
Related documents with shared materials, methods, properties, or citations.
first bonding layer
second bonding layer
passivation layer
SiN passivation layer
SiN
AlGaN buffer layer
AlGaN
interlayer dielectric material
passivation layer preferred thickness range (preferred) | 10–20 | passivation layer |
passivation layer preferred thickness range (more preferred) | 20–50 | passivation layer |
passivation layer preferred thickness range (most preferred) | 50–100 | passivation layer |
combined thickness of first bonding layer, second bonding layer, Al(Ga,In)N barrier layer and GaN channel layer (preferred embodiment) | 15–30 | — |
GaN layer thickness sufficient to meet 48V breakdown voltage | 150 | GaN |
maximum vertical gate/channel separation | 50 | — |
Thickness | 5–100 nm | — |
Thickness | 10–100 nm | — |
Thickness | 10–20 nm | — |
Thickness | 20–50 nm | — |
Thickness | 50–100 nm | — |
Thickness | 15–100 nm | — |
Thickness | 15–30 nm | — |
first bonding layer
second bonding layer
passivation layer
SiN passivation layer
SiN
AlGaN buffer layer
AlGaN
interlayer dielectric material
passivation layer preferred thickness range (preferred) | 10–20 | passivation layer |
passivation layer preferred thickness range (more preferred) | 20–50 | passivation layer |
passivation layer preferred thickness range (most preferred) | 50–100 | passivation layer |
combined thickness of first bonding layer, second bonding layer, Al(Ga,In)N barrier layer and GaN channel layer (preferred embodiment) | 15–30 | — |
GaN layer thickness sufficient to meet 48V breakdown voltage | 150 | GaN |
maximum vertical gate/channel separation | 50 | — |
Thickness | 5–100 nm | — |
Thickness | 10–100 nm | — |
Thickness | 10–20 nm | — |
Thickness | 20–50 nm | — |
Thickness | 50–100 nm | — |
Thickness | 15–100 nm | — |
Thickness | 15–30 nm | — |
first bonding layer
second bonding layer
passivation layer
SiN passivation layer
SiN
AlGaN buffer layer
AlGaN
interlayer dielectric material
passivation layer preferred thickness range (preferred) | 10–20 | passivation layer |
passivation layer preferred thickness range (more preferred) | 20–50 | passivation layer |
passivation layer preferred thickness range (most preferred) | 50–100 | passivation layer |
combined thickness of first bonding layer, second bonding layer, Al(Ga,In)N barrier layer and GaN channel layer (preferred embodiment) | 15–30 | — |
GaN layer thickness sufficient to meet 48V breakdown voltage | 150 | GaN |
maximum vertical gate/channel separation | 50 | — |
Thickness | 5–100 nm | — |
Thickness | 10–100 nm | — |
Thickness | 10–20 nm | — |
Thickness | 20–50 nm | — |
Thickness | 50–100 nm | — |
Thickness | 15–100 nm | — |
Thickness | 15–30 nm | — |
first bonding layer
second bonding layer
passivation layer
SiN passivation layer
SiN
AlGaN buffer layer
AlGaN
interlayer dielectric material
passivation layer preferred thickness range (preferred) | 10–20 | passivation layer |
passivation layer preferred thickness range (more preferred) | 20–50 | passivation layer |
passivation layer preferred thickness range (most preferred) | 50–100 | passivation layer |
combined thickness of first bonding layer, second bonding layer, Al(Ga,In)N barrier layer and GaN channel layer (preferred embodiment) | 15–30 | — |
GaN layer thickness sufficient to meet 48V breakdown voltage | 150 | GaN |
maximum vertical gate/channel separation | 50 | — |
Thickness | 5–100 nm | — |
Thickness | 10–100 nm | — |
Thickness | 10–20 nm | — |
Thickness | 20–50 nm | — |
Thickness | 50–100 nm | — |
Thickness | 15–100 nm | — |
Thickness | 15–30 nm | — |