Patent
Atlas literature
Patent
US 11,749,779 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1A and 1B schematically represent, in a cross- section view, a device comprising a GaN/InGaN structure according to different particular embodiments of …
FIGS. 2A, 2B, 2C and 2D schematically represent differ- ent steps of the process for manufacturing the device com- prising a GaN/InGaN structure, according to …
FIGS. 3A, 3B and 3C schematically represent different steps of the process for manufacturing the device comprising a GaN/InGaN structure, according to another …
FIG. 4 schematically represents a step of electrochemi- cally anodising InGaN mesas in a particular embodiment of the invention. 5
FIG. 5 is a graph representing different phenomena (pre- breakdown, porosification and electropolishing) occurring during an anodisation step, as a function of …
FIG. 6A, the regrowth is lateral and a subsequent pixeli- sation step by etching is advantageously performed. It is also possible to passivate the flanks with a …
FIG. 7B. Annealing is then carried out, for example at 900° C. (
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A process comprising the following steps of: a) providing a device comprising: a GaN/InGaN structure comprising an electrically con-ductive doped GaN layer locally covered with InGaN mesas, the InGaN mesas comprising a doped InGaN layer and an undoped or weakly doped InGaN layer, B₂ an electrically insulating layer substantially covering the electrically conductive doped GaN layer between the mesas, b) electrically connecting the electrically conductive doped InGaN layer of the device and a counter-elec-trode to a voltage or current generator, c) dipping the device and the counter-electrode into an electrolyte solution, d) porosifying the doped InGaN layer of the mesas by applying a voltage or current between the electrically conductive doped GaN layer and the counter-electrode, e) forming an InGaN layer by epitaxy on the InGaN mesas, whereby a relaxed epitaxially grown InGaN layer is obtained, wherein the electrolyte solution does not contact the electrically conductive doped GaN layer between the mesas.
The process according to claim 1, wherein the undoped or weakly doped InGaN layer has a thickness ranging from 0.25 to 3 nm.
The process according to claim 1, wherein the electri-cally insulating layer is of SiO₂ or SiN.
The process according to claim 1, wherein the device provided in step a) is manufactured by forming the electri-cally insulating layer and then the InGaN mesas.
The process according to claim 1, wherein the device provided in step a) is manufactured by forming the InGaN mesas and then the electrically insulating layer.
The process according to claim 1, wherein the electri-cally conductive doped GaN layer covers a support of sapphire or silicon.
The process according to claim 1, wherein the mesas have a thickness of less than 100 nm.
The process according to claim 1, wherein the process comprises a step during which an implantation doping or metal-organic vapour phase epitaxy doping step is carried out on the InGaN mesas.
The process according to claim 1, wherein the InGaN mesas of the structure provided in step a) are obtained according to the following steps of: depositing a full-plate InGaN layer, locally performing an implantation doping or metal-or-ganic vapour phase epitaxy doping step in the full-plate InGaN layer so as to have doped and undoped zones, depositing an unintentionally doped or weakly doped full-plate InGaN layer onto the full-plate InGaN layer, etching the full-plate InGaN layer through the undoped or weakly doped full-plate InGaN layer so as to remove the undoped zones, whereby InGaN mesas comprising a doped InGaN layer and an undoped or weakly doped InGaN layer are locally formed.
The process according to claim 1, wherein the undoped or weakly doped InGaN layer has a concentration of less than 5*1017 at/cm3.
A process comprising the following steps of: a) providing a device comprising: a GaN/InGaN structure comprising an electrically con-ductive doped GaN layer locally covered with InGaN mesas, the InGaN mesas comprising a doped InGaN layer and an undoped or weakly doped InGaN layer having a thickness ranging from 0.25 to 3 nm, an electrically insulating layer covering the electrically conductive doped GaN layer between the mesas, b) electrically connecting the electrically conductive doped GaN layer of the device and a counter-electrode to a voltage or current generator, 5 c) dipping the device and the counter-electrode into an electrolyte solution, d) applying a voltage or current between the electrically conductive doped GaN layer and the second so as to porosify the doped InGaN layer of the mesas, e) forming an InGaN layer by epitaxy on the InGaN mesas, whereby a relaxed epitaxially grown InGaN layer is obtained.
A process comprising the following steps of: a) providing a device comprising: 15 a GaN/InGaN structure comprising an electrically con-ductive doped GaN layer locally covered with InGaN mesas, the InGaN mesas comprising a doped B₂ InGaN layer and an undoped or weakly doped InGaN layer, and wherein the InGaN mesas have a thickness of less than 100 nm, an electrically insulating layer covering the electrically conductive doped GaN layer between the mesas, b) electrically connecting the electrically conductive doped GaN layer of the device and a counter-electrode to a voltage or current generator, c) dipping the device and the counter-electrode into an electrolyte solution, d) applying a voltage or current between the electrically conductive doped GaN layer and the second so as to porosify the doped InGaN layer of the mesas, e) forming an InGaN layer by epitaxy on the InGaN mesas, whereby a relaxed epitaxially grown InGaN layer is obtained. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN/InGaN structure with InGaN mesas on doped GaN layer
Materials described outside the worked examples.
doped GaN layer (electrically conductive)
GaN
doped InGaN layer
InGaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 5 is a graph representing different phenomena (pre- breakdown, porosification and electropolishing) occurring during an anodisation step, as a function of …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
undoped or weakly doped InGaN layer thickness (claim 2/claim 13) | — | InGaN |
InGaN mesa total thickness (claim 7/claim 14) | — |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 5
Cited non-patent literature · 2
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,749,779 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1A and 1B schematically represent, in a cross- section view, a device comprising a GaN/InGaN structure according to different particular embodiments of …
FIGS. 2A, 2B, 2C and 2D schematically represent differ- ent steps of the process for manufacturing the device com- prising a GaN/InGaN structure, according to …
FIGS. 3A, 3B and 3C schematically represent different steps of the process for manufacturing the device comprising a GaN/InGaN structure, according to another …
FIG. 4 schematically represents a step of electrochemi- cally anodising InGaN mesas in a particular embodiment of the invention. 5
FIG. 5 is a graph representing different phenomena (pre- breakdown, porosification and electropolishing) occurring during an anodisation step, as a function of …
FIG. 6A, the regrowth is lateral and a subsequent pixeli- sation step by etching is advantageously performed. It is also possible to passivate the flanks with a …
FIG. 7B. Annealing is then carried out, for example at 900° C. (
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A process comprising the following steps of: a) providing a device comprising: a GaN/InGaN structure comprising an electrically con-ductive doped GaN layer locally covered with InGaN mesas, the InGaN mesas comprising a doped InGaN layer and an undoped or weakly doped InGaN layer, B₂ an electrically insulating layer substantially covering the electrically conductive doped GaN layer between the mesas, b) electrically connecting the electrically conductive doped InGaN layer of the device and a counter-elec-trode to a voltage or current generator, c) dipping the device and the counter-electrode into an electrolyte solution, d) porosifying the doped InGaN layer of the mesas by applying a voltage or current between the electrically conductive doped GaN layer and the counter-electrode, e) forming an InGaN layer by epitaxy on the InGaN mesas, whereby a relaxed epitaxially grown InGaN layer is obtained, wherein the electrolyte solution does not contact the electrically conductive doped GaN layer between the mesas.
The process according to claim 1, wherein the undoped or weakly doped InGaN layer has a thickness ranging from 0.25 to 3 nm.
The process according to claim 1, wherein the electri-cally insulating layer is of SiO₂ or SiN.
The process according to claim 1, wherein the device provided in step a) is manufactured by forming the electri-cally insulating layer and then the InGaN mesas.
The process according to claim 1, wherein the device provided in step a) is manufactured by forming the InGaN mesas and then the electrically insulating layer.
The process according to claim 1, wherein the electri-cally conductive doped GaN layer covers a support of sapphire or silicon.
The process according to claim 1, wherein the mesas have a thickness of less than 100 nm.
The process according to claim 1, wherein the process comprises a step during which an implantation doping or metal-organic vapour phase epitaxy doping step is carried out on the InGaN mesas.
The process according to claim 1, wherein the InGaN mesas of the structure provided in step a) are obtained according to the following steps of: depositing a full-plate InGaN layer, locally performing an implantation doping or metal-or-ganic vapour phase epitaxy doping step in the full-plate InGaN layer so as to have doped and undoped zones, depositing an unintentionally doped or weakly doped full-plate InGaN layer onto the full-plate InGaN layer, etching the full-plate InGaN layer through the undoped or weakly doped full-plate InGaN layer so as to remove the undoped zones, whereby InGaN mesas comprising a doped InGaN layer and an undoped or weakly doped InGaN layer are locally formed.
The process according to claim 1, wherein the undoped or weakly doped InGaN layer has a concentration of less than 5*1017 at/cm3.
A process comprising the following steps of: a) providing a device comprising: a GaN/InGaN structure comprising an electrically con-ductive doped GaN layer locally covered with InGaN mesas, the InGaN mesas comprising a doped InGaN layer and an undoped or weakly doped InGaN layer having a thickness ranging from 0.25 to 3 nm, an electrically insulating layer covering the electrically conductive doped GaN layer between the mesas, b) electrically connecting the electrically conductive doped GaN layer of the device and a counter-electrode to a voltage or current generator, 5 c) dipping the device and the counter-electrode into an electrolyte solution, d) applying a voltage or current between the electrically conductive doped GaN layer and the second so as to porosify the doped InGaN layer of the mesas, e) forming an InGaN layer by epitaxy on the InGaN mesas, whereby a relaxed epitaxially grown InGaN layer is obtained.
A process comprising the following steps of: a) providing a device comprising: 15 a GaN/InGaN structure comprising an electrically con-ductive doped GaN layer locally covered with InGaN mesas, the InGaN mesas comprising a doped B₂ InGaN layer and an undoped or weakly doped InGaN layer, and wherein the InGaN mesas have a thickness of less than 100 nm, an electrically insulating layer covering the electrically conductive doped GaN layer between the mesas, b) electrically connecting the electrically conductive doped GaN layer of the device and a counter-electrode to a voltage or current generator, c) dipping the device and the counter-electrode into an electrolyte solution, d) applying a voltage or current between the electrically conductive doped GaN layer and the second so as to porosify the doped InGaN layer of the mesas, e) forming an InGaN layer by epitaxy on the InGaN mesas, whereby a relaxed epitaxially grown InGaN layer is obtained. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN/InGaN structure with InGaN mesas on doped GaN layer
Materials described outside the worked examples.
doped GaN layer (electrically conductive)
GaN
doped InGaN layer
InGaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 5 is a graph representing different phenomena (pre- breakdown, porosification and electropolishing) occurring during an anodisation step, as a function of …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
undoped or weakly doped InGaN layer thickness (claim 2/claim 13) | — | InGaN |
InGaN mesa total thickness (claim 7/claim 14) | — |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 5
Cited non-patent literature · 2
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,749,779 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1A and 1B schematically represent, in a cross- section view, a device comprising a GaN/InGaN structure according to different particular embodiments of …
FIGS. 2A, 2B, 2C and 2D schematically represent differ- ent steps of the process for manufacturing the device com- prising a GaN/InGaN structure, according to …
FIGS. 3A, 3B and 3C schematically represent different steps of the process for manufacturing the device comprising a GaN/InGaN structure, according to another …
FIG. 4 schematically represents a step of electrochemi- cally anodising InGaN mesas in a particular embodiment of the invention. 5
FIG. 5 is a graph representing different phenomena (pre- breakdown, porosification and electropolishing) occurring during an anodisation step, as a function of …
FIG. 6A, the regrowth is lateral and a subsequent pixeli- sation step by etching is advantageously performed. It is also possible to passivate the flanks with a …
FIG. 7B. Annealing is then carried out, for example at 900° C. (
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A process comprising the following steps of: a) providing a device comprising: a GaN/InGaN structure comprising an electrically con-ductive doped GaN layer locally covered with InGaN mesas, the InGaN mesas comprising a doped InGaN layer and an undoped or weakly doped InGaN layer, B₂ an electrically insulating layer substantially covering the electrically conductive doped GaN layer between the mesas, b) electrically connecting the electrically conductive doped InGaN layer of the device and a counter-elec-trode to a voltage or current generator, c) dipping the device and the counter-electrode into an electrolyte solution, d) porosifying the doped InGaN layer of the mesas by applying a voltage or current between the electrically conductive doped GaN layer and the counter-electrode, e) forming an InGaN layer by epitaxy on the InGaN mesas, whereby a relaxed epitaxially grown InGaN layer is obtained, wherein the electrolyte solution does not contact the electrically conductive doped GaN layer between the mesas.
The process according to claim 1, wherein the undoped or weakly doped InGaN layer has a thickness ranging from 0.25 to 3 nm.
The process according to claim 1, wherein the electri-cally insulating layer is of SiO₂ or SiN.
The process according to claim 1, wherein the device provided in step a) is manufactured by forming the electri-cally insulating layer and then the InGaN mesas.
The process according to claim 1, wherein the device provided in step a) is manufactured by forming the InGaN mesas and then the electrically insulating layer.
The process according to claim 1, wherein the electri-cally conductive doped GaN layer covers a support of sapphire or silicon.
The process according to claim 1, wherein the mesas have a thickness of less than 100 nm.
The process according to claim 1, wherein the process comprises a step during which an implantation doping or metal-organic vapour phase epitaxy doping step is carried out on the InGaN mesas.
The process according to claim 1, wherein the InGaN mesas of the structure provided in step a) are obtained according to the following steps of: depositing a full-plate InGaN layer, locally performing an implantation doping or metal-or-ganic vapour phase epitaxy doping step in the full-plate InGaN layer so as to have doped and undoped zones, depositing an unintentionally doped or weakly doped full-plate InGaN layer onto the full-plate InGaN layer, etching the full-plate InGaN layer through the undoped or weakly doped full-plate InGaN layer so as to remove the undoped zones, whereby InGaN mesas comprising a doped InGaN layer and an undoped or weakly doped InGaN layer are locally formed.
The process according to claim 1, wherein the undoped or weakly doped InGaN layer has a concentration of less than 5*1017 at/cm3.
A process comprising the following steps of: a) providing a device comprising: a GaN/InGaN structure comprising an electrically con-ductive doped GaN layer locally covered with InGaN mesas, the InGaN mesas comprising a doped InGaN layer and an undoped or weakly doped InGaN layer having a thickness ranging from 0.25 to 3 nm, an electrically insulating layer covering the electrically conductive doped GaN layer between the mesas, b) electrically connecting the electrically conductive doped GaN layer of the device and a counter-electrode to a voltage or current generator, 5 c) dipping the device and the counter-electrode into an electrolyte solution, d) applying a voltage or current between the electrically conductive doped GaN layer and the second so as to porosify the doped InGaN layer of the mesas, e) forming an InGaN layer by epitaxy on the InGaN mesas, whereby a relaxed epitaxially grown InGaN layer is obtained.
A process comprising the following steps of: a) providing a device comprising: 15 a GaN/InGaN structure comprising an electrically con-ductive doped GaN layer locally covered with InGaN mesas, the InGaN mesas comprising a doped B₂ InGaN layer and an undoped or weakly doped InGaN layer, and wherein the InGaN mesas have a thickness of less than 100 nm, an electrically insulating layer covering the electrically conductive doped GaN layer between the mesas, b) electrically connecting the electrically conductive doped GaN layer of the device and a counter-electrode to a voltage or current generator, c) dipping the device and the counter-electrode into an electrolyte solution, d) applying a voltage or current between the electrically conductive doped GaN layer and the second so as to porosify the doped InGaN layer of the mesas, e) forming an InGaN layer by epitaxy on the InGaN mesas, whereby a relaxed epitaxially grown InGaN layer is obtained. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN/InGaN structure with InGaN mesas on doped GaN layer
Materials described outside the worked examples.
doped GaN layer (electrically conductive)
GaN
doped InGaN layer
InGaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 5 is a graph representing different phenomena (pre- breakdown, porosification and electropolishing) occurring during an anodisation step, as a function of …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
undoped or weakly doped InGaN layer thickness (claim 2/claim 13) | — | InGaN |
InGaN mesa total thickness (claim 7/claim 14) | — |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 5
Cited non-patent literature · 2
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,749,779 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1A and 1B schematically represent, in a cross- section view, a device comprising a GaN/InGaN structure according to different particular embodiments of …
FIGS. 2A, 2B, 2C and 2D schematically represent differ- ent steps of the process for manufacturing the device com- prising a GaN/InGaN structure, according to …
FIGS. 3A, 3B and 3C schematically represent different steps of the process for manufacturing the device comprising a GaN/InGaN structure, according to another …
FIG. 4 schematically represents a step of electrochemi- cally anodising InGaN mesas in a particular embodiment of the invention. 5
FIG. 5 is a graph representing different phenomena (pre- breakdown, porosification and electropolishing) occurring during an anodisation step, as a function of …
FIG. 6A, the regrowth is lateral and a subsequent pixeli- sation step by etching is advantageously performed. It is also possible to passivate the flanks with a …
FIG. 7B. Annealing is then carried out, for example at 900° C. (
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A process comprising the following steps of: a) providing a device comprising: a GaN/InGaN structure comprising an electrically con-ductive doped GaN layer locally covered with InGaN mesas, the InGaN mesas comprising a doped InGaN layer and an undoped or weakly doped InGaN layer, B₂ an electrically insulating layer substantially covering the electrically conductive doped GaN layer between the mesas, b) electrically connecting the electrically conductive doped InGaN layer of the device and a counter-elec-trode to a voltage or current generator, c) dipping the device and the counter-electrode into an electrolyte solution, d) porosifying the doped InGaN layer of the mesas by applying a voltage or current between the electrically conductive doped GaN layer and the counter-electrode, e) forming an InGaN layer by epitaxy on the InGaN mesas, whereby a relaxed epitaxially grown InGaN layer is obtained, wherein the electrolyte solution does not contact the electrically conductive doped GaN layer between the mesas.
The process according to claim 1, wherein the undoped or weakly doped InGaN layer has a thickness ranging from 0.25 to 3 nm.
The process according to claim 1, wherein the electri-cally insulating layer is of SiO₂ or SiN.
The process according to claim 1, wherein the device provided in step a) is manufactured by forming the electri-cally insulating layer and then the InGaN mesas.
The process according to claim 1, wherein the device provided in step a) is manufactured by forming the InGaN mesas and then the electrically insulating layer.
The process according to claim 1, wherein the electri-cally conductive doped GaN layer covers a support of sapphire or silicon.
The process according to claim 1, wherein the mesas have a thickness of less than 100 nm.
The process according to claim 1, wherein the process comprises a step during which an implantation doping or metal-organic vapour phase epitaxy doping step is carried out on the InGaN mesas.
The process according to claim 1, wherein the InGaN mesas of the structure provided in step a) are obtained according to the following steps of: depositing a full-plate InGaN layer, locally performing an implantation doping or metal-or-ganic vapour phase epitaxy doping step in the full-plate InGaN layer so as to have doped and undoped zones, depositing an unintentionally doped or weakly doped full-plate InGaN layer onto the full-plate InGaN layer, etching the full-plate InGaN layer through the undoped or weakly doped full-plate InGaN layer so as to remove the undoped zones, whereby InGaN mesas comprising a doped InGaN layer and an undoped or weakly doped InGaN layer are locally formed.
The process according to claim 1, wherein the undoped or weakly doped InGaN layer has a concentration of less than 5*1017 at/cm3.
A process comprising the following steps of: a) providing a device comprising: a GaN/InGaN structure comprising an electrically con-ductive doped GaN layer locally covered with InGaN mesas, the InGaN mesas comprising a doped InGaN layer and an undoped or weakly doped InGaN layer having a thickness ranging from 0.25 to 3 nm, an electrically insulating layer covering the electrically conductive doped GaN layer between the mesas, b) electrically connecting the electrically conductive doped GaN layer of the device and a counter-electrode to a voltage or current generator, 5 c) dipping the device and the counter-electrode into an electrolyte solution, d) applying a voltage or current between the electrically conductive doped GaN layer and the second so as to porosify the doped InGaN layer of the mesas, e) forming an InGaN layer by epitaxy on the InGaN mesas, whereby a relaxed epitaxially grown InGaN layer is obtained.
A process comprising the following steps of: a) providing a device comprising: 15 a GaN/InGaN structure comprising an electrically con-ductive doped GaN layer locally covered with InGaN mesas, the InGaN mesas comprising a doped B₂ InGaN layer and an undoped or weakly doped InGaN layer, and wherein the InGaN mesas have a thickness of less than 100 nm, an electrically insulating layer covering the electrically conductive doped GaN layer between the mesas, b) electrically connecting the electrically conductive doped GaN layer of the device and a counter-electrode to a voltage or current generator, c) dipping the device and the counter-electrode into an electrolyte solution, d) applying a voltage or current between the electrically conductive doped GaN layer and the second so as to porosify the doped InGaN layer of the mesas, e) forming an InGaN layer by epitaxy on the InGaN mesas, whereby a relaxed epitaxially grown InGaN layer is obtained. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN/InGaN structure with InGaN mesas on doped GaN layer
Materials described outside the worked examples.
doped GaN layer (electrically conductive)
GaN
doped InGaN layer
InGaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 5 is a graph representing different phenomena (pre- breakdown, porosification and electropolishing) occurring during an anodisation step, as a function of …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
undoped or weakly doped InGaN layer thickness (claim 2/claim 13) | — | InGaN |
InGaN mesa total thickness (claim 7/claim 14) | — |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 5
Cited non-patent literature · 2
Related documents with shared materials, methods, properties, or citations.
SiO₂
SiN
sapphire
Al₂O₃
silicon
Si
FIG. 6A, the regrowth is lateral and a subsequent pixeli- sation step by etching is advantageously performed. It is also possible to passivate the flanks with a …
FIG. 7B. Annealing is then carried out, for example at 900° C. (
FIG. 7B. Annealing is then carried out, for example at 900° C. (
dopant concentration in undoped or weakly doped InGaN layer (claim 12) | — | InGaN |
Thickness | 0.25–3 nm | — |
Thickness | ≤ 1 nm | — |
SiO₂
SiN
sapphire
Al₂O₃
silicon
Si
FIG. 6A, the regrowth is lateral and a subsequent pixeli- sation step by etching is advantageously performed. It is also possible to passivate the flanks with a …
FIG. 7B. Annealing is then carried out, for example at 900° C. (
FIG. 7B. Annealing is then carried out, for example at 900° C. (
dopant concentration in undoped or weakly doped InGaN layer (claim 12) | — | InGaN |
Thickness | 0.25–3 nm | — |
Thickness | ≤ 1 nm | — |
SiO₂
SiN
sapphire
Al₂O₃
silicon
Si
FIG. 6A, the regrowth is lateral and a subsequent pixeli- sation step by etching is advantageously performed. It is also possible to passivate the flanks with a …
FIG. 7B. Annealing is then carried out, for example at 900° C. (
FIG. 7B. Annealing is then carried out, for example at 900° C. (
dopant concentration in undoped or weakly doped InGaN layer (claim 12) | — | InGaN |
Thickness | 0.25–3 nm | — |
Thickness | ≤ 1 nm | — |
SiO₂
SiN
sapphire
Al₂O₃
silicon
Si
FIG. 6A, the regrowth is lateral and a subsequent pixeli- sation step by etching is advantageously performed. It is also possible to passivate the flanks with a …
FIG. 7B. Annealing is then carried out, for example at 900° C. (
FIG. 7B. Annealing is then carried out, for example at 900° C. (
dopant concentration in undoped or weakly doped InGaN layer (claim 12) | — | InGaN |
Thickness | 0.25–3 nm | — |
Thickness | ≤ 1 nm | — |
