The method of claim 1, further comprising, forming a source contact on the IlIl -N based nanowire; and forming a drain contact on the doped buffer layer opposite to the Ill-N based nanowire.

The method of claim 1, wherein epitaxially growing the I ll -N based nanowire comprises a selective growth of the I ll -N based nanowire followed by a pulsed growth of the Ill -N based nanowire.

A method for making a HEMT transistor array according to claim 1, further comprising: epitaxially growing a plurality of IlIl -N based nanowires through the growth mask from the doped buffer layer; forming a shell member surrounding a length of each nanowire of the plurality of IlIl -N based nanowires for forming a two-dimensional electron gas (2- DEG) at an interface between each I ll -N based nanowire and the shell member, forming the first dielectric layer surrounding a first portion of each shell member and over the doped buffer layer; forming the metal gate surrounding a second portion of each shell member and over the first dielectric layer; and forming the second dielectric layer surrounding a third portion of each shell member and over a portion of the metal gate.

The method of claim 6, further comprising, forming a source contact on the IlIl -N based post; and forming a drain contact having the doped buffer layer disposed there on.

The method of claim 6, wherein forming the I ll -N based post over the first portion of the doped buffer layer comprises, forming a IlIl -N based layer over the doped buffer layer; and top-down etching the IlIl -N based layer to form the Ill -N based post having a length and a cross-sectional shape.

A method for making a HEMT transistor array according to claim 6, further comprising: forming a plurality of Ill -N based posts over the doped buffer layer; wherein each post of the plurality of I ll -N based posts has a minor cross- sectional dimension of greater than about 250; forming a shell member surrounding a length of each post of the plurality of IlIl -N based posts for forming a two-dimensional electron gas (2-DEG) at an interface between each I ll -N based nanowire and the shell member, forming the first dielectric layer surrounding a first portion of each shell member over the doped buffer layer; forming a metal gate surrounding a second portion of each shell member and over the first dielectric layer; and forming a second dielectric layer surrounding a third portion of each shell member and over a portion of the metal gate.

The method of claim 1, further comprising, forming a source contact on the IlIl -N based nanowire; and forming a drain contact on the doped buffer layer opposite to the Ill-N based nanowire.

The method of claim 1, wherein epitaxially growing the I ll -N based nanowire comprises a selective growth of the I ll -N based nanowire followed by a pulsed growth of the Ill -N based nanowire.

A method for making a HEMT transistor array according to claim 1, further comprising: epitaxially growing a plurality of IlIl -N based nanowires through the growth mask from the doped buffer layer; forming a shell member surrounding a length of each nanowire of the plurality of IlIl -N based nanowires for forming a two-dimensional electron gas (2- DEG) at an interface between each I ll -N based nanowire and the shell member, forming the first dielectric layer surrounding a first portion of each shell member and over the doped buffer layer; forming the metal gate surrounding a second portion of each shell member and over the first dielectric layer; and forming the second dielectric layer surrounding a third portion of each shell member and over a portion of the metal gate.

The method of claim 6, further comprising, forming a source contact on the IlIl -N based post; and forming a drain contact having the doped buffer layer disposed there on.

The method of claim 6, wherein forming the I ll -N based post over the first portion of the doped buffer layer comprises, forming a IlIl -N based layer over the doped buffer layer; and top-down etching the IlIl -N based layer to form the Ill -N based post having a length and a cross-sectional shape.

A method for making a HEMT transistor array according to claim 6, further comprising: forming a plurality of Ill -N based posts over the doped buffer layer; wherein each post of the plurality of I ll -N based posts has a minor cross- sectional dimension of greater than about 250; forming a shell member surrounding a length of each post of the plurality of IlIl -N based posts for forming a two-dimensional electron gas (2-DEG) at an interface between each I ll -N based nanowire and the shell member, forming the first dielectric layer surrounding a first portion of each shell member over the doped buffer layer; forming a metal gate surrounding a second portion of each shell member and over the first dielectric layer; and forming a second dielectric layer surrounding a third portion of each shell member and over a portion of the metal gate.

The method of claim 1, further comprising, forming a source contact on the IlIl -N based nanowire; and forming a drain contact on the doped buffer layer opposite to the Ill-N based nanowire.

The method of claim 1, wherein epitaxially growing the I ll -N based nanowire comprises a selective growth of the I ll -N based nanowire followed by a pulsed growth of the Ill -N based nanowire.

A method for making a HEMT transistor array according to claim 1, further comprising: epitaxially growing a plurality of IlIl -N based nanowires through the growth mask from the doped buffer layer; forming a shell member surrounding a length of each nanowire of the plurality of IlIl -N based nanowires for forming a two-dimensional electron gas (2- DEG) at an interface between each I ll -N based nanowire and the shell member, forming the first dielectric layer surrounding a first portion of each shell member and over the doped buffer layer; forming the metal gate surrounding a second portion of each shell member and over the first dielectric layer; and forming the second dielectric layer surrounding a third portion of each shell member and over a portion of the metal gate.

The method of claim 6, further comprising, forming a source contact on the IlIl -N based post; and forming a drain contact having the doped buffer layer disposed there on.

The method of claim 6, wherein forming the I ll -N based post over the first portion of the doped buffer layer comprises, forming a IlIl -N based layer over the doped buffer layer; and top-down etching the IlIl -N based layer to form the Ill -N based post having a length and a cross-sectional shape.

A method for making a HEMT transistor array according to claim 6, further comprising: forming a plurality of Ill -N based posts over the doped buffer layer; wherein each post of the plurality of I ll -N based posts has a minor cross- sectional dimension of greater than about 250; forming a shell member surrounding a length of each post of the plurality of IlIl -N based posts for forming a two-dimensional electron gas (2-DEG) at an interface between each I ll -N based nanowire and the shell member, forming the first dielectric layer surrounding a first portion of each shell member over the doped buffer layer; forming a metal gate surrounding a second portion of each shell member and over the first dielectric layer; and forming a second dielectric layer surrounding a third portion of each shell member and over a portion of the metal gate.

The method of claim 1, further comprising, forming a source contact on the IlIl -N based nanowire; and forming a drain contact on the doped buffer layer opposite to the Ill-N based nanowire.

The method of claim 1, wherein epitaxially growing the I ll -N based nanowire comprises a selective growth of the I ll -N based nanowire followed by a pulsed growth of the Ill -N based nanowire.

A method for making a HEMT transistor array according to claim 1, further comprising: epitaxially growing a plurality of IlIl -N based nanowires through the growth mask from the doped buffer layer; forming a shell member surrounding a length of each nanowire of the plurality of IlIl -N based nanowires for forming a two-dimensional electron gas (2- DEG) at an interface between each I ll -N based nanowire and the shell member, forming the first dielectric layer surrounding a first portion of each shell member and over the doped buffer layer; forming the metal gate surrounding a second portion of each shell member and over the first dielectric layer; and forming the second dielectric layer surrounding a third portion of each shell member and over a portion of the metal gate.

The method of claim 6, further comprising, forming a source contact on the IlIl -N based post; and forming a drain contact having the doped buffer layer disposed there on.

The method of claim 6, wherein forming the I ll -N based post over the first portion of the doped buffer layer comprises, forming a IlIl -N based layer over the doped buffer layer; and top-down etching the IlIl -N based layer to form the Ill -N based post having a length and a cross-sectional shape.

A method for making a HEMT transistor array according to claim 6, further comprising: forming a plurality of Ill -N based posts over the doped buffer layer; wherein each post of the plurality of I ll -N based posts has a minor cross- sectional dimension of greater than about 250; forming a shell member surrounding a length of each post of the plurality of IlIl -N based posts for forming a two-dimensional electron gas (2-DEG) at an interface between each I ll -N based nanowire and the shell member, forming the first dielectric layer surrounding a first portion of each shell member over the doped buffer layer; forming a metal gate surrounding a second portion of each shell member and over the first dielectric layer; and forming a second dielectric layer surrounding a third portion of each shell member and over a portion of the metal gate.