Patent
US 9,219,137VERTICAL GALLIUM NITRIDE TRANSISTORS AND METHODS OF FABRICATING THE SAME
Motonobu TAKEYA
US
Copyright © 2026 Matter42. All rights reserved.
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Atlas literature
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US 9,219,137Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view illustrating a vertical gallium nitride transistor according to an exemplary embodiment of the present invention. 20 [0024]
FIGS. 2 to 9 are cross-sectional views illustrating a method of fabricating the vertical gallium nitride transistor according to the exemplary embodiment of
FIG. 3). In such a case, the GaN layer may be formed to a thickness of about 1 micrometer to about 2 micrometers. Referring to
FIG. 4, additional semiconductor layers 25a of the first conductivity 20 type may be grown on respective stripe patterns 23a. The additional semiconductor …
FIG. 5, current blocking layers 31 may be formed on the second semiconductor layer 29. The current blocking layers 31 may be formed by depositing a silicon …
FIG. 6, a support substrate 41 may be attached to the second semiconductor layer 29. The support substrate 41 may be formed by depositing a metal layer 35 …
FIG. 7, the growth substrate 21 may be removed from the semiconductor layers 25, 27, and 29 including the stripe patterns 25a. The growth substrate 21 10 may …
FIG. 8, source electrodes 43 may be formed on the top surface of the semiconductor structure 20. The source electrodes 43 may be formed to be electrically …
FIG. 9 are cross- sectional views illustrating a method of fabricating the vertical gallium nitride transistor shown in
FIG. 10 is a cross-sectional view illustrating an off-state of a vertical gallium nitride transistor according to an exemplary embodiment of the present …
FIG. 11 is a cross-sectional view illustrating an on-state of the vertical gallium nitride transistor according to the exemplary embodiment of
FIGS. 12 to 27 are cross-sectional views illustrating a method of fabricating the vertical gallium nitride transistor according to an exemplary embodiment of …
FIG. 13, a GaN layer heavily doped with N-type impurities may be 10 grown on the seed layer 102 to form a first semiconductor layer 120. The first semiconductor …
FIG. 14, a GaN layer lightly doped with N-type impurities may be grown on the first semiconductor layer 120 to form a first semiconductor layer 125. That is, the …
FIG. 15, the blocking layers 135 may be formed on the 31 upper GaN layer 125 to face respective ones of the seed patterns 102. Each of the blocking layers 135 …
FIG. 16, the second semiconductor layer 140 may be formed of an undoped GaN layer. The second semiconductor layers 140 may be formed to cover edges of the …
FIG. 17, the third semiconductor layer 150 may be formed of a P- type GaN layer on entire surfaces of the blocking layers 135 and the second semiconductor …
FIG. 18, the insulation layer 155 may be formed on the 15 third semiconductor layer 150, for example, the P-type GaN layer. [0087] Refe rr ing to
FIGS. 19 to 24A, the step of forming the source electrodes 166 and the gate electrodes 160 may include a step of forming a metal layer 160 on the insulation …
FIG. 20, a step of patterning the insulation layer 155 and the 20 P-type GaN layer 150 to form openings that expose portions of the second semiconductor layer …
FIG. 21, a step of forming the source electrodes 166 composed of a metal layer in the openings as illustrated in
FIG. 22, and a step of forming a passivation layer 175 that fills spaces between the source electrodes 166 and the 32 gate electrodes 160 and covers the source …
FIG. 23, 24A, and
FIG. 24B are cross-sectional views illustrating a method of fabricating a vertical gallium nitride according to an exemplary embodiment of the present …
FIG. 25, the second substrate 109 may be attached to a surface of the passivation layer 175 opposite to the first substrate 101. Referring to
FIG. 26, the first substrate 101 may be detached from the first semiconductor layers 120 and 125. The first substrate 101 may be detached using a laser lift-off 5 …
FIG. 27. The additional blocking layers 115 may be formed of the same material as the blocking layers 135. Further, the additional blocking layers 115 may be …
FIG. 28 is a cross-sectional view illustrating an off-state of a vertical gallium 10 nitride transistor according to an exemplary embodiment of the present …
FIG. 29 is a cross-sectional view illustrating an on-state of the vertical gallium nitride transistor according to the exemplary embodiment of
FIG. 30 is a cross-sectional view illustrating an off-state of a vertical gallium nitride transistor according to an exemplary embodiment of the present …
FIG. 31 is a cross-sectional view illustrating an on-state of the vertical gallium nitride transistor according to the exemplary embodiment of
FIGS. 32 to 46 are cross-sectional views illustrating a method of fabricating the vertical gallium nitride transistor according to an exemplary embodiment of …
FIG. 33, a GaN layer heavily doped with N- type impurities may be grown on the seed patterns 302 to form the first semiconductor layer 320. [00103] Refe rr ing …
FIG. 34, a GaN layer lightly doped with N-type impurities 5 may be grown on the first semiconductor layer 320 to form the first semiconductor layer 325. That is, …
FIG. 35, the blocking layers 335 may be formed on the upper GaN layer 325 to face respective ones of the seed patterns 302. Each of the blocking layers 335 may …
FIG. 36, an undoped GaN layer may be grown using the first semiconductor layer 325 as a seed layer to form the second semiconductor layers 340. The 20 second …
FIG. 37. The insulation layer 355 may be formed on the third semiconductor layer 350, as illustrated in
FIG. 38. [00107] The step of forming the source electrodes 366 and the gate electrodes 360 may include a step of forming a metal layer 360 on the insulation …
FIG. 39, a step of patterning the metal layer 360 to form the gate electrodes 360 as illustrated in
FIG. 41, a step of forming the source electrodes 366 composed of a metal layer in the openings as illustrated in
FIG. 42, and a step of forming an insulation layer 375 that fills spaces between the source electrodes 366 and the gate electrodes 360 and covers the source …
FIG. 43. [00108] As illustrated in
FIG. 44, the second substrate 309 may be attached to a surface of the insulation layer 375 opposite to the first substrate 301. Referring to
FIG. 45, the first substrate 301 may be detached from the first semiconductor layer 320. After the first substrate 101 is removed, additional blocking layers 315 …
FIG. 46. The additional blocking layers 315 may be formed of the sane material as the blocking layers 335. Further, the additional blocking layers 115 may be …
FIG. 47 is a cross-sectional view illustrating a vertical gallium nitride transistor according to an exemplary embodiment of the present invention. [0035]
FIG. 48 is a cross-sectional view illustrating a vertical gallium nitride transistor according to an exemplary embodiment of the present invention. [0036]
FIGS. 49 to 60 are cross-sectional views illustrating a method of fabricating the vertical gallium nitride transistors shown in
FIG. 50, a GaN layer 1108 may be formed on the exposed portions of the buffer layer 1104. The GaN layer 1108 may be formed to have an N-type. In one exemplary …
FIG. 51, a first drift layer 1110 may be formed on the GaN layer 1108. The first drift layer 1110 may be formed of an N-type GaN layer. Portions of the GaN layer …
FIG. 52, second drift layers 1116 may be formed on respective ones of the exposed portions of the first drift layer 1110. The second drift layers 1116 may be …
FIG. 53, channel layers 1118 may be formed on respective ones of the second drift layers 1116. The channel layers 1118 may be formed of a P-type GaN layer. The …
FIG. 54, a donor layer 1120 may be formed on the current blocking patterns 1114 and the channel layers 1118. The donor layer 1120 may be formed of an N-type …
FIG. 55, the donor layer 1120 may be etched back or planarized until top surfaces of the second drift layers 1116 are exposed. As a result, a single donor …
FIG. 56, a gate insulation layer 1122 may be formed on top surfaces of the second drift layers 1116, the channel layers 1118 and the donor layers 1120. In one …
FIG. 57, resist patterns 1160 may be formed on the gate insulation layer 1122. The resist patterns 1160 may be formed to perform a subsequent lift-off process. …
FIG. 58, the resist patterns 1160 may be removed. The resist patterns 1160 may be removed using an ashing process. When the resist patterns 1160 are removed, …
FIG. 59, the insulation layer 1126, the gate insulation layer 1122 and the donor layers 1120 may be etched to form contact holes. A metal layer may then be …
FIG. 60, a portion of the resultant including the source electrodes 1128 may be removed to expose a portion of the GaN layer 1108. A portion of the resultant …
FIG. 61,
FIG. 62, and
FIG. 63 are cross-sectional views illustrating another method of fabricating the vertical gallium nitride transistor shown in
FIGS. 64 to 75 are cross-sectional views illustrating a method of fabricating the vertical gallium nitride transistor shown in
FIG. 65, a GaN layer 1208 may be formed on the exposed portions of the buffer layer 1204. The GaN layer 1208 may be formed to have an N-type. In one exemplary …
FIG. 66, a first drift layer 1210 may be formed on the 5 GaN layer 1208. The first drift layer 1210 may be formed of an N-type GaN layer. Portions of the GaN …
FIG. 67, second drift layers 1216 may be formed on respective ones 20 of the exposed portions of the first drift layer 1210. The second drift layers 1216 may be …
FIG. 68, channel layers 1218 may be formed on respective ones of the second drift layers 1216. The channel layers 1218 may be formed of a P-type GaN layer. 10 …
FIG. 69, a donor layer 1220 may be formed on the 15 current blocking patterns 1214 and the channel layers 1218. The donor layer 1220 may be formed of an N-type …
FIG. 70, the donor layer 1220 may be etched back or planarized until top surfaces of the second drift layers 1216 are exposed. As a result, a single donor …
FIG. 71, a heterogeneous semiconductor layer 1250 may be formed on the donor layers 1220, the channel layers 1218 and the second drift layer 1216. The 58 …
FIG. 72, a gate insulation layer 1222 may be formed on a top surface of the heterogeneous semiconductor layer 1250. In one exemplary embodiment, the gate …
FIG. 73, the resist patterns 1260 may be removed. The resist patterns 1260 may be removed using an ashing process. When the resist patterns 1260 are removed, …
FIG. 74, an insulation layer 1226 may be formed on the 10 gate electrodes 1224 and the gate insulation layer 1222. Subsequently, the insulation layer 1226, the …
FIG. 75, a portion of the resultant including the source electrodes 1228 may be removed to expose a portion of the GaN layer 1208. The portion of the resultant …
FIG. 76,
FIG. 77, and
FIG. 78 are cross-sectional views illustrating another method of fabricating a vertical gallium nitride transistor shown in
FIGS. 79 to 92 are cross-sectional views illustrating a method of fabricating a 10 vertical gallium nitride transistor according to an exemplary embodiment of …
FIG. 80, second GaN layers 2108 may be grown on respective ones of the exposed portions of the first GaN layer 2104. In one exemplary embodiment, the 15 second …
FIG. 81, third GaN layers 2110 may be grown on respective ones of the second GaN layers 2108. The third GaN layers 2110 may act as channel modulation layers …
FIG. 82, current blocking patterns 2114 may formed on the fourth GaN layer 2112. In one exemplary embodiment, the current blocking patterns 2114 may be formed …
FIG. 83, a fifth GaN layer 2116 may be formed to cover the 63 current blocking patterns 2114 and the fourth GaN layer 2112. The fifth GaN layer 2116 may be …
FIG. 84, a drain electrode layer 2120 may be formed on the sixth GaN layer 2118. The drain electrode layer 2120 may be formed of a metal layer. Subsequently, a …
FIG. 85. Subsequently, the first GaN layer 2104 may be removed. The first GaN layer 2104 may be removed using an anisotropic etch process, for example, a …
FIG. 86, the mask patterns 2106 may be removed to form recessed regions 2125. In the event that the mask patterns 2106 are formed of a silicon oxide layer, the …
FIG. 87, a gate insulation layer 2127 may be formed on the second GaN layers 2108 including the recessed regions 2125. Subsequently, etch mask patterns 2130 …
FIG. 88, the gate insulation layer 2127 and the 20 second GaN layers 2108 may be etched using the etch mask patterns 2130 as etch masks. As a result, gate …
FIG. 89, lift-off mask patterns 2132 may be formed on the gate insulation patterns 2128. In one exemplary embodiment, the lift-off mask patterns 2132 may be 10 …
FIG. 90, a metal layer may be formed on a surface of the substrate including the lift-off mask patterns 2132. The metal layer may be deposited to a thickness …
FIG. 91, the lift-off mask patterns 2132 may be removed. In the event that the lift-off mask patterns 2132 are formed of a photoresist layer, the lift-off mask …
FIG. 92, if the vertical GaN transistor is turned on, carriers may be vertically 15 drifted through first regions (indicated by a reference character "B") in …
FIG. 8079 a sacrificial layer 2104, for example, a first GaN layer, may be formed on a first substrate 2102. The first substrate 2102 may act as a substrate for …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A vertical gallium nitride transistor, comprising: a first semiconductor layer of a first conductivity type comprising a first surface, a second surface opposite to the first surface, and sidewalls; a second semiconductor layer of the first conductivity type surrounding the second surface and the sidewalls of the first semiconductor layer; a third semiconductor layer of a second conductivity type disposed between the first semiconductor layer and the second semiconductor layer, the third semiconductor layer separating the first and second semiconductor layers from each other; a source electrode disposed on the first surface of the first semiconductor layer, the source electrode being electrically connected to the first semiconductor layer; a gate electrode disposed on a first surface of the third semiconductor layer between the first and second semiconductor layers; [[and]] a drain electrode, wherein the second semiconductor layer is disposed on a first surface of the drain electrode; and a current blocking layer disposed between the drain electrode and the second semiconductor layer, the current blocking layer comprising a lower surface in direct contact with the drain electrode and an upper surface that is in direct contact with the second semiconductor layer, wherein the first semiconductor layer, the third semiconductor layer, and the second 2 Application No.: 14/177,825 Reply dated Response to Office Action of semiconductor layer comprise a semiconductor structure.
The vertical gallium nitride transistor of claim 1, wherein the semiconductor structure further comprises a doped layer disposed between the drain electrode and the second semiconductor layer.
The vertical gallium nitride transistor of claim 1, further comprising a support substrate, wherein a second surface of the drain electrode opposite to the first surface is disposed on the support substrate.
The vertical gallium nitride transistor of claim 1, further comprising a current blocking layer disposed between the drain electrode and the second semiconductor layer.
The vertical gallium nitride transistor of claim 1, wherein the first and second semiconductor layers comprise N-type gallium nitride; and wherein the third semiconductor layer comprises P-type gallium nitride.
The vertical gallium nitride transistor of claim 1, wherein: the third semiconductor layer comprises a plurality of third semiconductor layers; the first semiconductor layer comprises a plurality of first semiconductor layers, the plurality of first semiconductor layers comprising a stripe pattern and a lower first semiconductor layer covering sidewalls and a bottom surface of the strip pattern; [[and]] the source electrode comprises a plurality of source electrodes; each of the plurality of third semiconductor layers surround at least two of the first 3 Application No.: 14/177,825 Reply dated Response to Office Action of semiconductor layers; [[and]] each of the source electrodes is electrically connected to at least two of the first semiconductor layers; and the second semiconductor layer surrounds the sidewalls and a bottom surface of the lower first semiconductor layer.
The vertical gallium nitride transistor of claim [[6]] 1, further comprising current blocking layers disposed between the drain electrode and the second semiconductor layer, wherein the drain electrode contacts the second semiconductor layer, between each of the current blocking layers.
The vertical gallium nitride transistor of claim 7, further comprising a dopcd laycr a low resistive layer disposed between the drain electrode and the second semiconductor layer, the low resistive layer being an etch damage layer formed by etching a portion of the second semiconductor layer.
A vertical gallium nitride transistor, comprising: a drain electrode; a first semiconductor layer of a first conductivity type disposed on the drain electrode; an undoped second semiconductor layer disposed on the first semiconductor layer; a third semiconductor layer of a second conductivity type disposed on the second semiconductor layer; a source electrode disposed on the second semiconductor layer and spaced apart from the third semiconductor layer; 4 Application No.: 14/177,825 Reply dated Response to Office Action of an insulation layer disposed on the third semiconductor layer; a gate electrode disposed on the insulation layer; and a first blocking layer disposed between the first and second semiconductor layers, wherein the first blocking layer is disposed between the source electrode and the drain electrode, and is configured to block a vertical current path between the source electrode and the drain electrode. withdrawn
The vertical gallium nitride transistor of claim 9, further comprising a second blocking layer disposed between the drain electrode and the first semiconductor layer, wherein the second blocking layer is disposed between the blocking layer and the drain electrode. withdrawn
The vertical gallium nitride transistor of claim 9, wherein the first semiconductor layer comprises: a first gallium nitride layer doped with impurities of the first conductivity type at a first concentration; and a second gallium nitride layer doped with impurities of the first conductivity type at a second concentration that is lower than the first concentration, wherein the first gallium nitride layer and the second gallium nitride layer are sequentially disposed on the drain electrode. withdrawn
The vertical gallium nitride transistor of claim 9, wherein the second semiconductor layer comprises a depletion region that is configured to contact the blocking layer when no bias voltage is applied to the gate electrode; and wherein the depletion region is configured to be spaced apart from the blocking layer 5 Application No.: 14/177,825 Reply dated Response to Office Action of when a gate voltage greater than a threshold voltage is applied to the gate electrode. withdrawn
The vertical gallium nitride transistor of claim 9, further comprising: a vertical drain electrode vertically penetrating the second semiconductor layer and the first semiconductor layer, the vertical drain electrode having a first band gap energy; and a channel layer disposed in the first semiconductor layer, the channel layer being electrically connected to the vertical drain electrode, wherein the channel layer has a second band gap energy different from the first band gap energy, and the channel layer comprises gallium nitride. withdrawn
The vertical gallium nitride transistor of claim 9, further comprising a barrier layer disposed between the second and third semiconductor layers, wherein the barrier layer has a band gap energy different from a band gap energy of the second semiconductor layer, and wherein the barrier layer comprises aluminum gallium nitride. withdrawn
A vertical gallium nitride transistor, comprising: a substrate; a buffer layer disposed on the substrate; a mask pattern disposed on the buffer layer, the mask pattern exposing portions of the buffer layer; a gallium nitride layer disposed on the mask pattern and the exposed portions of the 6 Application No.: 14/177,825 Reply dated Response to Office Action of buffer layer; a first drift layer disposed on a portion of the gallium nitride layer; a current blocking pattern disposed on the first drift layer, the current blocking pattern exposing a portion of the first drift layer; a second drift layer disposed on the exposed portion of the first drift layer; a donor layer disposed on the current blocking pattern; a channel layer disposed on the current blocking pattern, the channel layer surrounding sidewalls of the donor layer; a gate electrode disposed on the second drift layer; a gate insulation layer disposed between, and configured to insulate, the gate electrode and the second drift layer; a source electrode disposed on the donor layer and electrically connected to the donor layer; and a drain electrode disposed on the gallium nitride layer and spaced apart from the first drift layer. withdrawn
The vertical gallium nitride transistor of claim 16, wherein the buffer layer comprises N-type gallium nitride; wherein the first drift layer, the second drift layer, and the donor layer comprise N-type gallium nitride having impurity concentrations that are lower than an impurity concentration of the buffer layer; and wherein the channel layer comprises P-type gallium nitride. withdrawn
The vertical gallium nitride transistor of claim 16, wherein the second drift layer disposed on the exposed portion of the first drift layer vertically overlaps with 7 Application No.: 14/177,825 Reply dated Response to Office Action of the mask pattern. withdrawn
The vertical gallium nitride transistor of claim 16, further comprising: a heterogeneous semiconductor layer disposed on the second drift layer, the heterogeneous semiconductor layer configured to form a two dimension electron gas (2DEG) layer at an interface with a first surface of the second drift layer, wherein the gate electrode is disposed on the heterogeneous semiconductor layer. withdrawn
The vertical gallium nitride transistor of claim heterogeneous semiconductor layer is disposed on the heterogeneous semiconductor layer is disposed portion of the heterogeneous semiconductor layer heterogeneous semiconductor layer. 8 withdrawn 19, wherein a first portion of the second drift layer and a second portion of on the channel layer, and wherein the first is thicker than the second portion of the
Layer stacks claimed or described, ordered top of device to substrate.
vertical gallium nitride transistor (claims 1-8)
Materials described outside the worked examples.
N-type gallium nitride
GaN
aluminum gallium nitride
AlGaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a cross-sectional view illustrating a vertical gallium nitride transistor according to an exemplary embodiment of the present invention. 20 [0024]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 7–9 µm | — |
Thickness | 18–1000 nm |
Table 1
ectric fields Emax according to various reverse bias voltages V b may be summarized as listed in the following table 1.
p. 9
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US 9,219,137Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view illustrating a vertical gallium nitride transistor according to an exemplary embodiment of the present invention. 20 [0024]
FIGS. 2 to 9 are cross-sectional views illustrating a method of fabricating the vertical gallium nitride transistor according to the exemplary embodiment of
FIG. 3). In such a case, the GaN layer may be formed to a thickness of about 1 micrometer to about 2 micrometers. Referring to
FIG. 4, additional semiconductor layers 25a of the first conductivity 20 type may be grown on respective stripe patterns 23a. The additional semiconductor …
FIG. 5, current blocking layers 31 may be formed on the second semiconductor layer 29. The current blocking layers 31 may be formed by depositing a silicon …
FIG. 6, a support substrate 41 may be attached to the second semiconductor layer 29. The support substrate 41 may be formed by depositing a metal layer 35 …
FIG. 7, the growth substrate 21 may be removed from the semiconductor layers 25, 27, and 29 including the stripe patterns 25a. The growth substrate 21 10 may …
FIG. 8, source electrodes 43 may be formed on the top surface of the semiconductor structure 20. The source electrodes 43 may be formed to be electrically …
FIG. 9 are cross- sectional views illustrating a method of fabricating the vertical gallium nitride transistor shown in
FIG. 10 is a cross-sectional view illustrating an off-state of a vertical gallium nitride transistor according to an exemplary embodiment of the present …
FIG. 11 is a cross-sectional view illustrating an on-state of the vertical gallium nitride transistor according to the exemplary embodiment of
FIGS. 12 to 27 are cross-sectional views illustrating a method of fabricating the vertical gallium nitride transistor according to an exemplary embodiment of …
FIG. 13, a GaN layer heavily doped with N-type impurities may be 10 grown on the seed layer 102 to form a first semiconductor layer 120. The first semiconductor …
FIG. 14, a GaN layer lightly doped with N-type impurities may be grown on the first semiconductor layer 120 to form a first semiconductor layer 125. That is, the …
FIG. 15, the blocking layers 135 may be formed on the 31 upper GaN layer 125 to face respective ones of the seed patterns 102. Each of the blocking layers 135 …
FIG. 16, the second semiconductor layer 140 may be formed of an undoped GaN layer. The second semiconductor layers 140 may be formed to cover edges of the …
FIG. 17, the third semiconductor layer 150 may be formed of a P- type GaN layer on entire surfaces of the blocking layers 135 and the second semiconductor …
FIG. 18, the insulation layer 155 may be formed on the 15 third semiconductor layer 150, for example, the P-type GaN layer. [0087] Refe rr ing to
FIGS. 19 to 24A, the step of forming the source electrodes 166 and the gate electrodes 160 may include a step of forming a metal layer 160 on the insulation …
FIG. 20, a step of patterning the insulation layer 155 and the 20 P-type GaN layer 150 to form openings that expose portions of the second semiconductor layer …
FIG. 21, a step of forming the source electrodes 166 composed of a metal layer in the openings as illustrated in
FIG. 22, and a step of forming a passivation layer 175 that fills spaces between the source electrodes 166 and the 32 gate electrodes 160 and covers the source …
FIG. 23, 24A, and
FIG. 24B are cross-sectional views illustrating a method of fabricating a vertical gallium nitride according to an exemplary embodiment of the present …
FIG. 25, the second substrate 109 may be attached to a surface of the passivation layer 175 opposite to the first substrate 101. Referring to
FIG. 26, the first substrate 101 may be detached from the first semiconductor layers 120 and 125. The first substrate 101 may be detached using a laser lift-off 5 …
FIG. 27. The additional blocking layers 115 may be formed of the same material as the blocking layers 135. Further, the additional blocking layers 115 may be …
FIG. 28 is a cross-sectional view illustrating an off-state of a vertical gallium 10 nitride transistor according to an exemplary embodiment of the present …
FIG. 29 is a cross-sectional view illustrating an on-state of the vertical gallium nitride transistor according to the exemplary embodiment of
FIG. 30 is a cross-sectional view illustrating an off-state of a vertical gallium nitride transistor according to an exemplary embodiment of the present …
FIG. 31 is a cross-sectional view illustrating an on-state of the vertical gallium nitride transistor according to the exemplary embodiment of
FIGS. 32 to 46 are cross-sectional views illustrating a method of fabricating the vertical gallium nitride transistor according to an exemplary embodiment of …
FIG. 33, a GaN layer heavily doped with N- type impurities may be grown on the seed patterns 302 to form the first semiconductor layer 320. [00103] Refe rr ing …
FIG. 34, a GaN layer lightly doped with N-type impurities 5 may be grown on the first semiconductor layer 320 to form the first semiconductor layer 325. That is, …
FIG. 35, the blocking layers 335 may be formed on the upper GaN layer 325 to face respective ones of the seed patterns 302. Each of the blocking layers 335 may …
FIG. 36, an undoped GaN layer may be grown using the first semiconductor layer 325 as a seed layer to form the second semiconductor layers 340. The 20 second …
FIG. 37. The insulation layer 355 may be formed on the third semiconductor layer 350, as illustrated in
FIG. 38. [00107] The step of forming the source electrodes 366 and the gate electrodes 360 may include a step of forming a metal layer 360 on the insulation …
FIG. 39, a step of patterning the metal layer 360 to form the gate electrodes 360 as illustrated in
FIG. 41, a step of forming the source electrodes 366 composed of a metal layer in the openings as illustrated in
FIG. 42, and a step of forming an insulation layer 375 that fills spaces between the source electrodes 366 and the gate electrodes 360 and covers the source …
FIG. 43. [00108] As illustrated in
FIG. 44, the second substrate 309 may be attached to a surface of the insulation layer 375 opposite to the first substrate 301. Referring to
FIG. 45, the first substrate 301 may be detached from the first semiconductor layer 320. After the first substrate 101 is removed, additional blocking layers 315 …
FIG. 46. The additional blocking layers 315 may be formed of the sane material as the blocking layers 335. Further, the additional blocking layers 115 may be …
FIG. 47 is a cross-sectional view illustrating a vertical gallium nitride transistor according to an exemplary embodiment of the present invention. [0035]
FIG. 48 is a cross-sectional view illustrating a vertical gallium nitride transistor according to an exemplary embodiment of the present invention. [0036]
FIGS. 49 to 60 are cross-sectional views illustrating a method of fabricating the vertical gallium nitride transistors shown in
FIG. 50, a GaN layer 1108 may be formed on the exposed portions of the buffer layer 1104. The GaN layer 1108 may be formed to have an N-type. In one exemplary …
FIG. 51, a first drift layer 1110 may be formed on the GaN layer 1108. The first drift layer 1110 may be formed of an N-type GaN layer. Portions of the GaN layer …
FIG. 52, second drift layers 1116 may be formed on respective ones of the exposed portions of the first drift layer 1110. The second drift layers 1116 may be …
FIG. 53, channel layers 1118 may be formed on respective ones of the second drift layers 1116. The channel layers 1118 may be formed of a P-type GaN layer. The …
FIG. 54, a donor layer 1120 may be formed on the current blocking patterns 1114 and the channel layers 1118. The donor layer 1120 may be formed of an N-type …
FIG. 55, the donor layer 1120 may be etched back or planarized until top surfaces of the second drift layers 1116 are exposed. As a result, a single donor …
FIG. 56, a gate insulation layer 1122 may be formed on top surfaces of the second drift layers 1116, the channel layers 1118 and the donor layers 1120. In one …
FIG. 57, resist patterns 1160 may be formed on the gate insulation layer 1122. The resist patterns 1160 may be formed to perform a subsequent lift-off process. …
FIG. 58, the resist patterns 1160 may be removed. The resist patterns 1160 may be removed using an ashing process. When the resist patterns 1160 are removed, …
FIG. 59, the insulation layer 1126, the gate insulation layer 1122 and the donor layers 1120 may be etched to form contact holes. A metal layer may then be …
FIG. 60, a portion of the resultant including the source electrodes 1128 may be removed to expose a portion of the GaN layer 1108. A portion of the resultant …
FIG. 61,
FIG. 62, and
FIG. 63 are cross-sectional views illustrating another method of fabricating the vertical gallium nitride transistor shown in
FIGS. 64 to 75 are cross-sectional views illustrating a method of fabricating the vertical gallium nitride transistor shown in
FIG. 65, a GaN layer 1208 may be formed on the exposed portions of the buffer layer 1204. The GaN layer 1208 may be formed to have an N-type. In one exemplary …
FIG. 66, a first drift layer 1210 may be formed on the 5 GaN layer 1208. The first drift layer 1210 may be formed of an N-type GaN layer. Portions of the GaN …
FIG. 67, second drift layers 1216 may be formed on respective ones 20 of the exposed portions of the first drift layer 1210. The second drift layers 1216 may be …
FIG. 68, channel layers 1218 may be formed on respective ones of the second drift layers 1216. The channel layers 1218 may be formed of a P-type GaN layer. 10 …
FIG. 69, a donor layer 1220 may be formed on the 15 current blocking patterns 1214 and the channel layers 1218. The donor layer 1220 may be formed of an N-type …
FIG. 70, the donor layer 1220 may be etched back or planarized until top surfaces of the second drift layers 1216 are exposed. As a result, a single donor …
FIG. 71, a heterogeneous semiconductor layer 1250 may be formed on the donor layers 1220, the channel layers 1218 and the second drift layer 1216. The 58 …
FIG. 72, a gate insulation layer 1222 may be formed on a top surface of the heterogeneous semiconductor layer 1250. In one exemplary embodiment, the gate …
FIG. 73, the resist patterns 1260 may be removed. The resist patterns 1260 may be removed using an ashing process. When the resist patterns 1260 are removed, …
FIG. 74, an insulation layer 1226 may be formed on the 10 gate electrodes 1224 and the gate insulation layer 1222. Subsequently, the insulation layer 1226, the …
FIG. 75, a portion of the resultant including the source electrodes 1228 may be removed to expose a portion of the GaN layer 1208. The portion of the resultant …
FIG. 76,
FIG. 77, and
FIG. 78 are cross-sectional views illustrating another method of fabricating a vertical gallium nitride transistor shown in
FIGS. 79 to 92 are cross-sectional views illustrating a method of fabricating a 10 vertical gallium nitride transistor according to an exemplary embodiment of …
FIG. 80, second GaN layers 2108 may be grown on respective ones of the exposed portions of the first GaN layer 2104. In one exemplary embodiment, the 15 second …
FIG. 81, third GaN layers 2110 may be grown on respective ones of the second GaN layers 2108. The third GaN layers 2110 may act as channel modulation layers …
FIG. 82, current blocking patterns 2114 may formed on the fourth GaN layer 2112. In one exemplary embodiment, the current blocking patterns 2114 may be formed …
FIG. 83, a fifth GaN layer 2116 may be formed to cover the 63 current blocking patterns 2114 and the fourth GaN layer 2112. The fifth GaN layer 2116 may be …
FIG. 84, a drain electrode layer 2120 may be formed on the sixth GaN layer 2118. The drain electrode layer 2120 may be formed of a metal layer. Subsequently, a …
FIG. 85. Subsequently, the first GaN layer 2104 may be removed. The first GaN layer 2104 may be removed using an anisotropic etch process, for example, a …
FIG. 86, the mask patterns 2106 may be removed to form recessed regions 2125. In the event that the mask patterns 2106 are formed of a silicon oxide layer, the …
FIG. 87, a gate insulation layer 2127 may be formed on the second GaN layers 2108 including the recessed regions 2125. Subsequently, etch mask patterns 2130 …
FIG. 88, the gate insulation layer 2127 and the 20 second GaN layers 2108 may be etched using the etch mask patterns 2130 as etch masks. As a result, gate …
FIG. 89, lift-off mask patterns 2132 may be formed on the gate insulation patterns 2128. In one exemplary embodiment, the lift-off mask patterns 2132 may be 10 …
FIG. 90, a metal layer may be formed on a surface of the substrate including the lift-off mask patterns 2132. The metal layer may be deposited to a thickness …
FIG. 91, the lift-off mask patterns 2132 may be removed. In the event that the lift-off mask patterns 2132 are formed of a photoresist layer, the lift-off mask …
FIG. 92, if the vertical GaN transistor is turned on, carriers may be vertically 15 drifted through first regions (indicated by a reference character "B") in …
FIG. 8079 a sacrificial layer 2104, for example, a first GaN layer, may be formed on a first substrate 2102. The first substrate 2102 may act as a substrate for …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A vertical gallium nitride transistor, comprising: a first semiconductor layer of a first conductivity type comprising a first surface, a second surface opposite to the first surface, and sidewalls; a second semiconductor layer of the first conductivity type surrounding the second surface and the sidewalls of the first semiconductor layer; a third semiconductor layer of a second conductivity type disposed between the first semiconductor layer and the second semiconductor layer, the third semiconductor layer separating the first and second semiconductor layers from each other; a source electrode disposed on the first surface of the first semiconductor layer, the source electrode being electrically connected to the first semiconductor layer; a gate electrode disposed on a first surface of the third semiconductor layer between the first and second semiconductor layers; [[and]] a drain electrode, wherein the second semiconductor layer is disposed on a first surface of the drain electrode; and a current blocking layer disposed between the drain electrode and the second semiconductor layer, the current blocking layer comprising a lower surface in direct contact with the drain electrode and an upper surface that is in direct contact with the second semiconductor layer, wherein the first semiconductor layer, the third semiconductor layer, and the second 2 Application No.: 14/177,825 Reply dated Response to Office Action of semiconductor layer comprise a semiconductor structure.
The vertical gallium nitride transistor of claim 1, wherein the semiconductor structure further comprises a doped layer disposed between the drain electrode and the second semiconductor layer.
The vertical gallium nitride transistor of claim 1, further comprising a support substrate, wherein a second surface of the drain electrode opposite to the first surface is disposed on the support substrate.
The vertical gallium nitride transistor of claim 1, further comprising a current blocking layer disposed between the drain electrode and the second semiconductor layer.
The vertical gallium nitride transistor of claim 1, wherein the first and second semiconductor layers comprise N-type gallium nitride; and wherein the third semiconductor layer comprises P-type gallium nitride.
The vertical gallium nitride transistor of claim 1, wherein: the third semiconductor layer comprises a plurality of third semiconductor layers; the first semiconductor layer comprises a plurality of first semiconductor layers, the plurality of first semiconductor layers comprising a stripe pattern and a lower first semiconductor layer covering sidewalls and a bottom surface of the strip pattern; [[and]] the source electrode comprises a plurality of source electrodes; each of the plurality of third semiconductor layers surround at least two of the first 3 Application No.: 14/177,825 Reply dated Response to Office Action of semiconductor layers; [[and]] each of the source electrodes is electrically connected to at least two of the first semiconductor layers; and the second semiconductor layer surrounds the sidewalls and a bottom surface of the lower first semiconductor layer.
The vertical gallium nitride transistor of claim [[6]] 1, further comprising current blocking layers disposed between the drain electrode and the second semiconductor layer, wherein the drain electrode contacts the second semiconductor layer, between each of the current blocking layers.
The vertical gallium nitride transistor of claim 7, further comprising a dopcd laycr a low resistive layer disposed between the drain electrode and the second semiconductor layer, the low resistive layer being an etch damage layer formed by etching a portion of the second semiconductor layer.
A vertical gallium nitride transistor, comprising: a drain electrode; a first semiconductor layer of a first conductivity type disposed on the drain electrode; an undoped second semiconductor layer disposed on the first semiconductor layer; a third semiconductor layer of a second conductivity type disposed on the second semiconductor layer; a source electrode disposed on the second semiconductor layer and spaced apart from the third semiconductor layer; 4 Application No.: 14/177,825 Reply dated Response to Office Action of an insulation layer disposed on the third semiconductor layer; a gate electrode disposed on the insulation layer; and a first blocking layer disposed between the first and second semiconductor layers, wherein the first blocking layer is disposed between the source electrode and the drain electrode, and is configured to block a vertical current path between the source electrode and the drain electrode. withdrawn
The vertical gallium nitride transistor of claim 9, further comprising a second blocking layer disposed between the drain electrode and the first semiconductor layer, wherein the second blocking layer is disposed between the blocking layer and the drain electrode. withdrawn
The vertical gallium nitride transistor of claim 9, wherein the first semiconductor layer comprises: a first gallium nitride layer doped with impurities of the first conductivity type at a first concentration; and a second gallium nitride layer doped with impurities of the first conductivity type at a second concentration that is lower than the first concentration, wherein the first gallium nitride layer and the second gallium nitride layer are sequentially disposed on the drain electrode. withdrawn
The vertical gallium nitride transistor of claim 9, wherein the second semiconductor layer comprises a depletion region that is configured to contact the blocking layer when no bias voltage is applied to the gate electrode; and wherein the depletion region is configured to be spaced apart from the blocking layer 5 Application No.: 14/177,825 Reply dated Response to Office Action of when a gate voltage greater than a threshold voltage is applied to the gate electrode. withdrawn
The vertical gallium nitride transistor of claim 9, further comprising: a vertical drain electrode vertically penetrating the second semiconductor layer and the first semiconductor layer, the vertical drain electrode having a first band gap energy; and a channel layer disposed in the first semiconductor layer, the channel layer being electrically connected to the vertical drain electrode, wherein the channel layer has a second band gap energy different from the first band gap energy, and the channel layer comprises gallium nitride. withdrawn
The vertical gallium nitride transistor of claim 9, further comprising a barrier layer disposed between the second and third semiconductor layers, wherein the barrier layer has a band gap energy different from a band gap energy of the second semiconductor layer, and wherein the barrier layer comprises aluminum gallium nitride. withdrawn
A vertical gallium nitride transistor, comprising: a substrate; a buffer layer disposed on the substrate; a mask pattern disposed on the buffer layer, the mask pattern exposing portions of the buffer layer; a gallium nitride layer disposed on the mask pattern and the exposed portions of the 6 Application No.: 14/177,825 Reply dated Response to Office Action of buffer layer; a first drift layer disposed on a portion of the gallium nitride layer; a current blocking pattern disposed on the first drift layer, the current blocking pattern exposing a portion of the first drift layer; a second drift layer disposed on the exposed portion of the first drift layer; a donor layer disposed on the current blocking pattern; a channel layer disposed on the current blocking pattern, the channel layer surrounding sidewalls of the donor layer; a gate electrode disposed on the second drift layer; a gate insulation layer disposed between, and configured to insulate, the gate electrode and the second drift layer; a source electrode disposed on the donor layer and electrically connected to the donor layer; and a drain electrode disposed on the gallium nitride layer and spaced apart from the first drift layer. withdrawn
The vertical gallium nitride transistor of claim 16, wherein the buffer layer comprises N-type gallium nitride; wherein the first drift layer, the second drift layer, and the donor layer comprise N-type gallium nitride having impurity concentrations that are lower than an impurity concentration of the buffer layer; and wherein the channel layer comprises P-type gallium nitride. withdrawn
The vertical gallium nitride transistor of claim 16, wherein the second drift layer disposed on the exposed portion of the first drift layer vertically overlaps with 7 Application No.: 14/177,825 Reply dated Response to Office Action of the mask pattern. withdrawn
The vertical gallium nitride transistor of claim 16, further comprising: a heterogeneous semiconductor layer disposed on the second drift layer, the heterogeneous semiconductor layer configured to form a two dimension electron gas (2DEG) layer at an interface with a first surface of the second drift layer, wherein the gate electrode is disposed on the heterogeneous semiconductor layer. withdrawn
The vertical gallium nitride transistor of claim heterogeneous semiconductor layer is disposed on the heterogeneous semiconductor layer is disposed portion of the heterogeneous semiconductor layer heterogeneous semiconductor layer. 8 withdrawn 19, wherein a first portion of the second drift layer and a second portion of on the channel layer, and wherein the first is thicker than the second portion of the
Layer stacks claimed or described, ordered top of device to substrate.
vertical gallium nitride transistor (claims 1-8)
Materials described outside the worked examples.
N-type gallium nitride
GaN
aluminum gallium nitride
AlGaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a cross-sectional view illustrating a vertical gallium nitride transistor according to an exemplary embodiment of the present invention. 20 [0024]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 7–9 µm | — |
Thickness | 18–1000 nm |
Table 1
ectric fields Emax according to various reverse bias voltages V b may be summarized as listed in the following table 1.
p. 9
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US 9,219,137Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view illustrating a vertical gallium nitride transistor according to an exemplary embodiment of the present invention. 20 [0024]
FIGS. 2 to 9 are cross-sectional views illustrating a method of fabricating the vertical gallium nitride transistor according to the exemplary embodiment of
FIG. 3). In such a case, the GaN layer may be formed to a thickness of about 1 micrometer to about 2 micrometers. Referring to
FIG. 4, additional semiconductor layers 25a of the first conductivity 20 type may be grown on respective stripe patterns 23a. The additional semiconductor …
FIG. 5, current blocking layers 31 may be formed on the second semiconductor layer 29. The current blocking layers 31 may be formed by depositing a silicon …
FIG. 6, a support substrate 41 may be attached to the second semiconductor layer 29. The support substrate 41 may be formed by depositing a metal layer 35 …
FIG. 7, the growth substrate 21 may be removed from the semiconductor layers 25, 27, and 29 including the stripe patterns 25a. The growth substrate 21 10 may …
FIG. 8, source electrodes 43 may be formed on the top surface of the semiconductor structure 20. The source electrodes 43 may be formed to be electrically …
FIG. 9 are cross- sectional views illustrating a method of fabricating the vertical gallium nitride transistor shown in
FIG. 10 is a cross-sectional view illustrating an off-state of a vertical gallium nitride transistor according to an exemplary embodiment of the present …
FIG. 11 is a cross-sectional view illustrating an on-state of the vertical gallium nitride transistor according to the exemplary embodiment of
FIGS. 12 to 27 are cross-sectional views illustrating a method of fabricating the vertical gallium nitride transistor according to an exemplary embodiment of …
FIG. 13, a GaN layer heavily doped with N-type impurities may be 10 grown on the seed layer 102 to form a first semiconductor layer 120. The first semiconductor …
FIG. 14, a GaN layer lightly doped with N-type impurities may be grown on the first semiconductor layer 120 to form a first semiconductor layer 125. That is, the …
FIG. 15, the blocking layers 135 may be formed on the 31 upper GaN layer 125 to face respective ones of the seed patterns 102. Each of the blocking layers 135 …
FIG. 16, the second semiconductor layer 140 may be formed of an undoped GaN layer. The second semiconductor layers 140 may be formed to cover edges of the …
FIG. 17, the third semiconductor layer 150 may be formed of a P- type GaN layer on entire surfaces of the blocking layers 135 and the second semiconductor …
FIG. 18, the insulation layer 155 may be formed on the 15 third semiconductor layer 150, for example, the P-type GaN layer. [0087] Refe rr ing to
FIGS. 19 to 24A, the step of forming the source electrodes 166 and the gate electrodes 160 may include a step of forming a metal layer 160 on the insulation …
FIG. 20, a step of patterning the insulation layer 155 and the 20 P-type GaN layer 150 to form openings that expose portions of the second semiconductor layer …
FIG. 21, a step of forming the source electrodes 166 composed of a metal layer in the openings as illustrated in
FIG. 22, and a step of forming a passivation layer 175 that fills spaces between the source electrodes 166 and the 32 gate electrodes 160 and covers the source …
FIG. 23, 24A, and
FIG. 24B are cross-sectional views illustrating a method of fabricating a vertical gallium nitride according to an exemplary embodiment of the present …
FIG. 25, the second substrate 109 may be attached to a surface of the passivation layer 175 opposite to the first substrate 101. Referring to
FIG. 26, the first substrate 101 may be detached from the first semiconductor layers 120 and 125. The first substrate 101 may be detached using a laser lift-off 5 …
FIG. 27. The additional blocking layers 115 may be formed of the same material as the blocking layers 135. Further, the additional blocking layers 115 may be …
FIG. 28 is a cross-sectional view illustrating an off-state of a vertical gallium 10 nitride transistor according to an exemplary embodiment of the present …
FIG. 29 is a cross-sectional view illustrating an on-state of the vertical gallium nitride transistor according to the exemplary embodiment of
FIG. 30 is a cross-sectional view illustrating an off-state of a vertical gallium nitride transistor according to an exemplary embodiment of the present …
FIG. 31 is a cross-sectional view illustrating an on-state of the vertical gallium nitride transistor according to the exemplary embodiment of
FIGS. 32 to 46 are cross-sectional views illustrating a method of fabricating the vertical gallium nitride transistor according to an exemplary embodiment of …
FIG. 33, a GaN layer heavily doped with N- type impurities may be grown on the seed patterns 302 to form the first semiconductor layer 320. [00103] Refe rr ing …
FIG. 34, a GaN layer lightly doped with N-type impurities 5 may be grown on the first semiconductor layer 320 to form the first semiconductor layer 325. That is, …
FIG. 35, the blocking layers 335 may be formed on the upper GaN layer 325 to face respective ones of the seed patterns 302. Each of the blocking layers 335 may …
FIG. 36, an undoped GaN layer may be grown using the first semiconductor layer 325 as a seed layer to form the second semiconductor layers 340. The 20 second …
FIG. 37. The insulation layer 355 may be formed on the third semiconductor layer 350, as illustrated in
FIG. 38. [00107] The step of forming the source electrodes 366 and the gate electrodes 360 may include a step of forming a metal layer 360 on the insulation …
FIG. 39, a step of patterning the metal layer 360 to form the gate electrodes 360 as illustrated in
FIG. 41, a step of forming the source electrodes 366 composed of a metal layer in the openings as illustrated in
FIG. 42, and a step of forming an insulation layer 375 that fills spaces between the source electrodes 366 and the gate electrodes 360 and covers the source …
FIG. 43. [00108] As illustrated in
FIG. 44, the second substrate 309 may be attached to a surface of the insulation layer 375 opposite to the first substrate 301. Referring to
FIG. 45, the first substrate 301 may be detached from the first semiconductor layer 320. After the first substrate 101 is removed, additional blocking layers 315 …
FIG. 46. The additional blocking layers 315 may be formed of the sane material as the blocking layers 335. Further, the additional blocking layers 115 may be …
FIG. 47 is a cross-sectional view illustrating a vertical gallium nitride transistor according to an exemplary embodiment of the present invention. [0035]
FIG. 48 is a cross-sectional view illustrating a vertical gallium nitride transistor according to an exemplary embodiment of the present invention. [0036]
FIGS. 49 to 60 are cross-sectional views illustrating a method of fabricating the vertical gallium nitride transistors shown in
FIG. 50, a GaN layer 1108 may be formed on the exposed portions of the buffer layer 1104. The GaN layer 1108 may be formed to have an N-type. In one exemplary …
FIG. 51, a first drift layer 1110 may be formed on the GaN layer 1108. The first drift layer 1110 may be formed of an N-type GaN layer. Portions of the GaN layer …
FIG. 52, second drift layers 1116 may be formed on respective ones of the exposed portions of the first drift layer 1110. The second drift layers 1116 may be …
FIG. 53, channel layers 1118 may be formed on respective ones of the second drift layers 1116. The channel layers 1118 may be formed of a P-type GaN layer. The …
FIG. 54, a donor layer 1120 may be formed on the current blocking patterns 1114 and the channel layers 1118. The donor layer 1120 may be formed of an N-type …
FIG. 55, the donor layer 1120 may be etched back or planarized until top surfaces of the second drift layers 1116 are exposed. As a result, a single donor …
FIG. 56, a gate insulation layer 1122 may be formed on top surfaces of the second drift layers 1116, the channel layers 1118 and the donor layers 1120. In one …
FIG. 57, resist patterns 1160 may be formed on the gate insulation layer 1122. The resist patterns 1160 may be formed to perform a subsequent lift-off process. …
FIG. 58, the resist patterns 1160 may be removed. The resist patterns 1160 may be removed using an ashing process. When the resist patterns 1160 are removed, …
FIG. 59, the insulation layer 1126, the gate insulation layer 1122 and the donor layers 1120 may be etched to form contact holes. A metal layer may then be …
FIG. 60, a portion of the resultant including the source electrodes 1128 may be removed to expose a portion of the GaN layer 1108. A portion of the resultant …
FIG. 61,
FIG. 62, and
FIG. 63 are cross-sectional views illustrating another method of fabricating the vertical gallium nitride transistor shown in
FIGS. 64 to 75 are cross-sectional views illustrating a method of fabricating the vertical gallium nitride transistor shown in
FIG. 65, a GaN layer 1208 may be formed on the exposed portions of the buffer layer 1204. The GaN layer 1208 may be formed to have an N-type. In one exemplary …
FIG. 66, a first drift layer 1210 may be formed on the 5 GaN layer 1208. The first drift layer 1210 may be formed of an N-type GaN layer. Portions of the GaN …
FIG. 67, second drift layers 1216 may be formed on respective ones 20 of the exposed portions of the first drift layer 1210. The second drift layers 1216 may be …
FIG. 68, channel layers 1218 may be formed on respective ones of the second drift layers 1216. The channel layers 1218 may be formed of a P-type GaN layer. 10 …
FIG. 69, a donor layer 1220 may be formed on the 15 current blocking patterns 1214 and the channel layers 1218. The donor layer 1220 may be formed of an N-type …
FIG. 70, the donor layer 1220 may be etched back or planarized until top surfaces of the second drift layers 1216 are exposed. As a result, a single donor …
FIG. 71, a heterogeneous semiconductor layer 1250 may be formed on the donor layers 1220, the channel layers 1218 and the second drift layer 1216. The 58 …
FIG. 72, a gate insulation layer 1222 may be formed on a top surface of the heterogeneous semiconductor layer 1250. In one exemplary embodiment, the gate …
FIG. 73, the resist patterns 1260 may be removed. The resist patterns 1260 may be removed using an ashing process. When the resist patterns 1260 are removed, …
FIG. 74, an insulation layer 1226 may be formed on the 10 gate electrodes 1224 and the gate insulation layer 1222. Subsequently, the insulation layer 1226, the …
FIG. 75, a portion of the resultant including the source electrodes 1228 may be removed to expose a portion of the GaN layer 1208. The portion of the resultant …
FIG. 76,
FIG. 77, and
FIG. 78 are cross-sectional views illustrating another method of fabricating a vertical gallium nitride transistor shown in
FIGS. 79 to 92 are cross-sectional views illustrating a method of fabricating a 10 vertical gallium nitride transistor according to an exemplary embodiment of …
FIG. 80, second GaN layers 2108 may be grown on respective ones of the exposed portions of the first GaN layer 2104. In one exemplary embodiment, the 15 second …
FIG. 81, third GaN layers 2110 may be grown on respective ones of the second GaN layers 2108. The third GaN layers 2110 may act as channel modulation layers …
FIG. 82, current blocking patterns 2114 may formed on the fourth GaN layer 2112. In one exemplary embodiment, the current blocking patterns 2114 may be formed …
FIG. 83, a fifth GaN layer 2116 may be formed to cover the 63 current blocking patterns 2114 and the fourth GaN layer 2112. The fifth GaN layer 2116 may be …
FIG. 84, a drain electrode layer 2120 may be formed on the sixth GaN layer 2118. The drain electrode layer 2120 may be formed of a metal layer. Subsequently, a …
FIG. 85. Subsequently, the first GaN layer 2104 may be removed. The first GaN layer 2104 may be removed using an anisotropic etch process, for example, a …
FIG. 86, the mask patterns 2106 may be removed to form recessed regions 2125. In the event that the mask patterns 2106 are formed of a silicon oxide layer, the …
FIG. 87, a gate insulation layer 2127 may be formed on the second GaN layers 2108 including the recessed regions 2125. Subsequently, etch mask patterns 2130 …
FIG. 88, the gate insulation layer 2127 and the 20 second GaN layers 2108 may be etched using the etch mask patterns 2130 as etch masks. As a result, gate …
FIG. 89, lift-off mask patterns 2132 may be formed on the gate insulation patterns 2128. In one exemplary embodiment, the lift-off mask patterns 2132 may be 10 …
FIG. 90, a metal layer may be formed on a surface of the substrate including the lift-off mask patterns 2132. The metal layer may be deposited to a thickness …
FIG. 91, the lift-off mask patterns 2132 may be removed. In the event that the lift-off mask patterns 2132 are formed of a photoresist layer, the lift-off mask …
FIG. 92, if the vertical GaN transistor is turned on, carriers may be vertically 15 drifted through first regions (indicated by a reference character "B") in …
FIG. 8079 a sacrificial layer 2104, for example, a first GaN layer, may be formed on a first substrate 2102. The first substrate 2102 may act as a substrate for …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A vertical gallium nitride transistor, comprising: a first semiconductor layer of a first conductivity type comprising a first surface, a second surface opposite to the first surface, and sidewalls; a second semiconductor layer of the first conductivity type surrounding the second surface and the sidewalls of the first semiconductor layer; a third semiconductor layer of a second conductivity type disposed between the first semiconductor layer and the second semiconductor layer, the third semiconductor layer separating the first and second semiconductor layers from each other; a source electrode disposed on the first surface of the first semiconductor layer, the source electrode being electrically connected to the first semiconductor layer; a gate electrode disposed on a first surface of the third semiconductor layer between the first and second semiconductor layers; [[and]] a drain electrode, wherein the second semiconductor layer is disposed on a first surface of the drain electrode; and a current blocking layer disposed between the drain electrode and the second semiconductor layer, the current blocking layer comprising a lower surface in direct contact with the drain electrode and an upper surface that is in direct contact with the second semiconductor layer, wherein the first semiconductor layer, the third semiconductor layer, and the second 2 Application No.: 14/177,825 Reply dated Response to Office Action of semiconductor layer comprise a semiconductor structure.
The vertical gallium nitride transistor of claim 1, wherein the semiconductor structure further comprises a doped layer disposed between the drain electrode and the second semiconductor layer.
The vertical gallium nitride transistor of claim 1, further comprising a support substrate, wherein a second surface of the drain electrode opposite to the first surface is disposed on the support substrate.
The vertical gallium nitride transistor of claim 1, further comprising a current blocking layer disposed between the drain electrode and the second semiconductor layer.
The vertical gallium nitride transistor of claim 1, wherein the first and second semiconductor layers comprise N-type gallium nitride; and wherein the third semiconductor layer comprises P-type gallium nitride.
The vertical gallium nitride transistor of claim 1, wherein: the third semiconductor layer comprises a plurality of third semiconductor layers; the first semiconductor layer comprises a plurality of first semiconductor layers, the plurality of first semiconductor layers comprising a stripe pattern and a lower first semiconductor layer covering sidewalls and a bottom surface of the strip pattern; [[and]] the source electrode comprises a plurality of source electrodes; each of the plurality of third semiconductor layers surround at least two of the first 3 Application No.: 14/177,825 Reply dated Response to Office Action of semiconductor layers; [[and]] each of the source electrodes is electrically connected to at least two of the first semiconductor layers; and the second semiconductor layer surrounds the sidewalls and a bottom surface of the lower first semiconductor layer.
The vertical gallium nitride transistor of claim [[6]] 1, further comprising current blocking layers disposed between the drain electrode and the second semiconductor layer, wherein the drain electrode contacts the second semiconductor layer, between each of the current blocking layers.
The vertical gallium nitride transistor of claim 7, further comprising a dopcd laycr a low resistive layer disposed between the drain electrode and the second semiconductor layer, the low resistive layer being an etch damage layer formed by etching a portion of the second semiconductor layer.
A vertical gallium nitride transistor, comprising: a drain electrode; a first semiconductor layer of a first conductivity type disposed on the drain electrode; an undoped second semiconductor layer disposed on the first semiconductor layer; a third semiconductor layer of a second conductivity type disposed on the second semiconductor layer; a source electrode disposed on the second semiconductor layer and spaced apart from the third semiconductor layer; 4 Application No.: 14/177,825 Reply dated Response to Office Action of an insulation layer disposed on the third semiconductor layer; a gate electrode disposed on the insulation layer; and a first blocking layer disposed between the first and second semiconductor layers, wherein the first blocking layer is disposed between the source electrode and the drain electrode, and is configured to block a vertical current path between the source electrode and the drain electrode. withdrawn
The vertical gallium nitride transistor of claim 9, further comprising a second blocking layer disposed between the drain electrode and the first semiconductor layer, wherein the second blocking layer is disposed between the blocking layer and the drain electrode. withdrawn
The vertical gallium nitride transistor of claim 9, wherein the first semiconductor layer comprises: a first gallium nitride layer doped with impurities of the first conductivity type at a first concentration; and a second gallium nitride layer doped with impurities of the first conductivity type at a second concentration that is lower than the first concentration, wherein the first gallium nitride layer and the second gallium nitride layer are sequentially disposed on the drain electrode. withdrawn
The vertical gallium nitride transistor of claim 9, wherein the second semiconductor layer comprises a depletion region that is configured to contact the blocking layer when no bias voltage is applied to the gate electrode; and wherein the depletion region is configured to be spaced apart from the blocking layer 5 Application No.: 14/177,825 Reply dated Response to Office Action of when a gate voltage greater than a threshold voltage is applied to the gate electrode. withdrawn
The vertical gallium nitride transistor of claim 9, further comprising: a vertical drain electrode vertically penetrating the second semiconductor layer and the first semiconductor layer, the vertical drain electrode having a first band gap energy; and a channel layer disposed in the first semiconductor layer, the channel layer being electrically connected to the vertical drain electrode, wherein the channel layer has a second band gap energy different from the first band gap energy, and the channel layer comprises gallium nitride. withdrawn
The vertical gallium nitride transistor of claim 9, further comprising a barrier layer disposed between the second and third semiconductor layers, wherein the barrier layer has a band gap energy different from a band gap energy of the second semiconductor layer, and wherein the barrier layer comprises aluminum gallium nitride. withdrawn
A vertical gallium nitride transistor, comprising: a substrate; a buffer layer disposed on the substrate; a mask pattern disposed on the buffer layer, the mask pattern exposing portions of the buffer layer; a gallium nitride layer disposed on the mask pattern and the exposed portions of the 6 Application No.: 14/177,825 Reply dated Response to Office Action of buffer layer; a first drift layer disposed on a portion of the gallium nitride layer; a current blocking pattern disposed on the first drift layer, the current blocking pattern exposing a portion of the first drift layer; a second drift layer disposed on the exposed portion of the first drift layer; a donor layer disposed on the current blocking pattern; a channel layer disposed on the current blocking pattern, the channel layer surrounding sidewalls of the donor layer; a gate electrode disposed on the second drift layer; a gate insulation layer disposed between, and configured to insulate, the gate electrode and the second drift layer; a source electrode disposed on the donor layer and electrically connected to the donor layer; and a drain electrode disposed on the gallium nitride layer and spaced apart from the first drift layer. withdrawn
The vertical gallium nitride transistor of claim 16, wherein the buffer layer comprises N-type gallium nitride; wherein the first drift layer, the second drift layer, and the donor layer comprise N-type gallium nitride having impurity concentrations that are lower than an impurity concentration of the buffer layer; and wherein the channel layer comprises P-type gallium nitride. withdrawn
The vertical gallium nitride transistor of claim 16, wherein the second drift layer disposed on the exposed portion of the first drift layer vertically overlaps with 7 Application No.: 14/177,825 Reply dated Response to Office Action of the mask pattern. withdrawn
The vertical gallium nitride transistor of claim 16, further comprising: a heterogeneous semiconductor layer disposed on the second drift layer, the heterogeneous semiconductor layer configured to form a two dimension electron gas (2DEG) layer at an interface with a first surface of the second drift layer, wherein the gate electrode is disposed on the heterogeneous semiconductor layer. withdrawn
The vertical gallium nitride transistor of claim heterogeneous semiconductor layer is disposed on the heterogeneous semiconductor layer is disposed portion of the heterogeneous semiconductor layer heterogeneous semiconductor layer. 8 withdrawn 19, wherein a first portion of the second drift layer and a second portion of on the channel layer, and wherein the first is thicker than the second portion of the
Layer stacks claimed or described, ordered top of device to substrate.
vertical gallium nitride transistor (claims 1-8)
Materials described outside the worked examples.
N-type gallium nitride
GaN
aluminum gallium nitride
AlGaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a cross-sectional view illustrating a vertical gallium nitride transistor according to an exemplary embodiment of the present invention. 20 [0024]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 7–9 µm | — |
Thickness | 18–1000 nm |
Table 1
ectric fields Emax according to various reverse bias voltages V b may be summarized as listed in the following table 1.
p. 9
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US 9,219,137Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view illustrating a vertical gallium nitride transistor according to an exemplary embodiment of the present invention. 20 [0024]
FIGS. 2 to 9 are cross-sectional views illustrating a method of fabricating the vertical gallium nitride transistor according to the exemplary embodiment of
FIG. 3). In such a case, the GaN layer may be formed to a thickness of about 1 micrometer to about 2 micrometers. Referring to
FIG. 4, additional semiconductor layers 25a of the first conductivity 20 type may be grown on respective stripe patterns 23a. The additional semiconductor …
FIG. 5, current blocking layers 31 may be formed on the second semiconductor layer 29. The current blocking layers 31 may be formed by depositing a silicon …
FIG. 6, a support substrate 41 may be attached to the second semiconductor layer 29. The support substrate 41 may be formed by depositing a metal layer 35 …
FIG. 7, the growth substrate 21 may be removed from the semiconductor layers 25, 27, and 29 including the stripe patterns 25a. The growth substrate 21 10 may …
FIG. 8, source electrodes 43 may be formed on the top surface of the semiconductor structure 20. The source electrodes 43 may be formed to be electrically …
FIG. 9 are cross- sectional views illustrating a method of fabricating the vertical gallium nitride transistor shown in
FIG. 10 is a cross-sectional view illustrating an off-state of a vertical gallium nitride transistor according to an exemplary embodiment of the present …
FIG. 11 is a cross-sectional view illustrating an on-state of the vertical gallium nitride transistor according to the exemplary embodiment of
FIGS. 12 to 27 are cross-sectional views illustrating a method of fabricating the vertical gallium nitride transistor according to an exemplary embodiment of …
FIG. 13, a GaN layer heavily doped with N-type impurities may be 10 grown on the seed layer 102 to form a first semiconductor layer 120. The first semiconductor …
FIG. 14, a GaN layer lightly doped with N-type impurities may be grown on the first semiconductor layer 120 to form a first semiconductor layer 125. That is, the …
FIG. 15, the blocking layers 135 may be formed on the 31 upper GaN layer 125 to face respective ones of the seed patterns 102. Each of the blocking layers 135 …
FIG. 16, the second semiconductor layer 140 may be formed of an undoped GaN layer. The second semiconductor layers 140 may be formed to cover edges of the …
FIG. 17, the third semiconductor layer 150 may be formed of a P- type GaN layer on entire surfaces of the blocking layers 135 and the second semiconductor …
FIG. 18, the insulation layer 155 may be formed on the 15 third semiconductor layer 150, for example, the P-type GaN layer. [0087] Refe rr ing to
FIGS. 19 to 24A, the step of forming the source electrodes 166 and the gate electrodes 160 may include a step of forming a metal layer 160 on the insulation …
FIG. 20, a step of patterning the insulation layer 155 and the 20 P-type GaN layer 150 to form openings that expose portions of the second semiconductor layer …
FIG. 21, a step of forming the source electrodes 166 composed of a metal layer in the openings as illustrated in
FIG. 22, and a step of forming a passivation layer 175 that fills spaces between the source electrodes 166 and the 32 gate electrodes 160 and covers the source …
FIG. 23, 24A, and
FIG. 24B are cross-sectional views illustrating a method of fabricating a vertical gallium nitride according to an exemplary embodiment of the present …
FIG. 25, the second substrate 109 may be attached to a surface of the passivation layer 175 opposite to the first substrate 101. Referring to
FIG. 26, the first substrate 101 may be detached from the first semiconductor layers 120 and 125. The first substrate 101 may be detached using a laser lift-off 5 …
FIG. 27. The additional blocking layers 115 may be formed of the same material as the blocking layers 135. Further, the additional blocking layers 115 may be …
FIG. 28 is a cross-sectional view illustrating an off-state of a vertical gallium 10 nitride transistor according to an exemplary embodiment of the present …
FIG. 29 is a cross-sectional view illustrating an on-state of the vertical gallium nitride transistor according to the exemplary embodiment of
FIG. 30 is a cross-sectional view illustrating an off-state of a vertical gallium nitride transistor according to an exemplary embodiment of the present …
FIG. 31 is a cross-sectional view illustrating an on-state of the vertical gallium nitride transistor according to the exemplary embodiment of
FIGS. 32 to 46 are cross-sectional views illustrating a method of fabricating the vertical gallium nitride transistor according to an exemplary embodiment of …
FIG. 33, a GaN layer heavily doped with N- type impurities may be grown on the seed patterns 302 to form the first semiconductor layer 320. [00103] Refe rr ing …
FIG. 34, a GaN layer lightly doped with N-type impurities 5 may be grown on the first semiconductor layer 320 to form the first semiconductor layer 325. That is, …
FIG. 35, the blocking layers 335 may be formed on the upper GaN layer 325 to face respective ones of the seed patterns 302. Each of the blocking layers 335 may …
FIG. 36, an undoped GaN layer may be grown using the first semiconductor layer 325 as a seed layer to form the second semiconductor layers 340. The 20 second …
FIG. 37. The insulation layer 355 may be formed on the third semiconductor layer 350, as illustrated in
FIG. 38. [00107] The step of forming the source electrodes 366 and the gate electrodes 360 may include a step of forming a metal layer 360 on the insulation …
FIG. 39, a step of patterning the metal layer 360 to form the gate electrodes 360 as illustrated in
FIG. 41, a step of forming the source electrodes 366 composed of a metal layer in the openings as illustrated in
FIG. 42, and a step of forming an insulation layer 375 that fills spaces between the source electrodes 366 and the gate electrodes 360 and covers the source …
FIG. 43. [00108] As illustrated in
FIG. 44, the second substrate 309 may be attached to a surface of the insulation layer 375 opposite to the first substrate 301. Referring to
FIG. 45, the first substrate 301 may be detached from the first semiconductor layer 320. After the first substrate 101 is removed, additional blocking layers 315 …
FIG. 46. The additional blocking layers 315 may be formed of the sane material as the blocking layers 335. Further, the additional blocking layers 115 may be …
FIG. 47 is a cross-sectional view illustrating a vertical gallium nitride transistor according to an exemplary embodiment of the present invention. [0035]
FIG. 48 is a cross-sectional view illustrating a vertical gallium nitride transistor according to an exemplary embodiment of the present invention. [0036]
FIGS. 49 to 60 are cross-sectional views illustrating a method of fabricating the vertical gallium nitride transistors shown in
FIG. 50, a GaN layer 1108 may be formed on the exposed portions of the buffer layer 1104. The GaN layer 1108 may be formed to have an N-type. In one exemplary …
FIG. 51, a first drift layer 1110 may be formed on the GaN layer 1108. The first drift layer 1110 may be formed of an N-type GaN layer. Portions of the GaN layer …
FIG. 52, second drift layers 1116 may be formed on respective ones of the exposed portions of the first drift layer 1110. The second drift layers 1116 may be …
FIG. 53, channel layers 1118 may be formed on respective ones of the second drift layers 1116. The channel layers 1118 may be formed of a P-type GaN layer. The …
FIG. 54, a donor layer 1120 may be formed on the current blocking patterns 1114 and the channel layers 1118. The donor layer 1120 may be formed of an N-type …
FIG. 55, the donor layer 1120 may be etched back or planarized until top surfaces of the second drift layers 1116 are exposed. As a result, a single donor …
FIG. 56, a gate insulation layer 1122 may be formed on top surfaces of the second drift layers 1116, the channel layers 1118 and the donor layers 1120. In one …
FIG. 57, resist patterns 1160 may be formed on the gate insulation layer 1122. The resist patterns 1160 may be formed to perform a subsequent lift-off process. …
FIG. 58, the resist patterns 1160 may be removed. The resist patterns 1160 may be removed using an ashing process. When the resist patterns 1160 are removed, …
FIG. 59, the insulation layer 1126, the gate insulation layer 1122 and the donor layers 1120 may be etched to form contact holes. A metal layer may then be …
FIG. 60, a portion of the resultant including the source electrodes 1128 may be removed to expose a portion of the GaN layer 1108. A portion of the resultant …
FIG. 61,
FIG. 62, and
FIG. 63 are cross-sectional views illustrating another method of fabricating the vertical gallium nitride transistor shown in
FIGS. 64 to 75 are cross-sectional views illustrating a method of fabricating the vertical gallium nitride transistor shown in
FIG. 65, a GaN layer 1208 may be formed on the exposed portions of the buffer layer 1204. The GaN layer 1208 may be formed to have an N-type. In one exemplary …
FIG. 66, a first drift layer 1210 may be formed on the 5 GaN layer 1208. The first drift layer 1210 may be formed of an N-type GaN layer. Portions of the GaN …
FIG. 67, second drift layers 1216 may be formed on respective ones 20 of the exposed portions of the first drift layer 1210. The second drift layers 1216 may be …
FIG. 68, channel layers 1218 may be formed on respective ones of the second drift layers 1216. The channel layers 1218 may be formed of a P-type GaN layer. 10 …
FIG. 69, a donor layer 1220 may be formed on the 15 current blocking patterns 1214 and the channel layers 1218. The donor layer 1220 may be formed of an N-type …
FIG. 70, the donor layer 1220 may be etched back or planarized until top surfaces of the second drift layers 1216 are exposed. As a result, a single donor …
FIG. 71, a heterogeneous semiconductor layer 1250 may be formed on the donor layers 1220, the channel layers 1218 and the second drift layer 1216. The 58 …
FIG. 72, a gate insulation layer 1222 may be formed on a top surface of the heterogeneous semiconductor layer 1250. In one exemplary embodiment, the gate …
FIG. 73, the resist patterns 1260 may be removed. The resist patterns 1260 may be removed using an ashing process. When the resist patterns 1260 are removed, …
FIG. 74, an insulation layer 1226 may be formed on the 10 gate electrodes 1224 and the gate insulation layer 1222. Subsequently, the insulation layer 1226, the …
FIG. 75, a portion of the resultant including the source electrodes 1228 may be removed to expose a portion of the GaN layer 1208. The portion of the resultant …
FIG. 76,
FIG. 77, and
FIG. 78 are cross-sectional views illustrating another method of fabricating a vertical gallium nitride transistor shown in
FIGS. 79 to 92 are cross-sectional views illustrating a method of fabricating a 10 vertical gallium nitride transistor according to an exemplary embodiment of …
FIG. 80, second GaN layers 2108 may be grown on respective ones of the exposed portions of the first GaN layer 2104. In one exemplary embodiment, the 15 second …
FIG. 81, third GaN layers 2110 may be grown on respective ones of the second GaN layers 2108. The third GaN layers 2110 may act as channel modulation layers …
FIG. 82, current blocking patterns 2114 may formed on the fourth GaN layer 2112. In one exemplary embodiment, the current blocking patterns 2114 may be formed …
FIG. 83, a fifth GaN layer 2116 may be formed to cover the 63 current blocking patterns 2114 and the fourth GaN layer 2112. The fifth GaN layer 2116 may be …
FIG. 84, a drain electrode layer 2120 may be formed on the sixth GaN layer 2118. The drain electrode layer 2120 may be formed of a metal layer. Subsequently, a …
FIG. 85. Subsequently, the first GaN layer 2104 may be removed. The first GaN layer 2104 may be removed using an anisotropic etch process, for example, a …
FIG. 86, the mask patterns 2106 may be removed to form recessed regions 2125. In the event that the mask patterns 2106 are formed of a silicon oxide layer, the …
FIG. 87, a gate insulation layer 2127 may be formed on the second GaN layers 2108 including the recessed regions 2125. Subsequently, etch mask patterns 2130 …
FIG. 88, the gate insulation layer 2127 and the 20 second GaN layers 2108 may be etched using the etch mask patterns 2130 as etch masks. As a result, gate …
FIG. 89, lift-off mask patterns 2132 may be formed on the gate insulation patterns 2128. In one exemplary embodiment, the lift-off mask patterns 2132 may be 10 …
FIG. 90, a metal layer may be formed on a surface of the substrate including the lift-off mask patterns 2132. The metal layer may be deposited to a thickness …
FIG. 91, the lift-off mask patterns 2132 may be removed. In the event that the lift-off mask patterns 2132 are formed of a photoresist layer, the lift-off mask …
FIG. 92, if the vertical GaN transistor is turned on, carriers may be vertically 15 drifted through first regions (indicated by a reference character "B") in …
FIG. 8079 a sacrificial layer 2104, for example, a first GaN layer, may be formed on a first substrate 2102. The first substrate 2102 may act as a substrate for …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A vertical gallium nitride transistor, comprising: a first semiconductor layer of a first conductivity type comprising a first surface, a second surface opposite to the first surface, and sidewalls; a second semiconductor layer of the first conductivity type surrounding the second surface and the sidewalls of the first semiconductor layer; a third semiconductor layer of a second conductivity type disposed between the first semiconductor layer and the second semiconductor layer, the third semiconductor layer separating the first and second semiconductor layers from each other; a source electrode disposed on the first surface of the first semiconductor layer, the source electrode being electrically connected to the first semiconductor layer; a gate electrode disposed on a first surface of the third semiconductor layer between the first and second semiconductor layers; [[and]] a drain electrode, wherein the second semiconductor layer is disposed on a first surface of the drain electrode; and a current blocking layer disposed between the drain electrode and the second semiconductor layer, the current blocking layer comprising a lower surface in direct contact with the drain electrode and an upper surface that is in direct contact with the second semiconductor layer, wherein the first semiconductor layer, the third semiconductor layer, and the second 2 Application No.: 14/177,825 Reply dated Response to Office Action of semiconductor layer comprise a semiconductor structure.
The vertical gallium nitride transistor of claim 1, wherein the semiconductor structure further comprises a doped layer disposed between the drain electrode and the second semiconductor layer.
The vertical gallium nitride transistor of claim 1, further comprising a support substrate, wherein a second surface of the drain electrode opposite to the first surface is disposed on the support substrate.
The vertical gallium nitride transistor of claim 1, further comprising a current blocking layer disposed between the drain electrode and the second semiconductor layer.
The vertical gallium nitride transistor of claim 1, wherein the first and second semiconductor layers comprise N-type gallium nitride; and wherein the third semiconductor layer comprises P-type gallium nitride.
The vertical gallium nitride transistor of claim 1, wherein: the third semiconductor layer comprises a plurality of third semiconductor layers; the first semiconductor layer comprises a plurality of first semiconductor layers, the plurality of first semiconductor layers comprising a stripe pattern and a lower first semiconductor layer covering sidewalls and a bottom surface of the strip pattern; [[and]] the source electrode comprises a plurality of source electrodes; each of the plurality of third semiconductor layers surround at least two of the first 3 Application No.: 14/177,825 Reply dated Response to Office Action of semiconductor layers; [[and]] each of the source electrodes is electrically connected to at least two of the first semiconductor layers; and the second semiconductor layer surrounds the sidewalls and a bottom surface of the lower first semiconductor layer.
The vertical gallium nitride transistor of claim [[6]] 1, further comprising current blocking layers disposed between the drain electrode and the second semiconductor layer, wherein the drain electrode contacts the second semiconductor layer, between each of the current blocking layers.
The vertical gallium nitride transistor of claim 7, further comprising a dopcd laycr a low resistive layer disposed between the drain electrode and the second semiconductor layer, the low resistive layer being an etch damage layer formed by etching a portion of the second semiconductor layer.
A vertical gallium nitride transistor, comprising: a drain electrode; a first semiconductor layer of a first conductivity type disposed on the drain electrode; an undoped second semiconductor layer disposed on the first semiconductor layer; a third semiconductor layer of a second conductivity type disposed on the second semiconductor layer; a source electrode disposed on the second semiconductor layer and spaced apart from the third semiconductor layer; 4 Application No.: 14/177,825 Reply dated Response to Office Action of an insulation layer disposed on the third semiconductor layer; a gate electrode disposed on the insulation layer; and a first blocking layer disposed between the first and second semiconductor layers, wherein the first blocking layer is disposed between the source electrode and the drain electrode, and is configured to block a vertical current path between the source electrode and the drain electrode. withdrawn
The vertical gallium nitride transistor of claim 9, further comprising a second blocking layer disposed between the drain electrode and the first semiconductor layer, wherein the second blocking layer is disposed between the blocking layer and the drain electrode. withdrawn
The vertical gallium nitride transistor of claim 9, wherein the first semiconductor layer comprises: a first gallium nitride layer doped with impurities of the first conductivity type at a first concentration; and a second gallium nitride layer doped with impurities of the first conductivity type at a second concentration that is lower than the first concentration, wherein the first gallium nitride layer and the second gallium nitride layer are sequentially disposed on the drain electrode. withdrawn
The vertical gallium nitride transistor of claim 9, wherein the second semiconductor layer comprises a depletion region that is configured to contact the blocking layer when no bias voltage is applied to the gate electrode; and wherein the depletion region is configured to be spaced apart from the blocking layer 5 Application No.: 14/177,825 Reply dated Response to Office Action of when a gate voltage greater than a threshold voltage is applied to the gate electrode. withdrawn
The vertical gallium nitride transistor of claim 9, further comprising: a vertical drain electrode vertically penetrating the second semiconductor layer and the first semiconductor layer, the vertical drain electrode having a first band gap energy; and a channel layer disposed in the first semiconductor layer, the channel layer being electrically connected to the vertical drain electrode, wherein the channel layer has a second band gap energy different from the first band gap energy, and the channel layer comprises gallium nitride. withdrawn
The vertical gallium nitride transistor of claim 9, further comprising a barrier layer disposed between the second and third semiconductor layers, wherein the barrier layer has a band gap energy different from a band gap energy of the second semiconductor layer, and wherein the barrier layer comprises aluminum gallium nitride. withdrawn
A vertical gallium nitride transistor, comprising: a substrate; a buffer layer disposed on the substrate; a mask pattern disposed on the buffer layer, the mask pattern exposing portions of the buffer layer; a gallium nitride layer disposed on the mask pattern and the exposed portions of the 6 Application No.: 14/177,825 Reply dated Response to Office Action of buffer layer; a first drift layer disposed on a portion of the gallium nitride layer; a current blocking pattern disposed on the first drift layer, the current blocking pattern exposing a portion of the first drift layer; a second drift layer disposed on the exposed portion of the first drift layer; a donor layer disposed on the current blocking pattern; a channel layer disposed on the current blocking pattern, the channel layer surrounding sidewalls of the donor layer; a gate electrode disposed on the second drift layer; a gate insulation layer disposed between, and configured to insulate, the gate electrode and the second drift layer; a source electrode disposed on the donor layer and electrically connected to the donor layer; and a drain electrode disposed on the gallium nitride layer and spaced apart from the first drift layer. withdrawn
The vertical gallium nitride transistor of claim 16, wherein the buffer layer comprises N-type gallium nitride; wherein the first drift layer, the second drift layer, and the donor layer comprise N-type gallium nitride having impurity concentrations that are lower than an impurity concentration of the buffer layer; and wherein the channel layer comprises P-type gallium nitride. withdrawn
The vertical gallium nitride transistor of claim 16, wherein the second drift layer disposed on the exposed portion of the first drift layer vertically overlaps with 7 Application No.: 14/177,825 Reply dated Response to Office Action of the mask pattern. withdrawn
The vertical gallium nitride transistor of claim 16, further comprising: a heterogeneous semiconductor layer disposed on the second drift layer, the heterogeneous semiconductor layer configured to form a two dimension electron gas (2DEG) layer at an interface with a first surface of the second drift layer, wherein the gate electrode is disposed on the heterogeneous semiconductor layer. withdrawn
The vertical gallium nitride transistor of claim heterogeneous semiconductor layer is disposed on the heterogeneous semiconductor layer is disposed portion of the heterogeneous semiconductor layer heterogeneous semiconductor layer. 8 withdrawn 19, wherein a first portion of the second drift layer and a second portion of on the channel layer, and wherein the first is thicker than the second portion of the
Layer stacks claimed or described, ordered top of device to substrate.
vertical gallium nitride transistor (claims 1-8)
Materials described outside the worked examples.
N-type gallium nitride
GaN
aluminum gallium nitride
AlGaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a cross-sectional view illustrating a vertical gallium nitride transistor according to an exemplary embodiment of the present invention. 20 [0024]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 7–9 µm | — |
Thickness | 18–1000 nm |
Table 1
ectric fields Emax according to various reverse bias voltages V b may be summarized as listed in the following table 1.
p. 9
Related documents with shared materials, methods, properties, or citations.
vertical gallium nitride transistor (claims 9-15)
vertical gallium nitride transistor (claims 16-22)
FIGS. 2 to 9 are cross-sectional views illustrating a method of fabricating the vertical gallium nitride transistor according to the exemplary embodiment of
FIG. 3). In such a case, the GaN layer may be formed to a thickness of about 1 micrometer to about 2 micrometers. Referring to
FIG. 8, source electrodes 43 may be formed on the top surface of the semiconductor structure 20. The source electrodes 43 may be formed to be electrically …
FIG. 9 are cross- sectional views illustrating a method of fabricating the vertical gallium nitride transistor shown in
FIG. 10 is a cross-sectional view illustrating an off-state of a vertical gallium nitride transistor according to an exemplary embodiment of the present …
FIG. 11 is a cross-sectional view illustrating an on-state of the vertical gallium nitride transistor according to the exemplary embodiment of
FIGS. 12 to 27 are cross-sectional views illustrating a method of fabricating the vertical gallium nitride transistor according to an exemplary embodiment of …
FIG. 28 is a cross-sectional view illustrating an off-state of a vertical gallium 10 nitride transistor according to an exemplary embodiment of the present …
FIG. 29 is a cross-sectional view illustrating an on-state of the vertical gallium nitride transistor according to the exemplary embodiment of
FIG. 30 is a cross-sectional view illustrating an off-state of a vertical gallium nitride transistor according to an exemplary embodiment of the present …
FIG. 31 is a cross-sectional view illustrating an on-state of the vertical gallium nitride transistor according to the exemplary embodiment of
FIGS. 32 to 46 are cross-sectional views illustrating a method of fabricating the vertical gallium nitride transistor according to an exemplary embodiment of …
FIG. 47 is a cross-sectional view illustrating a vertical gallium nitride transistor according to an exemplary embodiment of the present invention. [0035]
FIG. 48 is a cross-sectional view illustrating a vertical gallium nitride transistor according to an exemplary embodiment of the present invention. [0036]
FIGS. 49 to 60 are cross-sectional views illustrating a method of fabricating the vertical gallium nitride transistors shown in
FIG. 54, a donor layer 1120 may be formed on the current blocking patterns 1114 and the channel layers 1118. The donor layer 1120 may be formed of an N-type …
FIG. 63 are cross-sectional views illustrating another method of fabricating the vertical gallium nitride transistor shown in
FIGS. 64 to 75 are cross-sectional views illustrating a method of fabricating the vertical gallium nitride transistor shown in
FIG. 69, a donor layer 1220 may be formed on the 15 current blocking patterns 1214 and the channel layers 1218. The donor layer 1220 may be formed of an N-type …
FIG. 78 are cross-sectional views illustrating another method of fabricating a vertical gallium nitride transistor shown in
FIGS. 79 to 92 are cross-sectional views illustrating a method of fabricating a 10 vertical gallium nitride transistor according to an exemplary embodiment of …
FIG. 90, a metal layer may be formed on a surface of the substrate including the lift-off mask patterns 2132. The metal layer may be deposited to a thickness …
FIG. 92, if the vertical GaN transistor is turned on, carriers may be vertically 15 drifted through first regions (indicated by a reference character "B") in …
| — |
Thickness | 5–10 µm | — |
Thickness | 100–500 µm | — |
Thickness | 15–20 µm | — |
Thickness | 0.2–1 µm | — |
Thickness | 1–2 µm | — |
Thickness | 10–100 nm | — |
Thickness | 2–20 µm | — |
Thickness | ≥ 9 µm | — |
vertical gallium nitride transistor (claims 9-15)
vertical gallium nitride transistor (claims 16-22)
FIGS. 2 to 9 are cross-sectional views illustrating a method of fabricating the vertical gallium nitride transistor according to the exemplary embodiment of
FIG. 3). In such a case, the GaN layer may be formed to a thickness of about 1 micrometer to about 2 micrometers. Referring to
FIG. 8, source electrodes 43 may be formed on the top surface of the semiconductor structure 20. The source electrodes 43 may be formed to be electrically …
FIG. 9 are cross- sectional views illustrating a method of fabricating the vertical gallium nitride transistor shown in
FIG. 10 is a cross-sectional view illustrating an off-state of a vertical gallium nitride transistor according to an exemplary embodiment of the present …
FIG. 11 is a cross-sectional view illustrating an on-state of the vertical gallium nitride transistor according to the exemplary embodiment of
FIGS. 12 to 27 are cross-sectional views illustrating a method of fabricating the vertical gallium nitride transistor according to an exemplary embodiment of …
FIG. 28 is a cross-sectional view illustrating an off-state of a vertical gallium 10 nitride transistor according to an exemplary embodiment of the present …
FIG. 29 is a cross-sectional view illustrating an on-state of the vertical gallium nitride transistor according to the exemplary embodiment of
FIG. 30 is a cross-sectional view illustrating an off-state of a vertical gallium nitride transistor according to an exemplary embodiment of the present …
FIG. 31 is a cross-sectional view illustrating an on-state of the vertical gallium nitride transistor according to the exemplary embodiment of
FIGS. 32 to 46 are cross-sectional views illustrating a method of fabricating the vertical gallium nitride transistor according to an exemplary embodiment of …
FIG. 47 is a cross-sectional view illustrating a vertical gallium nitride transistor according to an exemplary embodiment of the present invention. [0035]
FIG. 48 is a cross-sectional view illustrating a vertical gallium nitride transistor according to an exemplary embodiment of the present invention. [0036]
FIGS. 49 to 60 are cross-sectional views illustrating a method of fabricating the vertical gallium nitride transistors shown in
FIG. 54, a donor layer 1120 may be formed on the current blocking patterns 1114 and the channel layers 1118. The donor layer 1120 may be formed of an N-type …
FIG. 63 are cross-sectional views illustrating another method of fabricating the vertical gallium nitride transistor shown in
FIGS. 64 to 75 are cross-sectional views illustrating a method of fabricating the vertical gallium nitride transistor shown in
FIG. 69, a donor layer 1220 may be formed on the 15 current blocking patterns 1214 and the channel layers 1218. The donor layer 1220 may be formed of an N-type …
FIG. 78 are cross-sectional views illustrating another method of fabricating a vertical gallium nitride transistor shown in
FIGS. 79 to 92 are cross-sectional views illustrating a method of fabricating a 10 vertical gallium nitride transistor according to an exemplary embodiment of …
FIG. 90, a metal layer may be formed on a surface of the substrate including the lift-off mask patterns 2132. The metal layer may be deposited to a thickness …
FIG. 92, if the vertical GaN transistor is turned on, carriers may be vertically 15 drifted through first regions (indicated by a reference character "B") in …
| — |
Thickness | 5–10 µm | — |
Thickness | 100–500 µm | — |
Thickness | 15–20 µm | — |
Thickness | 0.2–1 µm | — |
Thickness | 1–2 µm | — |
Thickness | 10–100 nm | — |
Thickness | 2–20 µm | — |
Thickness | ≥ 9 µm | — |
vertical gallium nitride transistor (claims 9-15)
vertical gallium nitride transistor (claims 16-22)
FIGS. 2 to 9 are cross-sectional views illustrating a method of fabricating the vertical gallium nitride transistor according to the exemplary embodiment of
FIG. 3). In such a case, the GaN layer may be formed to a thickness of about 1 micrometer to about 2 micrometers. Referring to
FIG. 8, source electrodes 43 may be formed on the top surface of the semiconductor structure 20. The source electrodes 43 may be formed to be electrically …
FIG. 9 are cross- sectional views illustrating a method of fabricating the vertical gallium nitride transistor shown in
FIG. 10 is a cross-sectional view illustrating an off-state of a vertical gallium nitride transistor according to an exemplary embodiment of the present …
FIG. 11 is a cross-sectional view illustrating an on-state of the vertical gallium nitride transistor according to the exemplary embodiment of
FIGS. 12 to 27 are cross-sectional views illustrating a method of fabricating the vertical gallium nitride transistor according to an exemplary embodiment of …
FIG. 28 is a cross-sectional view illustrating an off-state of a vertical gallium 10 nitride transistor according to an exemplary embodiment of the present …
FIG. 29 is a cross-sectional view illustrating an on-state of the vertical gallium nitride transistor according to the exemplary embodiment of
FIG. 30 is a cross-sectional view illustrating an off-state of a vertical gallium nitride transistor according to an exemplary embodiment of the present …
FIG. 31 is a cross-sectional view illustrating an on-state of the vertical gallium nitride transistor according to the exemplary embodiment of
FIGS. 32 to 46 are cross-sectional views illustrating a method of fabricating the vertical gallium nitride transistor according to an exemplary embodiment of …
FIG. 47 is a cross-sectional view illustrating a vertical gallium nitride transistor according to an exemplary embodiment of the present invention. [0035]
FIG. 48 is a cross-sectional view illustrating a vertical gallium nitride transistor according to an exemplary embodiment of the present invention. [0036]
FIGS. 49 to 60 are cross-sectional views illustrating a method of fabricating the vertical gallium nitride transistors shown in
FIG. 54, a donor layer 1120 may be formed on the current blocking patterns 1114 and the channel layers 1118. The donor layer 1120 may be formed of an N-type …
FIG. 63 are cross-sectional views illustrating another method of fabricating the vertical gallium nitride transistor shown in
FIGS. 64 to 75 are cross-sectional views illustrating a method of fabricating the vertical gallium nitride transistor shown in
FIG. 69, a donor layer 1220 may be formed on the 15 current blocking patterns 1214 and the channel layers 1218. The donor layer 1220 may be formed of an N-type …
FIG. 78 are cross-sectional views illustrating another method of fabricating a vertical gallium nitride transistor shown in
FIGS. 79 to 92 are cross-sectional views illustrating a method of fabricating a 10 vertical gallium nitride transistor according to an exemplary embodiment of …
FIG. 90, a metal layer may be formed on a surface of the substrate including the lift-off mask patterns 2132. The metal layer may be deposited to a thickness …
FIG. 92, if the vertical GaN transistor is turned on, carriers may be vertically 15 drifted through first regions (indicated by a reference character "B") in …
| — |
Thickness | 5–10 µm | — |
Thickness | 100–500 µm | — |
Thickness | 15–20 µm | — |
Thickness | 0.2–1 µm | — |
Thickness | 1–2 µm | — |
Thickness | 10–100 nm | — |
Thickness | 2–20 µm | — |
Thickness | ≥ 9 µm | — |
vertical gallium nitride transistor (claims 9-15)
vertical gallium nitride transistor (claims 16-22)
FIGS. 2 to 9 are cross-sectional views illustrating a method of fabricating the vertical gallium nitride transistor according to the exemplary embodiment of
FIG. 3). In such a case, the GaN layer may be formed to a thickness of about 1 micrometer to about 2 micrometers. Referring to
FIG. 8, source electrodes 43 may be formed on the top surface of the semiconductor structure 20. The source electrodes 43 may be formed to be electrically …
FIG. 9 are cross- sectional views illustrating a method of fabricating the vertical gallium nitride transistor shown in
FIG. 10 is a cross-sectional view illustrating an off-state of a vertical gallium nitride transistor according to an exemplary embodiment of the present …
FIG. 11 is a cross-sectional view illustrating an on-state of the vertical gallium nitride transistor according to the exemplary embodiment of
FIGS. 12 to 27 are cross-sectional views illustrating a method of fabricating the vertical gallium nitride transistor according to an exemplary embodiment of …
FIG. 28 is a cross-sectional view illustrating an off-state of a vertical gallium 10 nitride transistor according to an exemplary embodiment of the present …
FIG. 29 is a cross-sectional view illustrating an on-state of the vertical gallium nitride transistor according to the exemplary embodiment of
FIG. 30 is a cross-sectional view illustrating an off-state of a vertical gallium nitride transistor according to an exemplary embodiment of the present …
FIG. 31 is a cross-sectional view illustrating an on-state of the vertical gallium nitride transistor according to the exemplary embodiment of
FIGS. 32 to 46 are cross-sectional views illustrating a method of fabricating the vertical gallium nitride transistor according to an exemplary embodiment of …
FIG. 47 is a cross-sectional view illustrating a vertical gallium nitride transistor according to an exemplary embodiment of the present invention. [0035]
FIG. 48 is a cross-sectional view illustrating a vertical gallium nitride transistor according to an exemplary embodiment of the present invention. [0036]
FIGS. 49 to 60 are cross-sectional views illustrating a method of fabricating the vertical gallium nitride transistors shown in
FIG. 54, a donor layer 1120 may be formed on the current blocking patterns 1114 and the channel layers 1118. The donor layer 1120 may be formed of an N-type …
FIG. 63 are cross-sectional views illustrating another method of fabricating the vertical gallium nitride transistor shown in
FIGS. 64 to 75 are cross-sectional views illustrating a method of fabricating the vertical gallium nitride transistor shown in
FIG. 69, a donor layer 1220 may be formed on the 15 current blocking patterns 1214 and the channel layers 1218. The donor layer 1220 may be formed of an N-type …
FIG. 78 are cross-sectional views illustrating another method of fabricating a vertical gallium nitride transistor shown in
FIGS. 79 to 92 are cross-sectional views illustrating a method of fabricating a 10 vertical gallium nitride transistor according to an exemplary embodiment of …
FIG. 90, a metal layer may be formed on a surface of the substrate including the lift-off mask patterns 2132. The metal layer may be deposited to a thickness …
FIG. 92, if the vertical GaN transistor is turned on, carriers may be vertically 15 drifted through first regions (indicated by a reference character "B") in …
| — |
Thickness | 5–10 µm | — |
Thickness | 100–500 µm | — |
Thickness | 15–20 µm | — |
Thickness | 0.2–1 µm | — |
Thickness | 1–2 µm | — |
Thickness | 10–100 nm | — |
Thickness | 2–20 µm | — |
Thickness | ≥ 9 µm | — |