Patent
US 10,290,808METHODS OF GRAPHENE GROWTH AND RELATED STRUCTURES
Miin-Jang CHEN
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 10,290,808Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view of a back-gated graphene device; [0006]
FIG. 2 is a flow chart of a method of fabricating a graphene device according to one or more aspects of the present disclosure; [0007]
FIGS. 3, 4, 5, 6, 7, and 8 illustrate cross sectional views of embodiments of a graphene device according to one or more aspects of the present disclosure and …
FIGS. 4A, 4 B, and 4C illustrate chemical structures of precursors used to form silane-containing self-assembled monolayers (SAMs), according to one or more …
FIG. 5, and in an embodiment of block 206, a metal layer 502 is formed over the carbon-containing layer 402 (e.g., the SAM). In various embodiments, the metal …
FIG. 6, and as a result of the anneal process, the graphene layer 602 is formed between the metal layer 502 (e.g., the catalytic metal) and the insulating …
FIG. 7, the graphene layer 602 has been directly formed on the insulating layer 304 using a transfer-free process. After removal of the metal layer 502, and in …
FIG. 8 includes a back-gated graphene device, where the directly formed, transfer-free graphene layer 602 is contacted by source/drain electrodes 802, and the …
FIG. 9 is a cross-sectional view of a dual-gated graphene device according to one or more aspects of the present disclosure; [0010]
FIG. 10 is a cross-sectional view of a top-gated graphene device according to one or more aspects of the present disclosure; [0011]
FIG. 11 is a flow chart of a method of fabricating a carbon nanotube (CNT) according to one or more aspects of the present disclosure; [0012]
FIGS. 12, 13, 14, 15, 16, and 17 illustrate cross sectional views of embodiments of the CNT according to one or more aspects of the present disclosure and …
FIG. 13. Generally, after nanorod formation and in some embodiments, an insulating layer (e.g., an oxide layer) may be formed over the surface of the nanorod …
FIG. 14, and in an embodiment of block 1104, a carbon-containing layer 1402 is formed over the insulating surface 1302 of the nanorod 1204, thereby providing a …
FIG. 15, and in an embodiment of block 1106, a metal layer 1502 is formed over the carbon-containing layer 1402 (e.g., the SAM). In various embodiments, the …
FIGS. 16 and 17, and in an embodiment of block 1110, the metal layer 1502 may be removed. In various embodiments, and depending on the material used for the …
FIG. 17, the CNT 1602 has been directly formed on the insulating surface 1302 of the nanorod 1204 using a transfer-free process. After removal of the metal …
FIG. 18 is a cross-sectional view of a back-gated CNT transistor according to one or more aspects of the present disclosure; [0014]
FIG. 19 is a cross-sectional view of a dual-gated CNT transistor according to one or more aspects of the present disclosure; [0015]
FIG. 20. DETAILED
FIGS. 21, 22, 23, 24, 25, 26, 27, and 28 illustrate cross sectional views of embodiments of the curved graphene transistor according to one or more aspects of …
FIG. 22, and in an additional embodiment of block 2002, a device 2200 including a substrate 2102 having a curved region 2205 may be provided, where the curved …
FIG. 23, and in an embodiment of block 2004, a carbon-containing layer 2302 is formed over the insulating layer 2104, thereby providing a carbon source for …
FIG. 24, and in an embodiment of block 2006, a metal layer 2402 is formed over the carbon-containing layer 2302 (e.g., the SAM). As described above, and in …
FIGS. 25 and 26, and in an embodiment of block 2010, the metal layer 2402 may be removed. In various embodiments, and depending on the material used for the …
FIG. 26, illustrated therein is the curved (e.g., concave) region 2105 and regions 2605 adjacent to and on either side of the curved region 2105. In some …
FIG. 27, after performing the thermal treatment in the reducing atmosphere and in an embodiment of block 2012, source/drain electrodes 2702 and a gate …
FIG. 28, and in an additional embodiment of block 2012, electrodes may be formed on the device 2200 including the curved convex region 2205. [0063] The device …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method, comprising: providing a substrate including a nanorod extending therefrom, wherein the nanorod includes an insulating outer surface that traverses a circumference of the nanorod; forming, by a vapor phase deposition process, a carbon-containing layer over the insulating outer surface; depositing a metal layer over the carbon-containing layer; and after depositing the metal layer, performing an annealing process, wherein the annealing process serves to convert the carbon-containing layer into a carbon nanotube (CNT). Original
The method of claim 1, wherein the CNT includes one of a single- wall CNT (SW-CNT), a double-wall CNT (DW-CNT), and a multi-wall CNT (MW-CNT). Original
The method of claim 1, wherein the nanorod includes a first diameter, and wherein the CNT includes a second diameter substantially equal to the first diameter. Original
The method of claim 1, wherein the vapor phase deposition process includes one of an atomic layer deposition (ALD) process and a molecular layer deposition (MLD) process. Original
The method of claim 1, wherein the carbon-containing layer includes a self-assembled monolayer (SAM). Original
The method of claim 1, wherein the metal layer includes one of Ni, Cu, Pt, Fe, Co, Au, and a Cu-Ni alloy. Original
The method of claim 1, further comprising: after performing the annealing process, removing the metal layer and performing a thermal treatment in a reducing atmosphere; and after performing the thermal treatment, forming source and drain electrodes in contact with the CNT; after forming the source and drain electrodes, depositing a top-gate dielectric layer over the CNT; and forming a top-gate electrode on the top-gate dielectric. Original
The method of claim 1, wherein a CNT band gap is determined at least in part by the first diameter. Original
The method of claim 1, further comprising: prior to forming the carbon-containing layer, cleaning the insulating outer surface of the nanorod. Original
A method, comprising: forming a plurality of nanorods extending from a substrate; depositing an oxide layer over an outer surface of each of the plurality of nanorods; forming a carbon-containing layer, the carbon-containing layer including a self-assembled monolayer (SAM), conformally over the oxide layer; depositing a metal layer over the SAM; and Serial No.: 15/925,195 Attorney Docket No. 20150929/24061.3218US02 Response to Restriction Requirement mailed 09/05/2018 Customer No.: 42717 after depositing the metal layer, performing an annealing process to convert the SAM into a carbon nanotube (CNT). Original
The method of claim 12, wherein each of the plurality of nanorods have a first diameter, wherein each of the plurality of nanorods including the oxide layer have a second diameter greater than the first diameter, and wherein the CNT includes a third diameter substantially equal to the second diameter. Original
The method of claim 12, wherein the SAM includes one of tridecafluoro-tetrahydrooctyl-trichlorosilane (FOTS) and dodecyltrichlorosilane (DT S). Original
The method of claim 12, further comprising: after performing the annealing process, etching the metal layer and thermally treating the CNT. Original
17-20. Canceled
Canceled
A method, comprising: providing a first substrate including a nanowire extending therefrom; forming a self-assembled monolayer (SAM) over an outer surface of the nanowire; depositing a metal layer over the SAM; after depositing the metal layer, performing a pyrolysis process to convert the SAM into a carbon nanotube (CNT); transferring the CNT onto an insulating surface of a second substrate; and Serial No.: 15/925,195 Attorney Docket No. 20150929/24061.3218US02 Response to Restriction Requirement mailed 09/05/2018 Customer No.: 42717 forming source and drain electrodes in contact with the CNT, depositing a top-gate dielectric layer over the CNT, and forming a top-gate electrode on the top-gate dielectric. New
The method of claim 21, wherein the outer surface of the nanowire includes an insulating outer surface that traverses a circumference of the nanowire. New
The method of claim 21, wherein the CNT includes one of a single- wall CNT (SW-CNT), a double-wall CNT (DW-CNT), and a multi-wall CNT (MW-CNT). New
The method of claim 21, wherein the SAM includes one of tridecafluoro-tetrahydrooctyl-trichlorosilane (FOTS), and dodecyltrichlorosilane (DT S). New
Layer stacks claimed or described, ordered top of device to substrate.
CNT on nanorod
top-gate CNT field-effect transistor
Materials described outside the worked examples.
carbon nanotube (CNT)
carbon-containing layer/self-assembled monolayer (SAM)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a cross-sectional view of a back-gated graphene device; [0006]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 90–100 nm | — |
Thickness | 280–300 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,290,808Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view of a back-gated graphene device; [0006]
FIG. 2 is a flow chart of a method of fabricating a graphene device according to one or more aspects of the present disclosure; [0007]
FIGS. 3, 4, 5, 6, 7, and 8 illustrate cross sectional views of embodiments of a graphene device according to one or more aspects of the present disclosure and …
FIGS. 4A, 4 B, and 4C illustrate chemical structures of precursors used to form silane-containing self-assembled monolayers (SAMs), according to one or more …
FIG. 5, and in an embodiment of block 206, a metal layer 502 is formed over the carbon-containing layer 402 (e.g., the SAM). In various embodiments, the metal …
FIG. 6, and as a result of the anneal process, the graphene layer 602 is formed between the metal layer 502 (e.g., the catalytic metal) and the insulating …
FIG. 7, the graphene layer 602 has been directly formed on the insulating layer 304 using a transfer-free process. After removal of the metal layer 502, and in …
FIG. 8 includes a back-gated graphene device, where the directly formed, transfer-free graphene layer 602 is contacted by source/drain electrodes 802, and the …
FIG. 9 is a cross-sectional view of a dual-gated graphene device according to one or more aspects of the present disclosure; [0010]
FIG. 10 is a cross-sectional view of a top-gated graphene device according to one or more aspects of the present disclosure; [0011]
FIG. 11 is a flow chart of a method of fabricating a carbon nanotube (CNT) according to one or more aspects of the present disclosure; [0012]
FIGS. 12, 13, 14, 15, 16, and 17 illustrate cross sectional views of embodiments of the CNT according to one or more aspects of the present disclosure and …
FIG. 13. Generally, after nanorod formation and in some embodiments, an insulating layer (e.g., an oxide layer) may be formed over the surface of the nanorod …
FIG. 14, and in an embodiment of block 1104, a carbon-containing layer 1402 is formed over the insulating surface 1302 of the nanorod 1204, thereby providing a …
FIG. 15, and in an embodiment of block 1106, a metal layer 1502 is formed over the carbon-containing layer 1402 (e.g., the SAM). In various embodiments, the …
FIGS. 16 and 17, and in an embodiment of block 1110, the metal layer 1502 may be removed. In various embodiments, and depending on the material used for the …
FIG. 17, the CNT 1602 has been directly formed on the insulating surface 1302 of the nanorod 1204 using a transfer-free process. After removal of the metal …
FIG. 18 is a cross-sectional view of a back-gated CNT transistor according to one or more aspects of the present disclosure; [0014]
FIG. 19 is a cross-sectional view of a dual-gated CNT transistor according to one or more aspects of the present disclosure; [0015]
FIG. 20. DETAILED
FIGS. 21, 22, 23, 24, 25, 26, 27, and 28 illustrate cross sectional views of embodiments of the curved graphene transistor according to one or more aspects of …
FIG. 22, and in an additional embodiment of block 2002, a device 2200 including a substrate 2102 having a curved region 2205 may be provided, where the curved …
FIG. 23, and in an embodiment of block 2004, a carbon-containing layer 2302 is formed over the insulating layer 2104, thereby providing a carbon source for …
FIG. 24, and in an embodiment of block 2006, a metal layer 2402 is formed over the carbon-containing layer 2302 (e.g., the SAM). As described above, and in …
FIGS. 25 and 26, and in an embodiment of block 2010, the metal layer 2402 may be removed. In various embodiments, and depending on the material used for the …
FIG. 26, illustrated therein is the curved (e.g., concave) region 2105 and regions 2605 adjacent to and on either side of the curved region 2105. In some …
FIG. 27, after performing the thermal treatment in the reducing atmosphere and in an embodiment of block 2012, source/drain electrodes 2702 and a gate …
FIG. 28, and in an additional embodiment of block 2012, electrodes may be formed on the device 2200 including the curved convex region 2205. [0063] The device …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method, comprising: providing a substrate including a nanorod extending therefrom, wherein the nanorod includes an insulating outer surface that traverses a circumference of the nanorod; forming, by a vapor phase deposition process, a carbon-containing layer over the insulating outer surface; depositing a metal layer over the carbon-containing layer; and after depositing the metal layer, performing an annealing process, wherein the annealing process serves to convert the carbon-containing layer into a carbon nanotube (CNT). Original
The method of claim 1, wherein the CNT includes one of a single- wall CNT (SW-CNT), a double-wall CNT (DW-CNT), and a multi-wall CNT (MW-CNT). Original
The method of claim 1, wherein the nanorod includes a first diameter, and wherein the CNT includes a second diameter substantially equal to the first diameter. Original
The method of claim 1, wherein the vapor phase deposition process includes one of an atomic layer deposition (ALD) process and a molecular layer deposition (MLD) process. Original
The method of claim 1, wherein the carbon-containing layer includes a self-assembled monolayer (SAM). Original
The method of claim 1, wherein the metal layer includes one of Ni, Cu, Pt, Fe, Co, Au, and a Cu-Ni alloy. Original
The method of claim 1, further comprising: after performing the annealing process, removing the metal layer and performing a thermal treatment in a reducing atmosphere; and after performing the thermal treatment, forming source and drain electrodes in contact with the CNT; after forming the source and drain electrodes, depositing a top-gate dielectric layer over the CNT; and forming a top-gate electrode on the top-gate dielectric. Original
The method of claim 1, wherein a CNT band gap is determined at least in part by the first diameter. Original
The method of claim 1, further comprising: prior to forming the carbon-containing layer, cleaning the insulating outer surface of the nanorod. Original
A method, comprising: forming a plurality of nanorods extending from a substrate; depositing an oxide layer over an outer surface of each of the plurality of nanorods; forming a carbon-containing layer, the carbon-containing layer including a self-assembled monolayer (SAM), conformally over the oxide layer; depositing a metal layer over the SAM; and Serial No.: 15/925,195 Attorney Docket No. 20150929/24061.3218US02 Response to Restriction Requirement mailed 09/05/2018 Customer No.: 42717 after depositing the metal layer, performing an annealing process to convert the SAM into a carbon nanotube (CNT). Original
The method of claim 12, wherein each of the plurality of nanorods have a first diameter, wherein each of the plurality of nanorods including the oxide layer have a second diameter greater than the first diameter, and wherein the CNT includes a third diameter substantially equal to the second diameter. Original
The method of claim 12, wherein the SAM includes one of tridecafluoro-tetrahydrooctyl-trichlorosilane (FOTS) and dodecyltrichlorosilane (DT S). Original
The method of claim 12, further comprising: after performing the annealing process, etching the metal layer and thermally treating the CNT. Original
17-20. Canceled
Canceled
A method, comprising: providing a first substrate including a nanowire extending therefrom; forming a self-assembled monolayer (SAM) over an outer surface of the nanowire; depositing a metal layer over the SAM; after depositing the metal layer, performing a pyrolysis process to convert the SAM into a carbon nanotube (CNT); transferring the CNT onto an insulating surface of a second substrate; and Serial No.: 15/925,195 Attorney Docket No. 20150929/24061.3218US02 Response to Restriction Requirement mailed 09/05/2018 Customer No.: 42717 forming source and drain electrodes in contact with the CNT, depositing a top-gate dielectric layer over the CNT, and forming a top-gate electrode on the top-gate dielectric. New
The method of claim 21, wherein the outer surface of the nanowire includes an insulating outer surface that traverses a circumference of the nanowire. New
The method of claim 21, wherein the CNT includes one of a single- wall CNT (SW-CNT), a double-wall CNT (DW-CNT), and a multi-wall CNT (MW-CNT). New
The method of claim 21, wherein the SAM includes one of tridecafluoro-tetrahydrooctyl-trichlorosilane (FOTS), and dodecyltrichlorosilane (DT S). New
Layer stacks claimed or described, ordered top of device to substrate.
CNT on nanorod
top-gate CNT field-effect transistor
Materials described outside the worked examples.
carbon nanotube (CNT)
carbon-containing layer/self-assembled monolayer (SAM)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a cross-sectional view of a back-gated graphene device; [0006]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 90–100 nm | — |
Thickness | 280–300 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,290,808Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view of a back-gated graphene device; [0006]
FIG. 2 is a flow chart of a method of fabricating a graphene device according to one or more aspects of the present disclosure; [0007]
FIGS. 3, 4, 5, 6, 7, and 8 illustrate cross sectional views of embodiments of a graphene device according to one or more aspects of the present disclosure and …
FIGS. 4A, 4 B, and 4C illustrate chemical structures of precursors used to form silane-containing self-assembled monolayers (SAMs), according to one or more …
FIG. 5, and in an embodiment of block 206, a metal layer 502 is formed over the carbon-containing layer 402 (e.g., the SAM). In various embodiments, the metal …
FIG. 6, and as a result of the anneal process, the graphene layer 602 is formed between the metal layer 502 (e.g., the catalytic metal) and the insulating …
FIG. 7, the graphene layer 602 has been directly formed on the insulating layer 304 using a transfer-free process. After removal of the metal layer 502, and in …
FIG. 8 includes a back-gated graphene device, where the directly formed, transfer-free graphene layer 602 is contacted by source/drain electrodes 802, and the …
FIG. 9 is a cross-sectional view of a dual-gated graphene device according to one or more aspects of the present disclosure; [0010]
FIG. 10 is a cross-sectional view of a top-gated graphene device according to one or more aspects of the present disclosure; [0011]
FIG. 11 is a flow chart of a method of fabricating a carbon nanotube (CNT) according to one or more aspects of the present disclosure; [0012]
FIGS. 12, 13, 14, 15, 16, and 17 illustrate cross sectional views of embodiments of the CNT according to one or more aspects of the present disclosure and …
FIG. 13. Generally, after nanorod formation and in some embodiments, an insulating layer (e.g., an oxide layer) may be formed over the surface of the nanorod …
FIG. 14, and in an embodiment of block 1104, a carbon-containing layer 1402 is formed over the insulating surface 1302 of the nanorod 1204, thereby providing a …
FIG. 15, and in an embodiment of block 1106, a metal layer 1502 is formed over the carbon-containing layer 1402 (e.g., the SAM). In various embodiments, the …
FIGS. 16 and 17, and in an embodiment of block 1110, the metal layer 1502 may be removed. In various embodiments, and depending on the material used for the …
FIG. 17, the CNT 1602 has been directly formed on the insulating surface 1302 of the nanorod 1204 using a transfer-free process. After removal of the metal …
FIG. 18 is a cross-sectional view of a back-gated CNT transistor according to one or more aspects of the present disclosure; [0014]
FIG. 19 is a cross-sectional view of a dual-gated CNT transistor according to one or more aspects of the present disclosure; [0015]
FIG. 20. DETAILED
FIGS. 21, 22, 23, 24, 25, 26, 27, and 28 illustrate cross sectional views of embodiments of the curved graphene transistor according to one or more aspects of …
FIG. 22, and in an additional embodiment of block 2002, a device 2200 including a substrate 2102 having a curved region 2205 may be provided, where the curved …
FIG. 23, and in an embodiment of block 2004, a carbon-containing layer 2302 is formed over the insulating layer 2104, thereby providing a carbon source for …
FIG. 24, and in an embodiment of block 2006, a metal layer 2402 is formed over the carbon-containing layer 2302 (e.g., the SAM). As described above, and in …
FIGS. 25 and 26, and in an embodiment of block 2010, the metal layer 2402 may be removed. In various embodiments, and depending on the material used for the …
FIG. 26, illustrated therein is the curved (e.g., concave) region 2105 and regions 2605 adjacent to and on either side of the curved region 2105. In some …
FIG. 27, after performing the thermal treatment in the reducing atmosphere and in an embodiment of block 2012, source/drain electrodes 2702 and a gate …
FIG. 28, and in an additional embodiment of block 2012, electrodes may be formed on the device 2200 including the curved convex region 2205. [0063] The device …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method, comprising: providing a substrate including a nanorod extending therefrom, wherein the nanorod includes an insulating outer surface that traverses a circumference of the nanorod; forming, by a vapor phase deposition process, a carbon-containing layer over the insulating outer surface; depositing a metal layer over the carbon-containing layer; and after depositing the metal layer, performing an annealing process, wherein the annealing process serves to convert the carbon-containing layer into a carbon nanotube (CNT). Original
The method of claim 1, wherein the CNT includes one of a single- wall CNT (SW-CNT), a double-wall CNT (DW-CNT), and a multi-wall CNT (MW-CNT). Original
The method of claim 1, wherein the nanorod includes a first diameter, and wherein the CNT includes a second diameter substantially equal to the first diameter. Original
The method of claim 1, wherein the vapor phase deposition process includes one of an atomic layer deposition (ALD) process and a molecular layer deposition (MLD) process. Original
The method of claim 1, wherein the carbon-containing layer includes a self-assembled monolayer (SAM). Original
The method of claim 1, wherein the metal layer includes one of Ni, Cu, Pt, Fe, Co, Au, and a Cu-Ni alloy. Original
The method of claim 1, further comprising: after performing the annealing process, removing the metal layer and performing a thermal treatment in a reducing atmosphere; and after performing the thermal treatment, forming source and drain electrodes in contact with the CNT; after forming the source and drain electrodes, depositing a top-gate dielectric layer over the CNT; and forming a top-gate electrode on the top-gate dielectric. Original
The method of claim 1, wherein a CNT band gap is determined at least in part by the first diameter. Original
The method of claim 1, further comprising: prior to forming the carbon-containing layer, cleaning the insulating outer surface of the nanorod. Original
A method, comprising: forming a plurality of nanorods extending from a substrate; depositing an oxide layer over an outer surface of each of the plurality of nanorods; forming a carbon-containing layer, the carbon-containing layer including a self-assembled monolayer (SAM), conformally over the oxide layer; depositing a metal layer over the SAM; and Serial No.: 15/925,195 Attorney Docket No. 20150929/24061.3218US02 Response to Restriction Requirement mailed 09/05/2018 Customer No.: 42717 after depositing the metal layer, performing an annealing process to convert the SAM into a carbon nanotube (CNT). Original
The method of claim 12, wherein each of the plurality of nanorods have a first diameter, wherein each of the plurality of nanorods including the oxide layer have a second diameter greater than the first diameter, and wherein the CNT includes a third diameter substantially equal to the second diameter. Original
The method of claim 12, wherein the SAM includes one of tridecafluoro-tetrahydrooctyl-trichlorosilane (FOTS) and dodecyltrichlorosilane (DT S). Original
The method of claim 12, further comprising: after performing the annealing process, etching the metal layer and thermally treating the CNT. Original
17-20. Canceled
Canceled
A method, comprising: providing a first substrate including a nanowire extending therefrom; forming a self-assembled monolayer (SAM) over an outer surface of the nanowire; depositing a metal layer over the SAM; after depositing the metal layer, performing a pyrolysis process to convert the SAM into a carbon nanotube (CNT); transferring the CNT onto an insulating surface of a second substrate; and Serial No.: 15/925,195 Attorney Docket No. 20150929/24061.3218US02 Response to Restriction Requirement mailed 09/05/2018 Customer No.: 42717 forming source and drain electrodes in contact with the CNT, depositing a top-gate dielectric layer over the CNT, and forming a top-gate electrode on the top-gate dielectric. New
The method of claim 21, wherein the outer surface of the nanowire includes an insulating outer surface that traverses a circumference of the nanowire. New
The method of claim 21, wherein the CNT includes one of a single- wall CNT (SW-CNT), a double-wall CNT (DW-CNT), and a multi-wall CNT (MW-CNT). New
The method of claim 21, wherein the SAM includes one of tridecafluoro-tetrahydrooctyl-trichlorosilane (FOTS), and dodecyltrichlorosilane (DT S). New
Layer stacks claimed or described, ordered top of device to substrate.
CNT on nanorod
top-gate CNT field-effect transistor
Materials described outside the worked examples.
carbon nanotube (CNT)
carbon-containing layer/self-assembled monolayer (SAM)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a cross-sectional view of a back-gated graphene device; [0006]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 90–100 nm | — |
Thickness | 280–300 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,290,808Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view of a back-gated graphene device; [0006]
FIG. 2 is a flow chart of a method of fabricating a graphene device according to one or more aspects of the present disclosure; [0007]
FIGS. 3, 4, 5, 6, 7, and 8 illustrate cross sectional views of embodiments of a graphene device according to one or more aspects of the present disclosure and …
FIGS. 4A, 4 B, and 4C illustrate chemical structures of precursors used to form silane-containing self-assembled monolayers (SAMs), according to one or more …
FIG. 5, and in an embodiment of block 206, a metal layer 502 is formed over the carbon-containing layer 402 (e.g., the SAM). In various embodiments, the metal …
FIG. 6, and as a result of the anneal process, the graphene layer 602 is formed between the metal layer 502 (e.g., the catalytic metal) and the insulating …
FIG. 7, the graphene layer 602 has been directly formed on the insulating layer 304 using a transfer-free process. After removal of the metal layer 502, and in …
FIG. 8 includes a back-gated graphene device, where the directly formed, transfer-free graphene layer 602 is contacted by source/drain electrodes 802, and the …
FIG. 9 is a cross-sectional view of a dual-gated graphene device according to one or more aspects of the present disclosure; [0010]
FIG. 10 is a cross-sectional view of a top-gated graphene device according to one or more aspects of the present disclosure; [0011]
FIG. 11 is a flow chart of a method of fabricating a carbon nanotube (CNT) according to one or more aspects of the present disclosure; [0012]
FIGS. 12, 13, 14, 15, 16, and 17 illustrate cross sectional views of embodiments of the CNT according to one or more aspects of the present disclosure and …
FIG. 13. Generally, after nanorod formation and in some embodiments, an insulating layer (e.g., an oxide layer) may be formed over the surface of the nanorod …
FIG. 14, and in an embodiment of block 1104, a carbon-containing layer 1402 is formed over the insulating surface 1302 of the nanorod 1204, thereby providing a …
FIG. 15, and in an embodiment of block 1106, a metal layer 1502 is formed over the carbon-containing layer 1402 (e.g., the SAM). In various embodiments, the …
FIGS. 16 and 17, and in an embodiment of block 1110, the metal layer 1502 may be removed. In various embodiments, and depending on the material used for the …
FIG. 17, the CNT 1602 has been directly formed on the insulating surface 1302 of the nanorod 1204 using a transfer-free process. After removal of the metal …
FIG. 18 is a cross-sectional view of a back-gated CNT transistor according to one or more aspects of the present disclosure; [0014]
FIG. 19 is a cross-sectional view of a dual-gated CNT transistor according to one or more aspects of the present disclosure; [0015]
FIG. 20. DETAILED
FIGS. 21, 22, 23, 24, 25, 26, 27, and 28 illustrate cross sectional views of embodiments of the curved graphene transistor according to one or more aspects of …
FIG. 22, and in an additional embodiment of block 2002, a device 2200 including a substrate 2102 having a curved region 2205 may be provided, where the curved …
FIG. 23, and in an embodiment of block 2004, a carbon-containing layer 2302 is formed over the insulating layer 2104, thereby providing a carbon source for …
FIG. 24, and in an embodiment of block 2006, a metal layer 2402 is formed over the carbon-containing layer 2302 (e.g., the SAM). As described above, and in …
FIGS. 25 and 26, and in an embodiment of block 2010, the metal layer 2402 may be removed. In various embodiments, and depending on the material used for the …
FIG. 26, illustrated therein is the curved (e.g., concave) region 2105 and regions 2605 adjacent to and on either side of the curved region 2105. In some …
FIG. 27, after performing the thermal treatment in the reducing atmosphere and in an embodiment of block 2012, source/drain electrodes 2702 and a gate …
FIG. 28, and in an additional embodiment of block 2012, electrodes may be formed on the device 2200 including the curved convex region 2205. [0063] The device …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method, comprising: providing a substrate including a nanorod extending therefrom, wherein the nanorod includes an insulating outer surface that traverses a circumference of the nanorod; forming, by a vapor phase deposition process, a carbon-containing layer over the insulating outer surface; depositing a metal layer over the carbon-containing layer; and after depositing the metal layer, performing an annealing process, wherein the annealing process serves to convert the carbon-containing layer into a carbon nanotube (CNT). Original
The method of claim 1, wherein the CNT includes one of a single- wall CNT (SW-CNT), a double-wall CNT (DW-CNT), and a multi-wall CNT (MW-CNT). Original
The method of claim 1, wherein the nanorod includes a first diameter, and wherein the CNT includes a second diameter substantially equal to the first diameter. Original
The method of claim 1, wherein the vapor phase deposition process includes one of an atomic layer deposition (ALD) process and a molecular layer deposition (MLD) process. Original
The method of claim 1, wherein the carbon-containing layer includes a self-assembled monolayer (SAM). Original
The method of claim 1, wherein the metal layer includes one of Ni, Cu, Pt, Fe, Co, Au, and a Cu-Ni alloy. Original
The method of claim 1, further comprising: after performing the annealing process, removing the metal layer and performing a thermal treatment in a reducing atmosphere; and after performing the thermal treatment, forming source and drain electrodes in contact with the CNT; after forming the source and drain electrodes, depositing a top-gate dielectric layer over the CNT; and forming a top-gate electrode on the top-gate dielectric. Original
The method of claim 1, wherein a CNT band gap is determined at least in part by the first diameter. Original
The method of claim 1, further comprising: prior to forming the carbon-containing layer, cleaning the insulating outer surface of the nanorod. Original
A method, comprising: forming a plurality of nanorods extending from a substrate; depositing an oxide layer over an outer surface of each of the plurality of nanorods; forming a carbon-containing layer, the carbon-containing layer including a self-assembled monolayer (SAM), conformally over the oxide layer; depositing a metal layer over the SAM; and Serial No.: 15/925,195 Attorney Docket No. 20150929/24061.3218US02 Response to Restriction Requirement mailed 09/05/2018 Customer No.: 42717 after depositing the metal layer, performing an annealing process to convert the SAM into a carbon nanotube (CNT). Original
The method of claim 12, wherein each of the plurality of nanorods have a first diameter, wherein each of the plurality of nanorods including the oxide layer have a second diameter greater than the first diameter, and wherein the CNT includes a third diameter substantially equal to the second diameter. Original
The method of claim 12, wherein the SAM includes one of tridecafluoro-tetrahydrooctyl-trichlorosilane (FOTS) and dodecyltrichlorosilane (DT S). Original
The method of claim 12, further comprising: after performing the annealing process, etching the metal layer and thermally treating the CNT. Original
17-20. Canceled
Canceled
A method, comprising: providing a first substrate including a nanowire extending therefrom; forming a self-assembled monolayer (SAM) over an outer surface of the nanowire; depositing a metal layer over the SAM; after depositing the metal layer, performing a pyrolysis process to convert the SAM into a carbon nanotube (CNT); transferring the CNT onto an insulating surface of a second substrate; and Serial No.: 15/925,195 Attorney Docket No. 20150929/24061.3218US02 Response to Restriction Requirement mailed 09/05/2018 Customer No.: 42717 forming source and drain electrodes in contact with the CNT, depositing a top-gate dielectric layer over the CNT, and forming a top-gate electrode on the top-gate dielectric. New
The method of claim 21, wherein the outer surface of the nanowire includes an insulating outer surface that traverses a circumference of the nanowire. New
The method of claim 21, wherein the CNT includes one of a single- wall CNT (SW-CNT), a double-wall CNT (DW-CNT), and a multi-wall CNT (MW-CNT). New
The method of claim 21, wherein the SAM includes one of tridecafluoro-tetrahydrooctyl-trichlorosilane (FOTS), and dodecyltrichlorosilane (DT S). New
Layer stacks claimed or described, ordered top of device to substrate.
CNT on nanorod
top-gate CNT field-effect transistor
Materials described outside the worked examples.
carbon nanotube (CNT)
carbon-containing layer/self-assembled monolayer (SAM)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a cross-sectional view of a back-gated graphene device; [0006]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 90–100 nm | — |
Thickness | 280–300 nm |
Related documents with shared materials, methods, properties, or citations.
back-gated graphene device
metal layer (catalytic metal)
tridecafluoro-tetrahydrooctyl-trichlorosilane (FOTS)
dodecyltrichlorosilane (DTS)
oxide layer
graphene
silicon dioxide (SiO₂) insulating layer
SiO₂
Ni
Cu
Pt
Fe
Co
Au
Cu-Ni alloy
FIG. 8 includes a back-gated graphene device, where the directly formed, transfer-free graphene layer 602 is contacted by source/drain electrodes 802, and the …
FIG. 18 is a cross-sectional view of a back-gated CNT transistor according to one or more aspects of the present disclosure; [0014]
FIG. 19 is a cross-sectional view of a dual-gated CNT transistor according to one or more aspects of the present disclosure; [0015]
FIGS. 21, 22, 23, 24, 25, 26, 27, and 28 illustrate cross sectional views of embodiments of the curved graphene transistor according to one or more aspects of …
FIG. 27, after performing the thermal treatment in the reducing atmosphere and in an embodiment of block 2012, source/drain electrodes 2702 and a gate …
| — |
Pressure | 0.5–1 Torr | — |
Duration | 1–60 minutes | — |
back-gated graphene device
metal layer (catalytic metal)
tridecafluoro-tetrahydrooctyl-trichlorosilane (FOTS)
dodecyltrichlorosilane (DTS)
oxide layer
graphene
silicon dioxide (SiO₂) insulating layer
SiO₂
Ni
Cu
Pt
Fe
Co
Au
Cu-Ni alloy
FIG. 8 includes a back-gated graphene device, where the directly formed, transfer-free graphene layer 602 is contacted by source/drain electrodes 802, and the …
FIG. 18 is a cross-sectional view of a back-gated CNT transistor according to one or more aspects of the present disclosure; [0014]
FIG. 19 is a cross-sectional view of a dual-gated CNT transistor according to one or more aspects of the present disclosure; [0015]
FIGS. 21, 22, 23, 24, 25, 26, 27, and 28 illustrate cross sectional views of embodiments of the curved graphene transistor according to one or more aspects of …
FIG. 27, after performing the thermal treatment in the reducing atmosphere and in an embodiment of block 2012, source/drain electrodes 2702 and a gate …
| — |
Pressure | 0.5–1 Torr | — |
Duration | 1–60 minutes | — |
back-gated graphene device
metal layer (catalytic metal)
tridecafluoro-tetrahydrooctyl-trichlorosilane (FOTS)
dodecyltrichlorosilane (DTS)
oxide layer
graphene
silicon dioxide (SiO₂) insulating layer
SiO₂
Ni
Cu
Pt
Fe
Co
Au
Cu-Ni alloy
FIG. 8 includes a back-gated graphene device, where the directly formed, transfer-free graphene layer 602 is contacted by source/drain electrodes 802, and the …
FIG. 18 is a cross-sectional view of a back-gated CNT transistor according to one or more aspects of the present disclosure; [0014]
FIG. 19 is a cross-sectional view of a dual-gated CNT transistor according to one or more aspects of the present disclosure; [0015]
FIGS. 21, 22, 23, 24, 25, 26, 27, and 28 illustrate cross sectional views of embodiments of the curved graphene transistor according to one or more aspects of …
FIG. 27, after performing the thermal treatment in the reducing atmosphere and in an embodiment of block 2012, source/drain electrodes 2702 and a gate …
| — |
Pressure | 0.5–1 Torr | — |
Duration | 1–60 minutes | — |
back-gated graphene device
metal layer (catalytic metal)
tridecafluoro-tetrahydrooctyl-trichlorosilane (FOTS)
dodecyltrichlorosilane (DTS)
oxide layer
graphene
silicon dioxide (SiO₂) insulating layer
SiO₂
Ni
Cu
Pt
Fe
Co
Au
Cu-Ni alloy
FIG. 8 includes a back-gated graphene device, where the directly formed, transfer-free graphene layer 602 is contacted by source/drain electrodes 802, and the …
FIG. 18 is a cross-sectional view of a back-gated CNT transistor according to one or more aspects of the present disclosure; [0014]
FIG. 19 is a cross-sectional view of a dual-gated CNT transistor according to one or more aspects of the present disclosure; [0015]
FIGS. 21, 22, 23, 24, 25, 26, 27, and 28 illustrate cross sectional views of embodiments of the curved graphene transistor according to one or more aspects of …
FIG. 27, after performing the thermal treatment in the reducing atmosphere and in an embodiment of block 2012, source/drain electrodes 2702 and a gate …
| — |
Pressure | 0.5–1 Torr | — |
Duration | 1–60 minutes | — |