Patent
US 9,082,613GRAPHENE NANOELECTRONIC DEVICE FABRICATION
Jonathan W. Ward, Michael J. O'Connor
Lockheed Martin Corporation·US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 9,082,613Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a measured etch rate of downstream hydrogen [0014]
FIG. 2 illustrates an optical image of an etched-back carbon fi lm; [0015]
FIG. 3 illustrates an atomic force microscopy (AFM) image of an etched-back carbon fi lm. DM US 41400583-1.083874.0417 3 Attorney Docket No. 083874-04 17 [0016]
FIGS. 4A and 4B depict a process for patterning a graphene layer segment on a substrate; [0017]
FIGS. 5A-5C depict a process for forming a device with a grapheme layer segment having portions with different thicknesses; [0018]
FIGS. 6A and 6B depict a process for forming electrical contacts on a patterned graphene layer segment; [0019]
FIGS. 7 A -7H depict a process for providing a passivated a graphene layer segment having an insulator layer thereabove, and forming electrical contacts with …
FIGS. 8A and 8B depict the formation of additional electronic nanocomponents for the formation of a field effect transistor.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of forming a graphene layer, comprising the steps o f: preparing a dispersion of functionalized graphene in a solvent; applying a coating of said dispersion onto a substrate and evaporating the solvent to form a layer of functionalized graphene; and defunctionalizing the graphene to form a graphene layer on the substrate. withdrawn
The method of claim 1, wherein the dispersion is applied to the substrate by spin coating. withdrawn
The method of claim 1, wherein the functionalized graphene is oxidized graphene. withdrawn
The method of claim 1, further comprising the steps of: applying a protective sacrificial layer to at least a portion of the graphene layer; applying an electrically insulating layer over at least a portion of the protective sacrificial layer in a configuration so as to be self-supporting upon removal of the protective sacrificial layer; removing the protective sacrificial layer to form a cavity between the graphene layer and the electrically insulating layer, thereby passivating the graphene layer; and DM US 58689492-1.083874.0417-2-Application No.: 13/847,433 optionally, forming or leaving openings in the electrically insulating layer and forming electrical connections to electronic nanocircuits in one or more layers on or above the electrically insulating layer. withdrawn
The method of claim 1, wherein the layer of graphene or functionalized graphene has a thickness of at least 20 A, and further comprising the step of etching the carbon or graphene layer to a thickness of less than 10 A. withdrawn
A method of forming a graphene layer, comprising the steps of: depositing a gra phene or carbon layer of graphen or depositing °'lay°r of amp>,-,r-e, on a substrate a the moro carbon layer o pd a carbon laye°r''..",,. hi a pol +°a e granular st-ct.°, said graphene or carbon layer having a fir st thickness of at least 20 nt- a substr-ate; and etching the ea-be-ef graphene or carbon layer to a second thickness of less than 10 A based on: absorbing a monola y er of hydrogen onto the g raphene or carbon la yer; annealin g the gra phene or carbon la y er under conditions sufficient to etch a monola y er of the gra phene or carbon la yer; and repeating the absorbing step and the annealin g step if necessary until the gra phene or carbon la y er is etched to the second thickness.
The method of claim 9, wherein the graphene or carbon layer is etched to a thickness of less than 7.5 A.
The method of claim 9, wherein the graphene or carbon layer is etched to a thickness corresponding to a single atomic layer graphene sheet.
The method of claim 9, wherein the gra phene la yer is deposited on the substrate, and wherein the graphene layer is deposited with chemical vapor deposition onto [[a]] the substrate having a graphene-forming catalyst.
The method of claim 9, wherein the carbon la y er is deposited on the substrate, and wherein a carbon layer is deposited by depositing an amorphous carbon layer by sputtering or atomic layer deposition and [[the]] annealing [[step]] the amorphous carbon la yer is ee4u^-ted in a nonoxidizing environment at a temperature between 800 ° C and 1200 ° C to produce a carbon la y er havin g a pol yc rystalline granular structure.
The method of claim 9, wherein the etching step comprises exposing the graphene or carbon layer to a remote plasma comprising hydrogen or an inductively coupled plasma comprising hydrogen.
. canceled
The method of claim [[17]] 9, wherein the annealing step is conducted in a non-oxidizing environment at a temperature between 800 ° C and 1200 °C.
The method of claim [[17]] 9 wherein the carbon la yer is deposited on the substrate, and wherein a carbon layer is deposited by depositing an amorphous carbon layer by sputtering or atomic layer deposition, and [[said]] annealing tep-pe-fems-sad the DM US 58689492-1.083874.0417-4-Application No.: 13/847,433 amorphous carbon la yer by etching function and -cnvers to convert the amorphous carbon to a polycrystalline granular structure.
A process of manufacturing a solid state electronic nanostructure including at least one graphene layer segment, comprising the steps o f: depositing or forming and optionally patterning the graphene layer segment having a thickness greater than 20 A onto a support, or depositing an amorphous carbon layer segment having a thickness greater than 20 A and converting the amorphous carbon to a polycrystalline granular structure at any point during the process; protecting a portion of the graphene or carbon layer segment with a mask; etching the unprotected portion of the graphene or carbon layer segment to a thickness of less than 10 A; and removing the mask, thereby providing a graphene layer segment with a portion having a thickness greater than 20 A and a portion having a thickness less than 10 A. withdrawn
The process of claim 20, wherein the portion of the graphene layer segment having a thickness less than 10 A is configured as a field effect transistor and the portion of the graphene layer segment having a thickness greater than 20 A is configured as an interconnect in electrical contact with the field effect transistor and one or more other components of the solid state electronic nanostructure. DM US 58689492-1.083874.0417-5-withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
passivated graphene nanoelectronic device
solid state electronic nanostructure with patterned graphene
Materials described outside the worked examples.
graphene
C
functionalized graphene
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3 illustrates an atomic force microscopy (AFM) image of an etched-back carbon fi lm. DM US 41400583-1.083874.0417 3 Attorney Docket No. 083874-04 17 [0016]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | 800–1200 °C | — |
Duration |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,082,613Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a measured etch rate of downstream hydrogen [0014]
FIG. 2 illustrates an optical image of an etched-back carbon fi lm; [0015]
FIG. 3 illustrates an atomic force microscopy (AFM) image of an etched-back carbon fi lm. DM US 41400583-1.083874.0417 3 Attorney Docket No. 083874-04 17 [0016]
FIGS. 4A and 4B depict a process for patterning a graphene layer segment on a substrate; [0017]
FIGS. 5A-5C depict a process for forming a device with a grapheme layer segment having portions with different thicknesses; [0018]
FIGS. 6A and 6B depict a process for forming electrical contacts on a patterned graphene layer segment; [0019]
FIGS. 7 A -7H depict a process for providing a passivated a graphene layer segment having an insulator layer thereabove, and forming electrical contacts with …
FIGS. 8A and 8B depict the formation of additional electronic nanocomponents for the formation of a field effect transistor.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of forming a graphene layer, comprising the steps o f: preparing a dispersion of functionalized graphene in a solvent; applying a coating of said dispersion onto a substrate and evaporating the solvent to form a layer of functionalized graphene; and defunctionalizing the graphene to form a graphene layer on the substrate. withdrawn
The method of claim 1, wherein the dispersion is applied to the substrate by spin coating. withdrawn
The method of claim 1, wherein the functionalized graphene is oxidized graphene. withdrawn
The method of claim 1, further comprising the steps of: applying a protective sacrificial layer to at least a portion of the graphene layer; applying an electrically insulating layer over at least a portion of the protective sacrificial layer in a configuration so as to be self-supporting upon removal of the protective sacrificial layer; removing the protective sacrificial layer to form a cavity between the graphene layer and the electrically insulating layer, thereby passivating the graphene layer; and DM US 58689492-1.083874.0417-2-Application No.: 13/847,433 optionally, forming or leaving openings in the electrically insulating layer and forming electrical connections to electronic nanocircuits in one or more layers on or above the electrically insulating layer. withdrawn
The method of claim 1, wherein the layer of graphene or functionalized graphene has a thickness of at least 20 A, and further comprising the step of etching the carbon or graphene layer to a thickness of less than 10 A. withdrawn
A method of forming a graphene layer, comprising the steps of: depositing a gra phene or carbon layer of graphen or depositing °'lay°r of amp>,-,r-e, on a substrate a the moro carbon layer o pd a carbon laye°r''..",,. hi a pol +°a e granular st-ct.°, said graphene or carbon layer having a fir st thickness of at least 20 nt- a substr-ate; and etching the ea-be-ef graphene or carbon layer to a second thickness of less than 10 A based on: absorbing a monola y er of hydrogen onto the g raphene or carbon la yer; annealin g the gra phene or carbon la y er under conditions sufficient to etch a monola y er of the gra phene or carbon la yer; and repeating the absorbing step and the annealin g step if necessary until the gra phene or carbon la y er is etched to the second thickness.
The method of claim 9, wherein the graphene or carbon layer is etched to a thickness of less than 7.5 A.
The method of claim 9, wherein the graphene or carbon layer is etched to a thickness corresponding to a single atomic layer graphene sheet.
The method of claim 9, wherein the gra phene la yer is deposited on the substrate, and wherein the graphene layer is deposited with chemical vapor deposition onto [[a]] the substrate having a graphene-forming catalyst.
The method of claim 9, wherein the carbon la y er is deposited on the substrate, and wherein a carbon layer is deposited by depositing an amorphous carbon layer by sputtering or atomic layer deposition and [[the]] annealing [[step]] the amorphous carbon la yer is ee4u^-ted in a nonoxidizing environment at a temperature between 800 ° C and 1200 ° C to produce a carbon la y er havin g a pol yc rystalline granular structure.
The method of claim 9, wherein the etching step comprises exposing the graphene or carbon layer to a remote plasma comprising hydrogen or an inductively coupled plasma comprising hydrogen.
. canceled
The method of claim [[17]] 9, wherein the annealing step is conducted in a non-oxidizing environment at a temperature between 800 ° C and 1200 °C.
The method of claim [[17]] 9 wherein the carbon la yer is deposited on the substrate, and wherein a carbon layer is deposited by depositing an amorphous carbon layer by sputtering or atomic layer deposition, and [[said]] annealing tep-pe-fems-sad the DM US 58689492-1.083874.0417-4-Application No.: 13/847,433 amorphous carbon la yer by etching function and -cnvers to convert the amorphous carbon to a polycrystalline granular structure.
A process of manufacturing a solid state electronic nanostructure including at least one graphene layer segment, comprising the steps o f: depositing or forming and optionally patterning the graphene layer segment having a thickness greater than 20 A onto a support, or depositing an amorphous carbon layer segment having a thickness greater than 20 A and converting the amorphous carbon to a polycrystalline granular structure at any point during the process; protecting a portion of the graphene or carbon layer segment with a mask; etching the unprotected portion of the graphene or carbon layer segment to a thickness of less than 10 A; and removing the mask, thereby providing a graphene layer segment with a portion having a thickness greater than 20 A and a portion having a thickness less than 10 A. withdrawn
The process of claim 20, wherein the portion of the graphene layer segment having a thickness less than 10 A is configured as a field effect transistor and the portion of the graphene layer segment having a thickness greater than 20 A is configured as an interconnect in electrical contact with the field effect transistor and one or more other components of the solid state electronic nanostructure. DM US 58689492-1.083874.0417-5-withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
passivated graphene nanoelectronic device
solid state electronic nanostructure with patterned graphene
Materials described outside the worked examples.
graphene
C
functionalized graphene
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3 illustrates an atomic force microscopy (AFM) image of an etched-back carbon fi lm. DM US 41400583-1.083874.0417 3 Attorney Docket No. 083874-04 17 [0016]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | 800–1200 °C | — |
Duration |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,082,613Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a measured etch rate of downstream hydrogen [0014]
FIG. 2 illustrates an optical image of an etched-back carbon fi lm; [0015]
FIG. 3 illustrates an atomic force microscopy (AFM) image of an etched-back carbon fi lm. DM US 41400583-1.083874.0417 3 Attorney Docket No. 083874-04 17 [0016]
FIGS. 4A and 4B depict a process for patterning a graphene layer segment on a substrate; [0017]
FIGS. 5A-5C depict a process for forming a device with a grapheme layer segment having portions with different thicknesses; [0018]
FIGS. 6A and 6B depict a process for forming electrical contacts on a patterned graphene layer segment; [0019]
FIGS. 7 A -7H depict a process for providing a passivated a graphene layer segment having an insulator layer thereabove, and forming electrical contacts with …
FIGS. 8A and 8B depict the formation of additional electronic nanocomponents for the formation of a field effect transistor.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of forming a graphene layer, comprising the steps o f: preparing a dispersion of functionalized graphene in a solvent; applying a coating of said dispersion onto a substrate and evaporating the solvent to form a layer of functionalized graphene; and defunctionalizing the graphene to form a graphene layer on the substrate. withdrawn
The method of claim 1, wherein the dispersion is applied to the substrate by spin coating. withdrawn
The method of claim 1, wherein the functionalized graphene is oxidized graphene. withdrawn
The method of claim 1, further comprising the steps of: applying a protective sacrificial layer to at least a portion of the graphene layer; applying an electrically insulating layer over at least a portion of the protective sacrificial layer in a configuration so as to be self-supporting upon removal of the protective sacrificial layer; removing the protective sacrificial layer to form a cavity between the graphene layer and the electrically insulating layer, thereby passivating the graphene layer; and DM US 58689492-1.083874.0417-2-Application No.: 13/847,433 optionally, forming or leaving openings in the electrically insulating layer and forming electrical connections to electronic nanocircuits in one or more layers on or above the electrically insulating layer. withdrawn
The method of claim 1, wherein the layer of graphene or functionalized graphene has a thickness of at least 20 A, and further comprising the step of etching the carbon or graphene layer to a thickness of less than 10 A. withdrawn
A method of forming a graphene layer, comprising the steps of: depositing a gra phene or carbon layer of graphen or depositing °'lay°r of amp>,-,r-e, on a substrate a the moro carbon layer o pd a carbon laye°r''..",,. hi a pol +°a e granular st-ct.°, said graphene or carbon layer having a fir st thickness of at least 20 nt- a substr-ate; and etching the ea-be-ef graphene or carbon layer to a second thickness of less than 10 A based on: absorbing a monola y er of hydrogen onto the g raphene or carbon la yer; annealin g the gra phene or carbon la y er under conditions sufficient to etch a monola y er of the gra phene or carbon la yer; and repeating the absorbing step and the annealin g step if necessary until the gra phene or carbon la y er is etched to the second thickness.
The method of claim 9, wherein the graphene or carbon layer is etched to a thickness of less than 7.5 A.
The method of claim 9, wherein the graphene or carbon layer is etched to a thickness corresponding to a single atomic layer graphene sheet.
The method of claim 9, wherein the gra phene la yer is deposited on the substrate, and wherein the graphene layer is deposited with chemical vapor deposition onto [[a]] the substrate having a graphene-forming catalyst.
The method of claim 9, wherein the carbon la y er is deposited on the substrate, and wherein a carbon layer is deposited by depositing an amorphous carbon layer by sputtering or atomic layer deposition and [[the]] annealing [[step]] the amorphous carbon la yer is ee4u^-ted in a nonoxidizing environment at a temperature between 800 ° C and 1200 ° C to produce a carbon la y er havin g a pol yc rystalline granular structure.
The method of claim 9, wherein the etching step comprises exposing the graphene or carbon layer to a remote plasma comprising hydrogen or an inductively coupled plasma comprising hydrogen.
. canceled
The method of claim [[17]] 9, wherein the annealing step is conducted in a non-oxidizing environment at a temperature between 800 ° C and 1200 °C.
The method of claim [[17]] 9 wherein the carbon la yer is deposited on the substrate, and wherein a carbon layer is deposited by depositing an amorphous carbon layer by sputtering or atomic layer deposition, and [[said]] annealing tep-pe-fems-sad the DM US 58689492-1.083874.0417-4-Application No.: 13/847,433 amorphous carbon la yer by etching function and -cnvers to convert the amorphous carbon to a polycrystalline granular structure.
A process of manufacturing a solid state electronic nanostructure including at least one graphene layer segment, comprising the steps o f: depositing or forming and optionally patterning the graphene layer segment having a thickness greater than 20 A onto a support, or depositing an amorphous carbon layer segment having a thickness greater than 20 A and converting the amorphous carbon to a polycrystalline granular structure at any point during the process; protecting a portion of the graphene or carbon layer segment with a mask; etching the unprotected portion of the graphene or carbon layer segment to a thickness of less than 10 A; and removing the mask, thereby providing a graphene layer segment with a portion having a thickness greater than 20 A and a portion having a thickness less than 10 A. withdrawn
The process of claim 20, wherein the portion of the graphene layer segment having a thickness less than 10 A is configured as a field effect transistor and the portion of the graphene layer segment having a thickness greater than 20 A is configured as an interconnect in electrical contact with the field effect transistor and one or more other components of the solid state electronic nanostructure. DM US 58689492-1.083874.0417-5-withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
passivated graphene nanoelectronic device
solid state electronic nanostructure with patterned graphene
Materials described outside the worked examples.
graphene
C
functionalized graphene
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3 illustrates an atomic force microscopy (AFM) image of an etched-back carbon fi lm. DM US 41400583-1.083874.0417 3 Attorney Docket No. 083874-04 17 [0016]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | 800–1200 °C | — |
Duration |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,082,613Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a measured etch rate of downstream hydrogen [0014]
FIG. 2 illustrates an optical image of an etched-back carbon fi lm; [0015]
FIG. 3 illustrates an atomic force microscopy (AFM) image of an etched-back carbon fi lm. DM US 41400583-1.083874.0417 3 Attorney Docket No. 083874-04 17 [0016]
FIGS. 4A and 4B depict a process for patterning a graphene layer segment on a substrate; [0017]
FIGS. 5A-5C depict a process for forming a device with a grapheme layer segment having portions with different thicknesses; [0018]
FIGS. 6A and 6B depict a process for forming electrical contacts on a patterned graphene layer segment; [0019]
FIGS. 7 A -7H depict a process for providing a passivated a graphene layer segment having an insulator layer thereabove, and forming electrical contacts with …
FIGS. 8A and 8B depict the formation of additional electronic nanocomponents for the formation of a field effect transistor.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of forming a graphene layer, comprising the steps o f: preparing a dispersion of functionalized graphene in a solvent; applying a coating of said dispersion onto a substrate and evaporating the solvent to form a layer of functionalized graphene; and defunctionalizing the graphene to form a graphene layer on the substrate. withdrawn
The method of claim 1, wherein the dispersion is applied to the substrate by spin coating. withdrawn
The method of claim 1, wherein the functionalized graphene is oxidized graphene. withdrawn
The method of claim 1, further comprising the steps of: applying a protective sacrificial layer to at least a portion of the graphene layer; applying an electrically insulating layer over at least a portion of the protective sacrificial layer in a configuration so as to be self-supporting upon removal of the protective sacrificial layer; removing the protective sacrificial layer to form a cavity between the graphene layer and the electrically insulating layer, thereby passivating the graphene layer; and DM US 58689492-1.083874.0417-2-Application No.: 13/847,433 optionally, forming or leaving openings in the electrically insulating layer and forming electrical connections to electronic nanocircuits in one or more layers on or above the electrically insulating layer. withdrawn
The method of claim 1, wherein the layer of graphene or functionalized graphene has a thickness of at least 20 A, and further comprising the step of etching the carbon or graphene layer to a thickness of less than 10 A. withdrawn
A method of forming a graphene layer, comprising the steps of: depositing a gra phene or carbon layer of graphen or depositing °'lay°r of amp>,-,r-e, on a substrate a the moro carbon layer o pd a carbon laye°r''..",,. hi a pol +°a e granular st-ct.°, said graphene or carbon layer having a fir st thickness of at least 20 nt- a substr-ate; and etching the ea-be-ef graphene or carbon layer to a second thickness of less than 10 A based on: absorbing a monola y er of hydrogen onto the g raphene or carbon la yer; annealin g the gra phene or carbon la y er under conditions sufficient to etch a monola y er of the gra phene or carbon la yer; and repeating the absorbing step and the annealin g step if necessary until the gra phene or carbon la y er is etched to the second thickness.
The method of claim 9, wherein the graphene or carbon layer is etched to a thickness of less than 7.5 A.
The method of claim 9, wherein the graphene or carbon layer is etched to a thickness corresponding to a single atomic layer graphene sheet.
The method of claim 9, wherein the gra phene la yer is deposited on the substrate, and wherein the graphene layer is deposited with chemical vapor deposition onto [[a]] the substrate having a graphene-forming catalyst.
The method of claim 9, wherein the carbon la y er is deposited on the substrate, and wherein a carbon layer is deposited by depositing an amorphous carbon layer by sputtering or atomic layer deposition and [[the]] annealing [[step]] the amorphous carbon la yer is ee4u^-ted in a nonoxidizing environment at a temperature between 800 ° C and 1200 ° C to produce a carbon la y er havin g a pol yc rystalline granular structure.
The method of claim 9, wherein the etching step comprises exposing the graphene or carbon layer to a remote plasma comprising hydrogen or an inductively coupled plasma comprising hydrogen.
. canceled
The method of claim [[17]] 9, wherein the annealing step is conducted in a non-oxidizing environment at a temperature between 800 ° C and 1200 °C.
The method of claim [[17]] 9 wherein the carbon la yer is deposited on the substrate, and wherein a carbon layer is deposited by depositing an amorphous carbon layer by sputtering or atomic layer deposition, and [[said]] annealing tep-pe-fems-sad the DM US 58689492-1.083874.0417-4-Application No.: 13/847,433 amorphous carbon la yer by etching function and -cnvers to convert the amorphous carbon to a polycrystalline granular structure.
A process of manufacturing a solid state electronic nanostructure including at least one graphene layer segment, comprising the steps o f: depositing or forming and optionally patterning the graphene layer segment having a thickness greater than 20 A onto a support, or depositing an amorphous carbon layer segment having a thickness greater than 20 A and converting the amorphous carbon to a polycrystalline granular structure at any point during the process; protecting a portion of the graphene or carbon layer segment with a mask; etching the unprotected portion of the graphene or carbon layer segment to a thickness of less than 10 A; and removing the mask, thereby providing a graphene layer segment with a portion having a thickness greater than 20 A and a portion having a thickness less than 10 A. withdrawn
The process of claim 20, wherein the portion of the graphene layer segment having a thickness less than 10 A is configured as a field effect transistor and the portion of the graphene layer segment having a thickness greater than 20 A is configured as an interconnect in electrical contact with the field effect transistor and one or more other components of the solid state electronic nanostructure. DM US 58689492-1.083874.0417-5-withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
passivated graphene nanoelectronic device
solid state electronic nanostructure with patterned graphene
Materials described outside the worked examples.
graphene
C
functionalized graphene
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3 illustrates an atomic force microscopy (AFM) image of an etched-back carbon fi lm. DM US 41400583-1.083874.0417 3 Attorney Docket No. 083874-04 17 [0016]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | 800–1200 °C | — |
Duration |
Related documents with shared materials, methods, properties, or citations.
graphene field effect transistor
oxidized graphene
oxidative etching agent
graphene-forming catalyst
silicon
Si
silicon oxide
SiO₂
aluminum oxide
Al₂O₃
hafnium oxide
HfO₂
silicon nitride
Si₃N₄
nickel
Ni
copper
Cu
platinum
Pt
ruthenium
Ru
palladium
Pd
gold
Au
rhodium
Rh
iridium
Ir
FIGS. 6A and 6B depict a process for forming electrical contacts on a patterned graphene layer segment; [0019]
FIGS. 7 A -7H depict a process for providing a passivated a graphene layer segment having an insulator layer thereabove, and forming electrical contacts with …
FIGS. 8A and 8B depict the formation of additional electronic nanocomponents for the formation of a field effect transistor.
| — |
Duration | 30–3600 s | — |
Temperature | 100–300 °C | — |
— | 0–25 W | — |
Pressure | 0.5–2 Torr | — |
Temperature | 800–900 °C | — |
Thickness | 1–2 nm | — |
Thickness | ≤ 1 nm | — |
Thickness | ≤ 20 nm | — |
Temperature | ≥ 400 °C | — |
Temperature | ≤ 10 k | — |
Temperature | ≥ 20 k | — |
graphene field effect transistor
oxidized graphene
oxidative etching agent
graphene-forming catalyst
silicon
Si
silicon oxide
SiO₂
aluminum oxide
Al₂O₃
hafnium oxide
HfO₂
silicon nitride
Si₃N₄
nickel
Ni
copper
Cu
platinum
Pt
ruthenium
Ru
palladium
Pd
gold
Au
rhodium
Rh
iridium
Ir
FIGS. 6A and 6B depict a process for forming electrical contacts on a patterned graphene layer segment; [0019]
FIGS. 7 A -7H depict a process for providing a passivated a graphene layer segment having an insulator layer thereabove, and forming electrical contacts with …
FIGS. 8A and 8B depict the formation of additional electronic nanocomponents for the formation of a field effect transistor.
| — |
Duration | 30–3600 s | — |
Temperature | 100–300 °C | — |
— | 0–25 W | — |
Pressure | 0.5–2 Torr | — |
Temperature | 800–900 °C | — |
Thickness | 1–2 nm | — |
Thickness | ≤ 1 nm | — |
Thickness | ≤ 20 nm | — |
Temperature | ≥ 400 °C | — |
Temperature | ≤ 10 k | — |
Temperature | ≥ 20 k | — |
graphene field effect transistor
oxidized graphene
oxidative etching agent
graphene-forming catalyst
silicon
Si
silicon oxide
SiO₂
aluminum oxide
Al₂O₃
hafnium oxide
HfO₂
silicon nitride
Si₃N₄
nickel
Ni
copper
Cu
platinum
Pt
ruthenium
Ru
palladium
Pd
gold
Au
rhodium
Rh
iridium
Ir
FIGS. 6A and 6B depict a process for forming electrical contacts on a patterned graphene layer segment; [0019]
FIGS. 7 A -7H depict a process for providing a passivated a graphene layer segment having an insulator layer thereabove, and forming electrical contacts with …
FIGS. 8A and 8B depict the formation of additional electronic nanocomponents for the formation of a field effect transistor.
| — |
Duration | 30–3600 s | — |
Temperature | 100–300 °C | — |
— | 0–25 W | — |
Pressure | 0.5–2 Torr | — |
Temperature | 800–900 °C | — |
Thickness | 1–2 nm | — |
Thickness | ≤ 1 nm | — |
Thickness | ≤ 20 nm | — |
Temperature | ≥ 400 °C | — |
Temperature | ≤ 10 k | — |
Temperature | ≥ 20 k | — |
graphene field effect transistor
oxidized graphene
oxidative etching agent
graphene-forming catalyst
silicon
Si
silicon oxide
SiO₂
aluminum oxide
Al₂O₃
hafnium oxide
HfO₂
silicon nitride
Si₃N₄
nickel
Ni
copper
Cu
platinum
Pt
ruthenium
Ru
palladium
Pd
gold
Au
rhodium
Rh
iridium
Ir
FIGS. 6A and 6B depict a process for forming electrical contacts on a patterned graphene layer segment; [0019]
FIGS. 7 A -7H depict a process for providing a passivated a graphene layer segment having an insulator layer thereabove, and forming electrical contacts with …
FIGS. 8A and 8B depict the formation of additional electronic nanocomponents for the formation of a field effect transistor.
| — |
Duration | 30–3600 s | — |
Temperature | 100–300 °C | — |
— | 0–25 W | — |
Pressure | 0.5–2 Torr | — |
Temperature | 800–900 °C | — |
Thickness | 1–2 nm | — |
Thickness | ≤ 1 nm | — |
Thickness | ≤ 20 nm | — |
Temperature | ≥ 400 °C | — |
Temperature | ≤ 10 k | — |
Temperature | ≥ 20 k | — |