An electronic device includes a boron nitride surface with a graphene layer over the boron nitride surface having a non-zero degree of lattice mismatch, and one or more electrical contacts on the graphene layer.

The electronic device of Example 1 configured such that the one or more electrical contacts include a pair of source/drain regions having a graphene channel region located therebetween, and a gate electrode located adjacent to the graphene channel region to form a transistor.

The non-zero degree of lattice mismatch includes rotation about a line normal to an interface plane between a lattice in the graphene layer and a lattice in the boron nitride surface.

The boron nitride surface includes a boron nitride layer over a substrate.

The gate electrode is below the graphene channel region.

The gate electrode is separated from the graphene channel region by the boron nitride layer.

The gate electrode is above the graphene channel region.

The transistor is formed on a silicon substrate.

The transistor is formed on an SiO₂ layer on the silicon substrate.

A method of forming an electronic device: forming a graphene layer and mechanically placing the graphene layer on a boron nitride layer wherein the graphene layer is placed with a non-zero degree of lattice mismatch with the boron nitride layer, and attaching one or more electrical contacts to the graphene layer.

Forming the graphene layer includes forming the layer on a separate substrate using chemical vapor deposition techniques.

Using chemical vapor deposition techniques includes forming on a copper catalyst layer.

Using chemical vapor deposition techniques includes forming on a nickel catalyst layer.

Further includes forming the boron nitride layer using chemical vapor deposition techniques.

Forming the boron nitride layer using chemical vapor deposition techniques includes forming on a copper catalyst layer.

Forming the boron nitride layer using chemical vapor deposition techniques includes forming on a nickel catalyst layer.

A method of forming a graphene field effect transistor: forming a graphene layer using CVD, mechanically placing the graphene layer on a boron nitride layer with non-zero lattice mismatch, forming source/drain regions coupled to the graphene layer defining a graphene channel region, and coupling a gate electrode adjacent to and electrically separated from the graphene channel region.

Forming the graphene layer using CVD includes forming the graphene layer using a sacrificial catalyst layer.

Forming the graphene layer using a sacrificial catalyst layer includes forming the graphene layer using a metallic catalyst layer.

A method of forming a graphene field effect transistor: forming source/drain regions on a graphene layer defining a graphene channel region, forming a boron nitride layer using CVD, mechanically placing the boron nitride layer on the graphene layer forming an interface with non-zero lattice mismatch, and coupling a gate electrode adjacent to and electrically separated from the graphene channel region.

Forming the boron nitride layer using CVD includes forming the boron nitride layer using a sacrificial catalyst layer.

Forming the boron nitride layer using a sacrificial catalyst layer includes forming the boron nitride layer using a metallic catalyst layer.

An electronic device includes a boron nitride surface with a graphene layer over the boron nitride surface having a non-zero degree of lattice mismatch, and one or more electrical contacts on the graphene layer.

The electronic device of Example 1 configured such that the one or more electrical contacts include a pair of source/drain regions having a graphene channel region located therebetween, and a gate electrode located adjacent to the graphene channel region to form a transistor.

The non-zero degree of lattice mismatch includes rotation about a line normal to an interface plane between a lattice in the graphene layer and a lattice in the boron nitride surface.

The boron nitride surface includes a boron nitride layer over a substrate.

The gate electrode is below the graphene channel region.

The gate electrode is separated from the graphene channel region by the boron nitride layer.

The gate electrode is above the graphene channel region.

The transistor is formed on a silicon substrate.

The transistor is formed on an SiO₂ layer on the silicon substrate.

A method of forming an electronic device: forming a graphene layer and mechanically placing the graphene layer on a boron nitride layer wherein the graphene layer is placed with a non-zero degree of lattice mismatch with the boron nitride layer, and attaching one or more electrical contacts to the graphene layer.

Forming the graphene layer includes forming the layer on a separate substrate using chemical vapor deposition techniques.

Using chemical vapor deposition techniques includes forming on a copper catalyst layer.

Using chemical vapor deposition techniques includes forming on a nickel catalyst layer.

Further includes forming the boron nitride layer using chemical vapor deposition techniques.

Forming the boron nitride layer using chemical vapor deposition techniques includes forming on a copper catalyst layer.

Forming the boron nitride layer using chemical vapor deposition techniques includes forming on a nickel catalyst layer.

A method of forming a graphene field effect transistor: forming a graphene layer using CVD, mechanically placing the graphene layer on a boron nitride layer with non-zero lattice mismatch, forming source/drain regions coupled to the graphene layer defining a graphene channel region, and coupling a gate electrode adjacent to and electrically separated from the graphene channel region.

Forming the graphene layer using CVD includes forming the graphene layer using a sacrificial catalyst layer.

Forming the graphene layer using a sacrificial catalyst layer includes forming the graphene layer using a metallic catalyst layer.

A method of forming a graphene field effect transistor: forming source/drain regions on a graphene layer defining a graphene channel region, forming a boron nitride layer using CVD, mechanically placing the boron nitride layer on the graphene layer forming an interface with non-zero lattice mismatch, and coupling a gate electrode adjacent to and electrically separated from the graphene channel region.

Forming the boron nitride layer using CVD includes forming the boron nitride layer using a sacrificial catalyst layer.

Forming the boron nitride layer using a sacrificial catalyst layer includes forming the boron nitride layer using a metallic catalyst layer.

An electronic device includes a boron nitride surface with a graphene layer over the boron nitride surface having a non-zero degree of lattice mismatch, and one or more electrical contacts on the graphene layer.

The electronic device of Example 1 configured such that the one or more electrical contacts include a pair of source/drain regions having a graphene channel region located therebetween, and a gate electrode located adjacent to the graphene channel region to form a transistor.

The non-zero degree of lattice mismatch includes rotation about a line normal to an interface plane between a lattice in the graphene layer and a lattice in the boron nitride surface.

The boron nitride surface includes a boron nitride layer over a substrate.

The gate electrode is below the graphene channel region.

The gate electrode is separated from the graphene channel region by the boron nitride layer.

The gate electrode is above the graphene channel region.

The transistor is formed on a silicon substrate.

The transistor is formed on an SiO₂ layer on the silicon substrate.

A method of forming an electronic device: forming a graphene layer and mechanically placing the graphene layer on a boron nitride layer wherein the graphene layer is placed with a non-zero degree of lattice mismatch with the boron nitride layer, and attaching one or more electrical contacts to the graphene layer.

Forming the graphene layer includes forming the layer on a separate substrate using chemical vapor deposition techniques.

Using chemical vapor deposition techniques includes forming on a copper catalyst layer.

Using chemical vapor deposition techniques includes forming on a nickel catalyst layer.

Further includes forming the boron nitride layer using chemical vapor deposition techniques.

Forming the boron nitride layer using chemical vapor deposition techniques includes forming on a copper catalyst layer.

Forming the boron nitride layer using chemical vapor deposition techniques includes forming on a nickel catalyst layer.

A method of forming a graphene field effect transistor: forming a graphene layer using CVD, mechanically placing the graphene layer on a boron nitride layer with non-zero lattice mismatch, forming source/drain regions coupled to the graphene layer defining a graphene channel region, and coupling a gate electrode adjacent to and electrically separated from the graphene channel region.

Forming the graphene layer using CVD includes forming the graphene layer using a sacrificial catalyst layer.

Forming the graphene layer using a sacrificial catalyst layer includes forming the graphene layer using a metallic catalyst layer.

A method of forming a graphene field effect transistor: forming source/drain regions on a graphene layer defining a graphene channel region, forming a boron nitride layer using CVD, mechanically placing the boron nitride layer on the graphene layer forming an interface with non-zero lattice mismatch, and coupling a gate electrode adjacent to and electrically separated from the graphene channel region.

Forming the boron nitride layer using CVD includes forming the boron nitride layer using a sacrificial catalyst layer.

Forming the boron nitride layer using a sacrificial catalyst layer includes forming the boron nitride layer using a metallic catalyst layer.

An electronic device includes a boron nitride surface with a graphene layer over the boron nitride surface having a non-zero degree of lattice mismatch, and one or more electrical contacts on the graphene layer.

The electronic device of Example 1 configured such that the one or more electrical contacts include a pair of source/drain regions having a graphene channel region located therebetween, and a gate electrode located adjacent to the graphene channel region to form a transistor.

The non-zero degree of lattice mismatch includes rotation about a line normal to an interface plane between a lattice in the graphene layer and a lattice in the boron nitride surface.

The boron nitride surface includes a boron nitride layer over a substrate.

The gate electrode is below the graphene channel region.

The gate electrode is separated from the graphene channel region by the boron nitride layer.

The gate electrode is above the graphene channel region.

The transistor is formed on a silicon substrate.

The transistor is formed on an SiO₂ layer on the silicon substrate.

A method of forming an electronic device: forming a graphene layer and mechanically placing the graphene layer on a boron nitride layer wherein the graphene layer is placed with a non-zero degree of lattice mismatch with the boron nitride layer, and attaching one or more electrical contacts to the graphene layer.

Forming the graphene layer includes forming the layer on a separate substrate using chemical vapor deposition techniques.

Using chemical vapor deposition techniques includes forming on a copper catalyst layer.

Using chemical vapor deposition techniques includes forming on a nickel catalyst layer.

Further includes forming the boron nitride layer using chemical vapor deposition techniques.

Forming the boron nitride layer using chemical vapor deposition techniques includes forming on a copper catalyst layer.

Forming the boron nitride layer using chemical vapor deposition techniques includes forming on a nickel catalyst layer.

A method of forming a graphene field effect transistor: forming a graphene layer using CVD, mechanically placing the graphene layer on a boron nitride layer with non-zero lattice mismatch, forming source/drain regions coupled to the graphene layer defining a graphene channel region, and coupling a gate electrode adjacent to and electrically separated from the graphene channel region.

Forming the graphene layer using CVD includes forming the graphene layer using a sacrificial catalyst layer.

Forming the graphene layer using a sacrificial catalyst layer includes forming the graphene layer using a metallic catalyst layer.

A method of forming a graphene field effect transistor: forming source/drain regions on a graphene layer defining a graphene channel region, forming a boron nitride layer using CVD, mechanically placing the boron nitride layer on the graphene layer forming an interface with non-zero lattice mismatch, and coupling a gate electrode adjacent to and electrically separated from the graphene channel region.

Forming the boron nitride layer using CVD includes forming the boron nitride layer using a sacrificial catalyst layer.

Forming the boron nitride layer using a sacrificial catalyst layer includes forming the boron nitride layer using a metallic catalyst layer.