Patent
US 9,240,473HIGH TEMPERATURE PERFORMANCE CAPABLE GALLIUM NITRIDE TRANSISTOR
Sten Heikman, Yifeng Wu
CREE, INC.·US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
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US 9,240,473Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a sectional view of one embodiment of a transistor device according to the present invention; [0012]
FIG.2 is a sectional view of one embodiment of the gate of a transistor device according to the present invention; [0013]
FIG.3 is a sectional view of one embodiment of a transistor device according to the present invention; [0014]
FIG.4 is a sectional view of one embodiment of a FET according to the present invention; [0015]
FIG.5 is a sectional view of one embodiment of a FET according to the present invention; [0016]
FIG.6 is a plan view of the top side of a transistor device according to the present invention; and [0017]
FIG.7 is a graph power output versus time for two different gate materials. [0018]
FIG.8 is a graph of power output versus time for a transistor device having a gate electrode with a NiCr contact portion.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A transistor device, comprising: a plurality of semiconductor layers; a barrier layer on said semiconductor layers; a spacer layer on at least a portion of said barrier layer; and a gate electrode comprising a contact portion and a protective layer, said contact portion made from a material known to exhibit a Schottky barrier height greater than 0.4e V and an R F output power degradation of not more than 0.5 dB after 100 hours of operation at 350 ' C, wherein said gate electrode comprises a split-level structure comprising a middle region and outer region on at least one side of said middle region, such that said contact portion of said middle region is contacting said barrier layer and said contact portion of said outer regions is contacting said spacer layer.
The transistor device of claim 1, wherein said semiconductor layers comprise gallium nitride (G aN) based layers.
The transistor device of claim 1, wherein said contact portion comprises a nickel-chromium alloy (NiCr).
The transistor device of claim 1, wherein said contact portion comprises polycrystalline indium nitride (InN).
The transistor device of claim 1, wherein said contact portion comprises a thickness of not less than 5 nm and not more than 100 nm.
The transistor device of claim 1, wherein said contact portion comprises a thickness of approximately 2 0 nm.
A transistor device, comprising: a plurality of semiconductor layers; a gate electrode on said semiconductor layers, said gate electrode comprising: a contact portion contacting said semiconductor layers, said contact portion made from a material known to exhibit a Schottky barrier height greater than 0.4e V and an R F output Page 3 of 8 App l. No. 13/480,328 Office Action Dated: Response Dated: power degradation of not more than 0.5 d B after 100 hours of operation at 350 'C; a diffusion barrier on said contact portion, such that said contact portion is between said diffusion barrier and said semiconductor layers; a lateral conduction layer on said diffusion barrier; and a protective layer on said lateral conduction layer.
The transistor device of claim 10, wherein said diffusion barrier comprises a thickness of not less than 10 nm and not more than 100 nm.
The transistor device of claim 10, wherein said diffusion barrier comprises a thickness of approximately 30nm.
The transistor device of claim 10, wherein said lateral conduction layer comprises gold (Au).
The transistor device of claim 10, wherein said protective layer comprises nickel (Ni).
The transistor device of claim 10, wherein said lateral conduction layer comprises a thickness of not less than 100 nm and not more than 2000nm.
The transistor device of claim 10, wherein said lateral conduction layer comprises a thickness of approximately 400nm.
The transistor device of claim 10, wherein said protective layer comprises a thickness of not less than 10 nm and not more than 100nm.
The transistor device of claim 10, wherein said protective layer comprises a thickness of approximately 30 nm.
A gate electrode for use in a transistor device, comprising: a contact portion, said contact portion made from a material known to exhibit a Schottky barrier height greater than 0.4e V and an R F output power degradation of not more than 0.5 dB after 100 hours of operation at 350 'C; a diffusion barrier on said contact portion; a lateral conduction layer on said diffusion barrier; and a protective layer on said lateral conduction layer, wherein said protective layer is resistant to one or more treatment processes including ion bombardment.
(previ o usly presented) A gate electrode for use in a semiconductor device, comprising: a contact portion, said contact portion comprising nickel chromium (NiCr); a diffusion barrier on said contact portion; a lateral conduction layer on said diffusion barrier; and a protective layer on said lateral conduction layer, wherein said protective layer is configured to shield said lateral conduction layer from one or more processes including a corrosive process.
The gate electrode of claim 20, wherein said diffusion barrier comprises platinum (Pt), said lateral conduction barrier comprises gold (Au), and said protective layer comprises nickel (Ni). Page 6 of 8
Layer stacks claimed or described, ordered top of device to substrate.
GaN transistor with split-level gate electrode
Materials described outside the worked examples.
gate contact material with high Schottky barrier
spacer layer
gallium nitride
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a sectional view of one embodiment of a transistor device according to the present invention; [0012]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Schottky barrier height requirement | ≥ 0.4 | gate contact material with high Schottky barrier |
RF output power degradation after 100 h at 350 C | ≤ 0.5 |
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Patent
Atlas literature
Patent
US 9,240,473Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a sectional view of one embodiment of a transistor device according to the present invention; [0012]
FIG.2 is a sectional view of one embodiment of the gate of a transistor device according to the present invention; [0013]
FIG.3 is a sectional view of one embodiment of a transistor device according to the present invention; [0014]
FIG.4 is a sectional view of one embodiment of a FET according to the present invention; [0015]
FIG.5 is a sectional view of one embodiment of a FET according to the present invention; [0016]
FIG.6 is a plan view of the top side of a transistor device according to the present invention; and [0017]
FIG.7 is a graph power output versus time for two different gate materials. [0018]
FIG.8 is a graph of power output versus time for a transistor device having a gate electrode with a NiCr contact portion.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A transistor device, comprising: a plurality of semiconductor layers; a barrier layer on said semiconductor layers; a spacer layer on at least a portion of said barrier layer; and a gate electrode comprising a contact portion and a protective layer, said contact portion made from a material known to exhibit a Schottky barrier height greater than 0.4e V and an R F output power degradation of not more than 0.5 dB after 100 hours of operation at 350 ' C, wherein said gate electrode comprises a split-level structure comprising a middle region and outer region on at least one side of said middle region, such that said contact portion of said middle region is contacting said barrier layer and said contact portion of said outer regions is contacting said spacer layer.
The transistor device of claim 1, wherein said semiconductor layers comprise gallium nitride (G aN) based layers.
The transistor device of claim 1, wherein said contact portion comprises a nickel-chromium alloy (NiCr).
The transistor device of claim 1, wherein said contact portion comprises polycrystalline indium nitride (InN).
The transistor device of claim 1, wherein said contact portion comprises a thickness of not less than 5 nm and not more than 100 nm.
The transistor device of claim 1, wherein said contact portion comprises a thickness of approximately 2 0 nm.
A transistor device, comprising: a plurality of semiconductor layers; a gate electrode on said semiconductor layers, said gate electrode comprising: a contact portion contacting said semiconductor layers, said contact portion made from a material known to exhibit a Schottky barrier height greater than 0.4e V and an R F output Page 3 of 8 App l. No. 13/480,328 Office Action Dated: Response Dated: power degradation of not more than 0.5 d B after 100 hours of operation at 350 'C; a diffusion barrier on said contact portion, such that said contact portion is between said diffusion barrier and said semiconductor layers; a lateral conduction layer on said diffusion barrier; and a protective layer on said lateral conduction layer.
The transistor device of claim 10, wherein said diffusion barrier comprises a thickness of not less than 10 nm and not more than 100 nm.
The transistor device of claim 10, wherein said diffusion barrier comprises a thickness of approximately 30nm.
The transistor device of claim 10, wherein said lateral conduction layer comprises gold (Au).
The transistor device of claim 10, wherein said protective layer comprises nickel (Ni).
The transistor device of claim 10, wherein said lateral conduction layer comprises a thickness of not less than 100 nm and not more than 2000nm.
The transistor device of claim 10, wherein said lateral conduction layer comprises a thickness of approximately 400nm.
The transistor device of claim 10, wherein said protective layer comprises a thickness of not less than 10 nm and not more than 100nm.
The transistor device of claim 10, wherein said protective layer comprises a thickness of approximately 30 nm.
A gate electrode for use in a transistor device, comprising: a contact portion, said contact portion made from a material known to exhibit a Schottky barrier height greater than 0.4e V and an R F output power degradation of not more than 0.5 dB after 100 hours of operation at 350 'C; a diffusion barrier on said contact portion; a lateral conduction layer on said diffusion barrier; and a protective layer on said lateral conduction layer, wherein said protective layer is resistant to one or more treatment processes including ion bombardment.
(previ o usly presented) A gate electrode for use in a semiconductor device, comprising: a contact portion, said contact portion comprising nickel chromium (NiCr); a diffusion barrier on said contact portion; a lateral conduction layer on said diffusion barrier; and a protective layer on said lateral conduction layer, wherein said protective layer is configured to shield said lateral conduction layer from one or more processes including a corrosive process.
The gate electrode of claim 20, wherein said diffusion barrier comprises platinum (Pt), said lateral conduction barrier comprises gold (Au), and said protective layer comprises nickel (Ni). Page 6 of 8
Layer stacks claimed or described, ordered top of device to substrate.
GaN transistor with split-level gate electrode
Materials described outside the worked examples.
gate contact material with high Schottky barrier
spacer layer
gallium nitride
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a sectional view of one embodiment of a transistor device according to the present invention; [0012]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Schottky barrier height requirement | ≥ 0.4 | gate contact material with high Schottky barrier |
RF output power degradation after 100 h at 350 C | ≤ 0.5 |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,240,473Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a sectional view of one embodiment of a transistor device according to the present invention; [0012]
FIG.2 is a sectional view of one embodiment of the gate of a transistor device according to the present invention; [0013]
FIG.3 is a sectional view of one embodiment of a transistor device according to the present invention; [0014]
FIG.4 is a sectional view of one embodiment of a FET according to the present invention; [0015]
FIG.5 is a sectional view of one embodiment of a FET according to the present invention; [0016]
FIG.6 is a plan view of the top side of a transistor device according to the present invention; and [0017]
FIG.7 is a graph power output versus time for two different gate materials. [0018]
FIG.8 is a graph of power output versus time for a transistor device having a gate electrode with a NiCr contact portion.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A transistor device, comprising: a plurality of semiconductor layers; a barrier layer on said semiconductor layers; a spacer layer on at least a portion of said barrier layer; and a gate electrode comprising a contact portion and a protective layer, said contact portion made from a material known to exhibit a Schottky barrier height greater than 0.4e V and an R F output power degradation of not more than 0.5 dB after 100 hours of operation at 350 ' C, wherein said gate electrode comprises a split-level structure comprising a middle region and outer region on at least one side of said middle region, such that said contact portion of said middle region is contacting said barrier layer and said contact portion of said outer regions is contacting said spacer layer.
The transistor device of claim 1, wherein said semiconductor layers comprise gallium nitride (G aN) based layers.
The transistor device of claim 1, wherein said contact portion comprises a nickel-chromium alloy (NiCr).
The transistor device of claim 1, wherein said contact portion comprises polycrystalline indium nitride (InN).
The transistor device of claim 1, wherein said contact portion comprises a thickness of not less than 5 nm and not more than 100 nm.
The transistor device of claim 1, wherein said contact portion comprises a thickness of approximately 2 0 nm.
A transistor device, comprising: a plurality of semiconductor layers; a gate electrode on said semiconductor layers, said gate electrode comprising: a contact portion contacting said semiconductor layers, said contact portion made from a material known to exhibit a Schottky barrier height greater than 0.4e V and an R F output Page 3 of 8 App l. No. 13/480,328 Office Action Dated: Response Dated: power degradation of not more than 0.5 d B after 100 hours of operation at 350 'C; a diffusion barrier on said contact portion, such that said contact portion is between said diffusion barrier and said semiconductor layers; a lateral conduction layer on said diffusion barrier; and a protective layer on said lateral conduction layer.
The transistor device of claim 10, wherein said diffusion barrier comprises a thickness of not less than 10 nm and not more than 100 nm.
The transistor device of claim 10, wherein said diffusion barrier comprises a thickness of approximately 30nm.
The transistor device of claim 10, wherein said lateral conduction layer comprises gold (Au).
The transistor device of claim 10, wherein said protective layer comprises nickel (Ni).
The transistor device of claim 10, wherein said lateral conduction layer comprises a thickness of not less than 100 nm and not more than 2000nm.
The transistor device of claim 10, wherein said lateral conduction layer comprises a thickness of approximately 400nm.
The transistor device of claim 10, wherein said protective layer comprises a thickness of not less than 10 nm and not more than 100nm.
The transistor device of claim 10, wherein said protective layer comprises a thickness of approximately 30 nm.
A gate electrode for use in a transistor device, comprising: a contact portion, said contact portion made from a material known to exhibit a Schottky barrier height greater than 0.4e V and an R F output power degradation of not more than 0.5 dB after 100 hours of operation at 350 'C; a diffusion barrier on said contact portion; a lateral conduction layer on said diffusion barrier; and a protective layer on said lateral conduction layer, wherein said protective layer is resistant to one or more treatment processes including ion bombardment.
(previ o usly presented) A gate electrode for use in a semiconductor device, comprising: a contact portion, said contact portion comprising nickel chromium (NiCr); a diffusion barrier on said contact portion; a lateral conduction layer on said diffusion barrier; and a protective layer on said lateral conduction layer, wherein said protective layer is configured to shield said lateral conduction layer from one or more processes including a corrosive process.
The gate electrode of claim 20, wherein said diffusion barrier comprises platinum (Pt), said lateral conduction barrier comprises gold (Au), and said protective layer comprises nickel (Ni). Page 6 of 8
Layer stacks claimed or described, ordered top of device to substrate.
GaN transistor with split-level gate electrode
Materials described outside the worked examples.
gate contact material with high Schottky barrier
spacer layer
gallium nitride
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a sectional view of one embodiment of a transistor device according to the present invention; [0012]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Schottky barrier height requirement | ≥ 0.4 | gate contact material with high Schottky barrier |
RF output power degradation after 100 h at 350 C | ≤ 0.5 |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,240,473Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a sectional view of one embodiment of a transistor device according to the present invention; [0012]
FIG.2 is a sectional view of one embodiment of the gate of a transistor device according to the present invention; [0013]
FIG.3 is a sectional view of one embodiment of a transistor device according to the present invention; [0014]
FIG.4 is a sectional view of one embodiment of a FET according to the present invention; [0015]
FIG.5 is a sectional view of one embodiment of a FET according to the present invention; [0016]
FIG.6 is a plan view of the top side of a transistor device according to the present invention; and [0017]
FIG.7 is a graph power output versus time for two different gate materials. [0018]
FIG.8 is a graph of power output versus time for a transistor device having a gate electrode with a NiCr contact portion.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A transistor device, comprising: a plurality of semiconductor layers; a barrier layer on said semiconductor layers; a spacer layer on at least a portion of said barrier layer; and a gate electrode comprising a contact portion and a protective layer, said contact portion made from a material known to exhibit a Schottky barrier height greater than 0.4e V and an R F output power degradation of not more than 0.5 dB after 100 hours of operation at 350 ' C, wherein said gate electrode comprises a split-level structure comprising a middle region and outer region on at least one side of said middle region, such that said contact portion of said middle region is contacting said barrier layer and said contact portion of said outer regions is contacting said spacer layer.
The transistor device of claim 1, wherein said semiconductor layers comprise gallium nitride (G aN) based layers.
The transistor device of claim 1, wherein said contact portion comprises a nickel-chromium alloy (NiCr).
The transistor device of claim 1, wherein said contact portion comprises polycrystalline indium nitride (InN).
The transistor device of claim 1, wherein said contact portion comprises a thickness of not less than 5 nm and not more than 100 nm.
The transistor device of claim 1, wherein said contact portion comprises a thickness of approximately 2 0 nm.
A transistor device, comprising: a plurality of semiconductor layers; a gate electrode on said semiconductor layers, said gate electrode comprising: a contact portion contacting said semiconductor layers, said contact portion made from a material known to exhibit a Schottky barrier height greater than 0.4e V and an R F output Page 3 of 8 App l. No. 13/480,328 Office Action Dated: Response Dated: power degradation of not more than 0.5 d B after 100 hours of operation at 350 'C; a diffusion barrier on said contact portion, such that said contact portion is between said diffusion barrier and said semiconductor layers; a lateral conduction layer on said diffusion barrier; and a protective layer on said lateral conduction layer.
The transistor device of claim 10, wherein said diffusion barrier comprises a thickness of not less than 10 nm and not more than 100 nm.
The transistor device of claim 10, wherein said diffusion barrier comprises a thickness of approximately 30nm.
The transistor device of claim 10, wherein said lateral conduction layer comprises gold (Au).
The transistor device of claim 10, wherein said protective layer comprises nickel (Ni).
The transistor device of claim 10, wherein said lateral conduction layer comprises a thickness of not less than 100 nm and not more than 2000nm.
The transistor device of claim 10, wherein said lateral conduction layer comprises a thickness of approximately 400nm.
The transistor device of claim 10, wherein said protective layer comprises a thickness of not less than 10 nm and not more than 100nm.
The transistor device of claim 10, wherein said protective layer comprises a thickness of approximately 30 nm.
A gate electrode for use in a transistor device, comprising: a contact portion, said contact portion made from a material known to exhibit a Schottky barrier height greater than 0.4e V and an R F output power degradation of not more than 0.5 dB after 100 hours of operation at 350 'C; a diffusion barrier on said contact portion; a lateral conduction layer on said diffusion barrier; and a protective layer on said lateral conduction layer, wherein said protective layer is resistant to one or more treatment processes including ion bombardment.
(previ o usly presented) A gate electrode for use in a semiconductor device, comprising: a contact portion, said contact portion comprising nickel chromium (NiCr); a diffusion barrier on said contact portion; a lateral conduction layer on said diffusion barrier; and a protective layer on said lateral conduction layer, wherein said protective layer is configured to shield said lateral conduction layer from one or more processes including a corrosive process.
The gate electrode of claim 20, wherein said diffusion barrier comprises platinum (Pt), said lateral conduction barrier comprises gold (Au), and said protective layer comprises nickel (Ni). Page 6 of 8
Layer stacks claimed or described, ordered top of device to substrate.
GaN transistor with split-level gate electrode
Materials described outside the worked examples.
gate contact material with high Schottky barrier
spacer layer
gallium nitride
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a sectional view of one embodiment of a transistor device according to the present invention; [0012]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Schottky barrier height requirement | ≥ 0.4 | gate contact material with high Schottky barrier |
RF output power degradation after 100 h at 350 C | ≤ 0.5 |
Related documents with shared materials, methods, properties, or citations.
transistor device with multi-layer gate electrode
gate electrode with NiCr contact and protective Ni cap
nickel-chromium alloy
NiCr
polycrystalline indium nitride
InN
gold
Au
nickel
Ni
platinum
Pt
silicon nitride
SiN
AlGaN barrier layer
AlxGa₁-xN
silicon carbide substrate
SiC
AlzGa₁-zN nucleation layer
AlzGa₁-zN
FIG.2 is a sectional view of one embodiment of the gate of a transistor device according to the present invention; [0013]
FIG.3 is a sectional view of one embodiment of a transistor device according to the present invention; [0014]
FIG.4 is a sectional view of one embodiment of a FET according to the present invention; [0015]
FIG.5 is a sectional view of one embodiment of a FET according to the present invention; [0016]
FIG.6 is a plan view of the top side of a transistor device according to the present invention; and [0017]
FIG.8 is a graph of power output versus time for a transistor device having a gate electrode with a NiCr contact portion.
FIG.8 is a graph of power output versus time for a transistor device having a gate electrode with a NiCr contact portion.
durability at high operating temperatures. Other materials have exhibited similar results as discussed below. [0022] It will be understood that when an element or layer is referred to as being "on", "connected to", "coupled to" or "in contact with" another ele
gate contact material with high Schottky barrier |
Thickness | 0.1–2 µm | — |
— | 0.6–1 eV | — |
Thickness | 5–1000 nm | — |
Thickness | 10–100 nm | — |
Thickness | 100–2000 nm | — |
Pressure | ≤ 7 PA | — |
Pressure | ≥ 7 PA | — |
Thickness | ≤ 5 nm | — |
Thickness | ≤ 10 nm | — |
Thickness | ≤ 1 nm | — |
Thickness | ≥ 1 nm | — |
Thickness | ≥ 2000 nm | — |
— | ≥ 0.4 eV | — |
transistor device with multi-layer gate electrode
gate electrode with NiCr contact and protective Ni cap
nickel-chromium alloy
NiCr
polycrystalline indium nitride
InN
gold
Au
nickel
Ni
platinum
Pt
silicon nitride
SiN
AlGaN barrier layer
AlxGa₁-xN
silicon carbide substrate
SiC
AlzGa₁-zN nucleation layer
AlzGa₁-zN
FIG.2 is a sectional view of one embodiment of the gate of a transistor device according to the present invention; [0013]
FIG.3 is a sectional view of one embodiment of a transistor device according to the present invention; [0014]
FIG.4 is a sectional view of one embodiment of a FET according to the present invention; [0015]
FIG.5 is a sectional view of one embodiment of a FET according to the present invention; [0016]
FIG.6 is a plan view of the top side of a transistor device according to the present invention; and [0017]
FIG.8 is a graph of power output versus time for a transistor device having a gate electrode with a NiCr contact portion.
FIG.8 is a graph of power output versus time for a transistor device having a gate electrode with a NiCr contact portion.
durability at high operating temperatures. Other materials have exhibited similar results as discussed below. [0022] It will be understood that when an element or layer is referred to as being "on", "connected to", "coupled to" or "in contact with" another ele
gate contact material with high Schottky barrier |
Thickness | 0.1–2 µm | — |
— | 0.6–1 eV | — |
Thickness | 5–1000 nm | — |
Thickness | 10–100 nm | — |
Thickness | 100–2000 nm | — |
Pressure | ≤ 7 PA | — |
Pressure | ≥ 7 PA | — |
Thickness | ≤ 5 nm | — |
Thickness | ≤ 10 nm | — |
Thickness | ≤ 1 nm | — |
Thickness | ≥ 1 nm | — |
Thickness | ≥ 2000 nm | — |
— | ≥ 0.4 eV | — |
transistor device with multi-layer gate electrode
gate electrode with NiCr contact and protective Ni cap
nickel-chromium alloy
NiCr
polycrystalline indium nitride
InN
gold
Au
nickel
Ni
platinum
Pt
silicon nitride
SiN
AlGaN barrier layer
AlxGa₁-xN
silicon carbide substrate
SiC
AlzGa₁-zN nucleation layer
AlzGa₁-zN
FIG.2 is a sectional view of one embodiment of the gate of a transistor device according to the present invention; [0013]
FIG.3 is a sectional view of one embodiment of a transistor device according to the present invention; [0014]
FIG.4 is a sectional view of one embodiment of a FET according to the present invention; [0015]
FIG.5 is a sectional view of one embodiment of a FET according to the present invention; [0016]
FIG.6 is a plan view of the top side of a transistor device according to the present invention; and [0017]
FIG.8 is a graph of power output versus time for a transistor device having a gate electrode with a NiCr contact portion.
FIG.8 is a graph of power output versus time for a transistor device having a gate electrode with a NiCr contact portion.
durability at high operating temperatures. Other materials have exhibited similar results as discussed below. [0022] It will be understood that when an element or layer is referred to as being "on", "connected to", "coupled to" or "in contact with" another ele
gate contact material with high Schottky barrier |
Thickness | 0.1–2 µm | — |
— | 0.6–1 eV | — |
Thickness | 5–1000 nm | — |
Thickness | 10–100 nm | — |
Thickness | 100–2000 nm | — |
Pressure | ≤ 7 PA | — |
Pressure | ≥ 7 PA | — |
Thickness | ≤ 5 nm | — |
Thickness | ≤ 10 nm | — |
Thickness | ≤ 1 nm | — |
Thickness | ≥ 1 nm | — |
Thickness | ≥ 2000 nm | — |
— | ≥ 0.4 eV | — |
transistor device with multi-layer gate electrode
gate electrode with NiCr contact and protective Ni cap
nickel-chromium alloy
NiCr
polycrystalline indium nitride
InN
gold
Au
nickel
Ni
platinum
Pt
silicon nitride
SiN
AlGaN barrier layer
AlxGa₁-xN
silicon carbide substrate
SiC
AlzGa₁-zN nucleation layer
AlzGa₁-zN
FIG.2 is a sectional view of one embodiment of the gate of a transistor device according to the present invention; [0013]
FIG.3 is a sectional view of one embodiment of a transistor device according to the present invention; [0014]
FIG.4 is a sectional view of one embodiment of a FET according to the present invention; [0015]
FIG.5 is a sectional view of one embodiment of a FET according to the present invention; [0016]
FIG.6 is a plan view of the top side of a transistor device according to the present invention; and [0017]
FIG.8 is a graph of power output versus time for a transistor device having a gate electrode with a NiCr contact portion.
FIG.8 is a graph of power output versus time for a transistor device having a gate electrode with a NiCr contact portion.
durability at high operating temperatures. Other materials have exhibited similar results as discussed below. [0022] It will be understood that when an element or layer is referred to as being "on", "connected to", "coupled to" or "in contact with" another ele
gate contact material with high Schottky barrier |
Thickness | 0.1–2 µm | — |
— | 0.6–1 eV | — |
Thickness | 5–1000 nm | — |
Thickness | 10–100 nm | — |
Thickness | 100–2000 nm | — |
Pressure | ≤ 7 PA | — |
Pressure | ≥ 7 PA | — |
Thickness | ≤ 5 nm | — |
Thickness | ≤ 10 nm | — |
Thickness | ≤ 1 nm | — |
Thickness | ≥ 1 nm | — |
Thickness | ≥ 2000 nm | — |
— | ≥ 0.4 eV | — |