Patent
US 10,818,596METHOD FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE
Tai-I YANG
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 10,818,596Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 P, in accordance with some embodiments of the disclosure. [0042] A first through silicon via (TSV) 140 is formed through the first substrate 102, and the …
FIG. 2B, in accordance with some embodiments of the disclosure. More specifically, the first TSV 140 is formed over the first portion 110 a of the first graphene …
FIG. 3E, in accordance with some embodiments of the disclosure. The second TSV 240 is electrically connected to the first TSV 140. [0067] Afterwards, a third …
FIG. 10, in accordance with some embodiments of the disclosure. In some embodiments, the substrate 102 is thinned by a chemical mechanical polishing (CMP) …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for forming a semiconductor device structure, comprising: forming an interconnect structure over a first substrate, wherein forming the interconnect structure over the first substrate comprises: forming a first dielectric layer over the first substrate, wherein the first dielectric layer has a plurality of openings; forming a catalyst layer over the first dielectric layer and in the openings; forming a graphene layer on the catalyst layer, wherein the catalyst layer is surrounded by the graphene layer; forming an insulating layer on the graphene layer; patterning the insulating layer, the graphene layer and the catalyst layer, wherein the graphene layer is formed in the openings, and the insulating layer is formed on the graphene layer and in the openings; and removing the catalyst layer to leave a portion of the graphene layer in the first dielectric layer and on the first dielectric layer, wherein the graphene layer comprises a first portion formed in the first dielectric layer and a second portion formed over the first dielectric layer. Original
The method for forming the semiconductor device structure as claimed in claim 1, before forming the graphene layer on the catalyst layer, further comprising: patterning the catalyst layer to form a plurality of trenches, wherein each of the openings has a first width, each of the trenches has a second width, and the first width is greater than the second width. Original
The method for forming the semiconductor device structure as claimed in claim 1, before removing the catalyst layer, further comprising: removing a portion of the insulating layer to expose a portion of the graphene layer; and removing the exposed portion of the graphene layer. Original
The method for forming the semiconductor device structure as claimed in claim 1, further comprising: bonding the first substrate to a second substrate, wherein a transistor device structure is pre-formed over the second substrate. Original
The method for forming the semiconductor device structure as claimed in claim 1, further comprising: forming a second substrate below the first substrate; and forming a transistor device structure below the second substrate; forming a through-silicon via (TSV) through the second substrate and a portion of the interconnect structure, wherein the TSV is electrically connected to the first portion of the graphene layer. Previously presented
The method for forming the semiconductor device structure as claimed in claim 1, further comprising: forming a second dielectric layer below the first dielectric layer; and forming a second graphene layer in and below the second dielectric layer, wherein a portion of the second graphene layer interfaces with the second portion of the first graphene layer. Original
The method for forming the semiconductor device structure as claimed in claim 1, further comprising: forming a first TSV in the first substrate, wherein the first TSV is on the first graphene layer. Original
The method for forming the semiconductor device structure as claimed in claim 1, further comprising: performing an annealing process on the first graphene layer, wherein no active device is formed in the first substrate before performing the annealing process. Original
A method for forming a semiconductor device structure, comprising: forming a first dielectric layer over a first substrate, wherein the first dielectric layer has a plurality of openings; forming a catalyst layer over the first dielectric layer and in the openings; patterning the catalyst layer to form a plurality of trenches; forming a U-shaped graphene layer on the catalyst layer and in the trenches; forming an insulating layer in a recessed portion of the U-shaped graphene layer; removing the catalyst layer to leave a portion of the U-shaped graphene layer in the first dielectric layer and on the first dielectric layer, wherein the U-shaped graphene layer comprises a first portion formed in the first dielectric layer and a second portion formed over the first dielectric layer. Original
The method for forming the semiconductor device structure as claimed in claim 11, further comprising: forming a through-silicon via (TSV) in the first substrate, wherein a portion of the first graphene layer is in direct contact with the TSV. Previously presented
The method for forming the semiconductor device structure as claimed in claim 11, further comprising: forming a second dielectric layer below the first dielectric layer; and forming a second graphene layer in and below the second dielectric layer, wherein a portion of the second graphene layer interfaces with the second portion of the first graphene layer. Original
The method for forming the semiconductor device structure as claimed in claim 11, further comprising: forming a through-silicon via (TSV) over a front-side of the first substrate, wherein the insulating layer is in direct contact with the TSV. Withdrawn
The method for forming the semiconductor device structure as claimed in claim 11, further comprising: forming a second substrate below the first substrate; and forming a transistor device structure below the second substrate. Previously presented
The method for forming the semiconductor device structure as claimed in claim 11, further comprising: performing an annealing process on the first graphene layer, wherein no active device is formed in the first substrate before performing the annealing process. Previously presented
A method for forming a semiconductor device structure, comprising: forming a first dielectric layer over a first substrate, wherein the dielectric layer has a plurality of openings; forming a catalyst layer over the first dielectric layer and in the openings; forming a first graphene layer in the openings and on the catalyst layer, wherein the first graphene layer is formed on and below the catalyst layer to surround the catalyst layer; forming an insulating layer in the first graphene layer; forming a second dielectric layer over the first dielectric layer; and forming a second graphene layer in and over the second dielectric layer, wherein a portion of the second graphene layer interfaces with a portion of the first graphene layer. Currently amended
The method for forming the semiconductor device structure as claimed in claim 17, further comprising: forming a third dielectric layer over the second dielectric layer; and forming a third graphene layer in and over the third dielectric layer, wherein a portion of the third graphene layer interfaces with a portion of the second graphene layer. Previously presented
The method for forming the semiconductor device structure as claimed in claim 17, further comprising: forming a through-silicon via (TSV) in the first substrate, wherein the TSV is in direct contact with another portion of the first graphene layer. Previously presented
The method for forming the semiconductor device structure as claimed in claim 17, wherein the first graphene layer is in direct contact with the first dielectric layer after forming the first graphene layer in the openings. New
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
graphene interconnect structure
transistor device structure on second substrate
No layer stack recorded.
Materials described outside the worked examples.
graphene layer
C
catalyst layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 P, in accordance with some embodiments of the disclosure. [0042] A first through silicon via (TSV) 140 is formed through the first substrate 102, and the …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 100–300 nm | — |
Duration | 10–180 minutes |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,818,596Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 P, in accordance with some embodiments of the disclosure. [0042] A first through silicon via (TSV) 140 is formed through the first substrate 102, and the …
FIG. 2B, in accordance with some embodiments of the disclosure. More specifically, the first TSV 140 is formed over the first portion 110 a of the first graphene …
FIG. 3E, in accordance with some embodiments of the disclosure. The second TSV 240 is electrically connected to the first TSV 140. [0067] Afterwards, a third …
FIG. 10, in accordance with some embodiments of the disclosure. In some embodiments, the substrate 102 is thinned by a chemical mechanical polishing (CMP) …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for forming a semiconductor device structure, comprising: forming an interconnect structure over a first substrate, wherein forming the interconnect structure over the first substrate comprises: forming a first dielectric layer over the first substrate, wherein the first dielectric layer has a plurality of openings; forming a catalyst layer over the first dielectric layer and in the openings; forming a graphene layer on the catalyst layer, wherein the catalyst layer is surrounded by the graphene layer; forming an insulating layer on the graphene layer; patterning the insulating layer, the graphene layer and the catalyst layer, wherein the graphene layer is formed in the openings, and the insulating layer is formed on the graphene layer and in the openings; and removing the catalyst layer to leave a portion of the graphene layer in the first dielectric layer and on the first dielectric layer, wherein the graphene layer comprises a first portion formed in the first dielectric layer and a second portion formed over the first dielectric layer. Original
The method for forming the semiconductor device structure as claimed in claim 1, before forming the graphene layer on the catalyst layer, further comprising: patterning the catalyst layer to form a plurality of trenches, wherein each of the openings has a first width, each of the trenches has a second width, and the first width is greater than the second width. Original
The method for forming the semiconductor device structure as claimed in claim 1, before removing the catalyst layer, further comprising: removing a portion of the insulating layer to expose a portion of the graphene layer; and removing the exposed portion of the graphene layer. Original
The method for forming the semiconductor device structure as claimed in claim 1, further comprising: bonding the first substrate to a second substrate, wherein a transistor device structure is pre-formed over the second substrate. Original
The method for forming the semiconductor device structure as claimed in claim 1, further comprising: forming a second substrate below the first substrate; and forming a transistor device structure below the second substrate; forming a through-silicon via (TSV) through the second substrate and a portion of the interconnect structure, wherein the TSV is electrically connected to the first portion of the graphene layer. Previously presented
The method for forming the semiconductor device structure as claimed in claim 1, further comprising: forming a second dielectric layer below the first dielectric layer; and forming a second graphene layer in and below the second dielectric layer, wherein a portion of the second graphene layer interfaces with the second portion of the first graphene layer. Original
The method for forming the semiconductor device structure as claimed in claim 1, further comprising: forming a first TSV in the first substrate, wherein the first TSV is on the first graphene layer. Original
The method for forming the semiconductor device structure as claimed in claim 1, further comprising: performing an annealing process on the first graphene layer, wherein no active device is formed in the first substrate before performing the annealing process. Original
A method for forming a semiconductor device structure, comprising: forming a first dielectric layer over a first substrate, wherein the first dielectric layer has a plurality of openings; forming a catalyst layer over the first dielectric layer and in the openings; patterning the catalyst layer to form a plurality of trenches; forming a U-shaped graphene layer on the catalyst layer and in the trenches; forming an insulating layer in a recessed portion of the U-shaped graphene layer; removing the catalyst layer to leave a portion of the U-shaped graphene layer in the first dielectric layer and on the first dielectric layer, wherein the U-shaped graphene layer comprises a first portion formed in the first dielectric layer and a second portion formed over the first dielectric layer. Original
The method for forming the semiconductor device structure as claimed in claim 11, further comprising: forming a through-silicon via (TSV) in the first substrate, wherein a portion of the first graphene layer is in direct contact with the TSV. Previously presented
The method for forming the semiconductor device structure as claimed in claim 11, further comprising: forming a second dielectric layer below the first dielectric layer; and forming a second graphene layer in and below the second dielectric layer, wherein a portion of the second graphene layer interfaces with the second portion of the first graphene layer. Original
The method for forming the semiconductor device structure as claimed in claim 11, further comprising: forming a through-silicon via (TSV) over a front-side of the first substrate, wherein the insulating layer is in direct contact with the TSV. Withdrawn
The method for forming the semiconductor device structure as claimed in claim 11, further comprising: forming a second substrate below the first substrate; and forming a transistor device structure below the second substrate. Previously presented
The method for forming the semiconductor device structure as claimed in claim 11, further comprising: performing an annealing process on the first graphene layer, wherein no active device is formed in the first substrate before performing the annealing process. Previously presented
A method for forming a semiconductor device structure, comprising: forming a first dielectric layer over a first substrate, wherein the dielectric layer has a plurality of openings; forming a catalyst layer over the first dielectric layer and in the openings; forming a first graphene layer in the openings and on the catalyst layer, wherein the first graphene layer is formed on and below the catalyst layer to surround the catalyst layer; forming an insulating layer in the first graphene layer; forming a second dielectric layer over the first dielectric layer; and forming a second graphene layer in and over the second dielectric layer, wherein a portion of the second graphene layer interfaces with a portion of the first graphene layer. Currently amended
The method for forming the semiconductor device structure as claimed in claim 17, further comprising: forming a third dielectric layer over the second dielectric layer; and forming a third graphene layer in and over the third dielectric layer, wherein a portion of the third graphene layer interfaces with a portion of the second graphene layer. Previously presented
The method for forming the semiconductor device structure as claimed in claim 17, further comprising: forming a through-silicon via (TSV) in the first substrate, wherein the TSV is in direct contact with another portion of the first graphene layer. Previously presented
The method for forming the semiconductor device structure as claimed in claim 17, wherein the first graphene layer is in direct contact with the first dielectric layer after forming the first graphene layer in the openings. New
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
graphene interconnect structure
transistor device structure on second substrate
No layer stack recorded.
Materials described outside the worked examples.
graphene layer
C
catalyst layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 P, in accordance with some embodiments of the disclosure. [0042] A first through silicon via (TSV) 140 is formed through the first substrate 102, and the …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 100–300 nm | — |
Duration | 10–180 minutes |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,818,596Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 P, in accordance with some embodiments of the disclosure. [0042] A first through silicon via (TSV) 140 is formed through the first substrate 102, and the …
FIG. 2B, in accordance with some embodiments of the disclosure. More specifically, the first TSV 140 is formed over the first portion 110 a of the first graphene …
FIG. 3E, in accordance with some embodiments of the disclosure. The second TSV 240 is electrically connected to the first TSV 140. [0067] Afterwards, a third …
FIG. 10, in accordance with some embodiments of the disclosure. In some embodiments, the substrate 102 is thinned by a chemical mechanical polishing (CMP) …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for forming a semiconductor device structure, comprising: forming an interconnect structure over a first substrate, wherein forming the interconnect structure over the first substrate comprises: forming a first dielectric layer over the first substrate, wherein the first dielectric layer has a plurality of openings; forming a catalyst layer over the first dielectric layer and in the openings; forming a graphene layer on the catalyst layer, wherein the catalyst layer is surrounded by the graphene layer; forming an insulating layer on the graphene layer; patterning the insulating layer, the graphene layer and the catalyst layer, wherein the graphene layer is formed in the openings, and the insulating layer is formed on the graphene layer and in the openings; and removing the catalyst layer to leave a portion of the graphene layer in the first dielectric layer and on the first dielectric layer, wherein the graphene layer comprises a first portion formed in the first dielectric layer and a second portion formed over the first dielectric layer. Original
The method for forming the semiconductor device structure as claimed in claim 1, before forming the graphene layer on the catalyst layer, further comprising: patterning the catalyst layer to form a plurality of trenches, wherein each of the openings has a first width, each of the trenches has a second width, and the first width is greater than the second width. Original
The method for forming the semiconductor device structure as claimed in claim 1, before removing the catalyst layer, further comprising: removing a portion of the insulating layer to expose a portion of the graphene layer; and removing the exposed portion of the graphene layer. Original
The method for forming the semiconductor device structure as claimed in claim 1, further comprising: bonding the first substrate to a second substrate, wherein a transistor device structure is pre-formed over the second substrate. Original
The method for forming the semiconductor device structure as claimed in claim 1, further comprising: forming a second substrate below the first substrate; and forming a transistor device structure below the second substrate; forming a through-silicon via (TSV) through the second substrate and a portion of the interconnect structure, wherein the TSV is electrically connected to the first portion of the graphene layer. Previously presented
The method for forming the semiconductor device structure as claimed in claim 1, further comprising: forming a second dielectric layer below the first dielectric layer; and forming a second graphene layer in and below the second dielectric layer, wherein a portion of the second graphene layer interfaces with the second portion of the first graphene layer. Original
The method for forming the semiconductor device structure as claimed in claim 1, further comprising: forming a first TSV in the first substrate, wherein the first TSV is on the first graphene layer. Original
The method for forming the semiconductor device structure as claimed in claim 1, further comprising: performing an annealing process on the first graphene layer, wherein no active device is formed in the first substrate before performing the annealing process. Original
A method for forming a semiconductor device structure, comprising: forming a first dielectric layer over a first substrate, wherein the first dielectric layer has a plurality of openings; forming a catalyst layer over the first dielectric layer and in the openings; patterning the catalyst layer to form a plurality of trenches; forming a U-shaped graphene layer on the catalyst layer and in the trenches; forming an insulating layer in a recessed portion of the U-shaped graphene layer; removing the catalyst layer to leave a portion of the U-shaped graphene layer in the first dielectric layer and on the first dielectric layer, wherein the U-shaped graphene layer comprises a first portion formed in the first dielectric layer and a second portion formed over the first dielectric layer. Original
The method for forming the semiconductor device structure as claimed in claim 11, further comprising: forming a through-silicon via (TSV) in the first substrate, wherein a portion of the first graphene layer is in direct contact with the TSV. Previously presented
The method for forming the semiconductor device structure as claimed in claim 11, further comprising: forming a second dielectric layer below the first dielectric layer; and forming a second graphene layer in and below the second dielectric layer, wherein a portion of the second graphene layer interfaces with the second portion of the first graphene layer. Original
The method for forming the semiconductor device structure as claimed in claim 11, further comprising: forming a through-silicon via (TSV) over a front-side of the first substrate, wherein the insulating layer is in direct contact with the TSV. Withdrawn
The method for forming the semiconductor device structure as claimed in claim 11, further comprising: forming a second substrate below the first substrate; and forming a transistor device structure below the second substrate. Previously presented
The method for forming the semiconductor device structure as claimed in claim 11, further comprising: performing an annealing process on the first graphene layer, wherein no active device is formed in the first substrate before performing the annealing process. Previously presented
A method for forming a semiconductor device structure, comprising: forming a first dielectric layer over a first substrate, wherein the dielectric layer has a plurality of openings; forming a catalyst layer over the first dielectric layer and in the openings; forming a first graphene layer in the openings and on the catalyst layer, wherein the first graphene layer is formed on and below the catalyst layer to surround the catalyst layer; forming an insulating layer in the first graphene layer; forming a second dielectric layer over the first dielectric layer; and forming a second graphene layer in and over the second dielectric layer, wherein a portion of the second graphene layer interfaces with a portion of the first graphene layer. Currently amended
The method for forming the semiconductor device structure as claimed in claim 17, further comprising: forming a third dielectric layer over the second dielectric layer; and forming a third graphene layer in and over the third dielectric layer, wherein a portion of the third graphene layer interfaces with a portion of the second graphene layer. Previously presented
The method for forming the semiconductor device structure as claimed in claim 17, further comprising: forming a through-silicon via (TSV) in the first substrate, wherein the TSV is in direct contact with another portion of the first graphene layer. Previously presented
The method for forming the semiconductor device structure as claimed in claim 17, wherein the first graphene layer is in direct contact with the first dielectric layer after forming the first graphene layer in the openings. New
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
graphene interconnect structure
transistor device structure on second substrate
No layer stack recorded.
Materials described outside the worked examples.
graphene layer
C
catalyst layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 P, in accordance with some embodiments of the disclosure. [0042] A first through silicon via (TSV) 140 is formed through the first substrate 102, and the …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 100–300 nm | — |
Duration | 10–180 minutes |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,818,596Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 P, in accordance with some embodiments of the disclosure. [0042] A first through silicon via (TSV) 140 is formed through the first substrate 102, and the …
FIG. 2B, in accordance with some embodiments of the disclosure. More specifically, the first TSV 140 is formed over the first portion 110 a of the first graphene …
FIG. 3E, in accordance with some embodiments of the disclosure. The second TSV 240 is electrically connected to the first TSV 140. [0067] Afterwards, a third …
FIG. 10, in accordance with some embodiments of the disclosure. In some embodiments, the substrate 102 is thinned by a chemical mechanical polishing (CMP) …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for forming a semiconductor device structure, comprising: forming an interconnect structure over a first substrate, wherein forming the interconnect structure over the first substrate comprises: forming a first dielectric layer over the first substrate, wherein the first dielectric layer has a plurality of openings; forming a catalyst layer over the first dielectric layer and in the openings; forming a graphene layer on the catalyst layer, wherein the catalyst layer is surrounded by the graphene layer; forming an insulating layer on the graphene layer; patterning the insulating layer, the graphene layer and the catalyst layer, wherein the graphene layer is formed in the openings, and the insulating layer is formed on the graphene layer and in the openings; and removing the catalyst layer to leave a portion of the graphene layer in the first dielectric layer and on the first dielectric layer, wherein the graphene layer comprises a first portion formed in the first dielectric layer and a second portion formed over the first dielectric layer. Original
The method for forming the semiconductor device structure as claimed in claim 1, before forming the graphene layer on the catalyst layer, further comprising: patterning the catalyst layer to form a plurality of trenches, wherein each of the openings has a first width, each of the trenches has a second width, and the first width is greater than the second width. Original
The method for forming the semiconductor device structure as claimed in claim 1, before removing the catalyst layer, further comprising: removing a portion of the insulating layer to expose a portion of the graphene layer; and removing the exposed portion of the graphene layer. Original
The method for forming the semiconductor device structure as claimed in claim 1, further comprising: bonding the first substrate to a second substrate, wherein a transistor device structure is pre-formed over the second substrate. Original
The method for forming the semiconductor device structure as claimed in claim 1, further comprising: forming a second substrate below the first substrate; and forming a transistor device structure below the second substrate; forming a through-silicon via (TSV) through the second substrate and a portion of the interconnect structure, wherein the TSV is electrically connected to the first portion of the graphene layer. Previously presented
The method for forming the semiconductor device structure as claimed in claim 1, further comprising: forming a second dielectric layer below the first dielectric layer; and forming a second graphene layer in and below the second dielectric layer, wherein a portion of the second graphene layer interfaces with the second portion of the first graphene layer. Original
The method for forming the semiconductor device structure as claimed in claim 1, further comprising: forming a first TSV in the first substrate, wherein the first TSV is on the first graphene layer. Original
The method for forming the semiconductor device structure as claimed in claim 1, further comprising: performing an annealing process on the first graphene layer, wherein no active device is formed in the first substrate before performing the annealing process. Original
A method for forming a semiconductor device structure, comprising: forming a first dielectric layer over a first substrate, wherein the first dielectric layer has a plurality of openings; forming a catalyst layer over the first dielectric layer and in the openings; patterning the catalyst layer to form a plurality of trenches; forming a U-shaped graphene layer on the catalyst layer and in the trenches; forming an insulating layer in a recessed portion of the U-shaped graphene layer; removing the catalyst layer to leave a portion of the U-shaped graphene layer in the first dielectric layer and on the first dielectric layer, wherein the U-shaped graphene layer comprises a first portion formed in the first dielectric layer and a second portion formed over the first dielectric layer. Original
The method for forming the semiconductor device structure as claimed in claim 11, further comprising: forming a through-silicon via (TSV) in the first substrate, wherein a portion of the first graphene layer is in direct contact with the TSV. Previously presented
The method for forming the semiconductor device structure as claimed in claim 11, further comprising: forming a second dielectric layer below the first dielectric layer; and forming a second graphene layer in and below the second dielectric layer, wherein a portion of the second graphene layer interfaces with the second portion of the first graphene layer. Original
The method for forming the semiconductor device structure as claimed in claim 11, further comprising: forming a through-silicon via (TSV) over a front-side of the first substrate, wherein the insulating layer is in direct contact with the TSV. Withdrawn
The method for forming the semiconductor device structure as claimed in claim 11, further comprising: forming a second substrate below the first substrate; and forming a transistor device structure below the second substrate. Previously presented
The method for forming the semiconductor device structure as claimed in claim 11, further comprising: performing an annealing process on the first graphene layer, wherein no active device is formed in the first substrate before performing the annealing process. Previously presented
A method for forming a semiconductor device structure, comprising: forming a first dielectric layer over a first substrate, wherein the dielectric layer has a plurality of openings; forming a catalyst layer over the first dielectric layer and in the openings; forming a first graphene layer in the openings and on the catalyst layer, wherein the first graphene layer is formed on and below the catalyst layer to surround the catalyst layer; forming an insulating layer in the first graphene layer; forming a second dielectric layer over the first dielectric layer; and forming a second graphene layer in and over the second dielectric layer, wherein a portion of the second graphene layer interfaces with a portion of the first graphene layer. Currently amended
The method for forming the semiconductor device structure as claimed in claim 17, further comprising: forming a third dielectric layer over the second dielectric layer; and forming a third graphene layer in and over the third dielectric layer, wherein a portion of the third graphene layer interfaces with a portion of the second graphene layer. Previously presented
The method for forming the semiconductor device structure as claimed in claim 17, further comprising: forming a through-silicon via (TSV) in the first substrate, wherein the TSV is in direct contact with another portion of the first graphene layer. Previously presented
The method for forming the semiconductor device structure as claimed in claim 17, wherein the first graphene layer is in direct contact with the first dielectric layer after forming the first graphene layer in the openings. New
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
graphene interconnect structure
transistor device structure on second substrate
No layer stack recorded.
Materials described outside the worked examples.
graphene layer
C
catalyst layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 P, in accordance with some embodiments of the disclosure. [0042] A first through silicon via (TSV) 140 is formed through the first substrate 102, and the …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 100–300 nm | — |
Duration | 10–180 minutes |
Related documents with shared materials, methods, properties, or citations.
U-shaped graphene interconnect structure
insulating layer
first dielectric layer
silicon oxide
SiOx
silicon nitride
SixNy
silicon oxynitride
SiON
copper
Cu
cobalt
Co
nickel
Ni
iron
Fe
zinc
Zn
methane
CH₄
FIG. 2B, in accordance with some embodiments of the disclosure. More specifically, the first TSV 140 is formed over the first portion 110 a of the first graphene …
FIG. 2B, in accordance with some embodiments of the disclosure. More specifically, the first TSV 140 is formed over the first portion 110 a of the first graphene …
FIG. 3E, in accordance with some embodiments of the disclosure. The second TSV 240 is electrically connected to the first TSV 140. [0067] Afterwards, a third …
FIG. 10, in accordance with some embodiments of the disclosure. In some embodiments, the substrate 102 is thinned by a chemical mechanical polishing (CMP) …
| — |
Duration | ≤ 10 minutes | — |
Thickness | ≥ 300 nm | — |
Duration | ≥ 180 minutes | — |
U-shaped graphene interconnect structure
insulating layer
first dielectric layer
silicon oxide
SiOx
silicon nitride
SixNy
silicon oxynitride
SiON
copper
Cu
cobalt
Co
nickel
Ni
iron
Fe
zinc
Zn
methane
CH₄
FIG. 2B, in accordance with some embodiments of the disclosure. More specifically, the first TSV 140 is formed over the first portion 110 a of the first graphene …
FIG. 2B, in accordance with some embodiments of the disclosure. More specifically, the first TSV 140 is formed over the first portion 110 a of the first graphene …
FIG. 3E, in accordance with some embodiments of the disclosure. The second TSV 240 is electrically connected to the first TSV 140. [0067] Afterwards, a third …
FIG. 10, in accordance with some embodiments of the disclosure. In some embodiments, the substrate 102 is thinned by a chemical mechanical polishing (CMP) …
| — |
Duration | ≤ 10 minutes | — |
Thickness | ≥ 300 nm | — |
Duration | ≥ 180 minutes | — |
U-shaped graphene interconnect structure
insulating layer
first dielectric layer
silicon oxide
SiOx
silicon nitride
SixNy
silicon oxynitride
SiON
copper
Cu
cobalt
Co
nickel
Ni
iron
Fe
zinc
Zn
methane
CH₄
FIG. 2B, in accordance with some embodiments of the disclosure. More specifically, the first TSV 140 is formed over the first portion 110 a of the first graphene …
FIG. 2B, in accordance with some embodiments of the disclosure. More specifically, the first TSV 140 is formed over the first portion 110 a of the first graphene …
FIG. 3E, in accordance with some embodiments of the disclosure. The second TSV 240 is electrically connected to the first TSV 140. [0067] Afterwards, a third …
FIG. 10, in accordance with some embodiments of the disclosure. In some embodiments, the substrate 102 is thinned by a chemical mechanical polishing (CMP) …
| — |
Duration | ≤ 10 minutes | — |
Thickness | ≥ 300 nm | — |
Duration | ≥ 180 minutes | — |
U-shaped graphene interconnect structure
insulating layer
first dielectric layer
silicon oxide
SiOx
silicon nitride
SixNy
silicon oxynitride
SiON
copper
Cu
cobalt
Co
nickel
Ni
iron
Fe
zinc
Zn
methane
CH₄
FIG. 2B, in accordance with some embodiments of the disclosure. More specifically, the first TSV 140 is formed over the first portion 110 a of the first graphene …
FIG. 2B, in accordance with some embodiments of the disclosure. More specifically, the first TSV 140 is formed over the first portion 110 a of the first graphene …
FIG. 3E, in accordance with some embodiments of the disclosure. The second TSV 240 is electrically connected to the first TSV 140. [0067] Afterwards, a third …
FIG. 10, in accordance with some embodiments of the disclosure. In some embodiments, the substrate 102 is thinned by a chemical mechanical polishing (CMP) …
| — |
Duration | ≤ 10 minutes | — |
Thickness | ≥ 300 nm | — |
Duration | ≥ 180 minutes | — |